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/*
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* QEMU 16550A UART emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2008 Citrix Systems, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "serial.h" |
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#include "qemu-char.h" |
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#include "qemu-timer.h" |
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//#define DEBUG_SERIAL
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
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#define UART_IIR_CTI 0x0C /* Character Timeout Indication */ |
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#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ |
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#define UART_IIR_FE 0xC0 /* Fifo enabled */ |
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
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#define UART_MCR_OUT2 0x08 /* Out2 complement */ |
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#define UART_MCR_OUT1 0x04 /* Out1 complement */ |
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#define UART_MCR_RTS 0x02 /* RTS complement */ |
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#define UART_MCR_DTR 0x01 /* DTR complement */ |
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/*
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* These are the definitions for the Modem Status Register
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*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
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#define UART_MSR_RI 0x40 /* Ring Indicator */ |
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#define UART_MSR_DSR 0x20 /* Data Set Ready */ |
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#define UART_MSR_CTS 0x10 /* Clear to Send */ |
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#define UART_MSR_DDCD 0x08 /* Delta DCD */ |
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
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#define UART_MSR_DDSR 0x02 /* Delta DSR */ |
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#define UART_MSR_DCTS 0x01 /* Delta CTS */ |
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
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#define UART_LSR_FE 0x08 /* Frame error indicator */ |
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#define UART_LSR_PE 0x04 /* Parity error indicator */ |
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#define UART_LSR_OE 0x02 /* Overrun error indicator */ |
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#define UART_LSR_DR 0x01 /* Receiver data ready */ |
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#define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ |
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/* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
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#define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ |
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#define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ |
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#define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ |
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#define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ |
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#define UART_FCR_DMS 0x08 /* DMA Mode Select */ |
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#define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ |
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#define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ |
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#define UART_FCR_FE 0x01 /* FIFO Enable */ |
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#define XMIT_FIFO 0 |
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#define RECV_FIFO 1 |
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#define MAX_XMIT_RETRY 4 |
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#ifdef DEBUG_SERIAL
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...) \
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do {} while (0) |
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#endif
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static void serial_receive1(void *opaque, const uint8_t *buf, int size); |
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static void fifo_clear(SerialState *s, int fifo) |
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{ |
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SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
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memset(f->data, 0, UART_FIFO_LENGTH);
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f->count = 0;
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f->head = 0;
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f->tail = 0;
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} |
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static int fifo_put(SerialState *s, int fifo, uint8_t chr) |
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{ |
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SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
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/* Receive overruns do not overwrite FIFO contents. */
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if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) {
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f->data[f->head++] = chr; |
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if (f->head == UART_FIFO_LENGTH)
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f->head = 0;
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} |
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if (f->count < UART_FIFO_LENGTH)
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f->count++; |
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else if (fifo == RECV_FIFO) |
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s->lsr |= UART_LSR_OE; |
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return 1; |
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} |
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static uint8_t fifo_get(SerialState *s, int fifo) |
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{ |
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SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
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uint8_t c; |
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if(f->count == 0) |
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return 0; |
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c = f->data[f->tail++]; |
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if (f->tail == UART_FIFO_LENGTH)
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f->tail = 0;
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f->count--; |
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return c;
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} |
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static void serial_update_irq(SerialState *s) |
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{ |
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uint8_t tmp_iir = UART_IIR_NO_INT; |
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if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
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tmp_iir = UART_IIR_RLSI; |
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} else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { |
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/* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
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* this is not in the specification but is observed on existing
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* hardware. */
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tmp_iir = UART_IIR_CTI; |
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} else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && |
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(!(s->fcr & UART_FCR_FE) || |
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s->recv_fifo.count >= s->recv_fifo.itl)) { |
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tmp_iir = UART_IIR_RDI; |
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} else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { |
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tmp_iir = UART_IIR_THRI; |
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} else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { |
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tmp_iir = UART_IIR_MSI; |
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} |
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s->iir = tmp_iir | (s->iir & 0xF0);
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if (tmp_iir != UART_IIR_NO_INT) {
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qemu_irq_raise(s->irq); |
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} else {
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qemu_irq_lower(s->irq); |
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} |
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} |
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static void serial_update_parameters(SerialState *s) |
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{ |
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int speed, parity, data_bits, stop_bits, frame_size;
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QEMUSerialSetParams ssp; |
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if (s->divider == 0) |
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return;
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/* Start bit. */
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frame_size = 1;
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if (s->lcr & 0x08) { |
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/* Parity bit. */
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frame_size++; |
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if (s->lcr & 0x10) |
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parity = 'E';
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else
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parity = 'O';
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} else {
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parity = 'N';
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} |
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if (s->lcr & 0x04) |
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stop_bits = 2;
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else
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stop_bits = 1;
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data_bits = (s->lcr & 0x03) + 5; |
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frame_size += data_bits + stop_bits; |
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speed = s->baudbase / s->divider; |
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ssp.speed = speed; |
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ssp.parity = parity; |
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ssp.data_bits = data_bits; |
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ssp.stop_bits = stop_bits; |
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s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; |
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
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DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
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speed, parity, data_bits, stop_bits); |
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} |
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static void serial_update_msl(SerialState *s) |
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{ |
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uint8_t omsr; |
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int flags;
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qemu_del_timer(s->modem_status_poll); |
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if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
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s->poll_msl = -1;
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return;
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} |
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omsr = s->msr; |
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s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; |
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s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; |
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s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; |
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s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; |
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if (s->msr != omsr) {
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/* Set delta bits */
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s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); |
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/* UART_MSR_TERI only if change was from 1 -> 0 */
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if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
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s->msr &= ~UART_MSR_TERI; |
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serial_update_irq(s); |
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} |
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/* The real 16550A apparently has a 250ns response latency to line status changes.
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We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
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if (s->poll_msl)
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qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100);
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} |
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static void serial_xmit(void *opaque) |
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{ |
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SerialState *s = opaque; |
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uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock); |
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if (s->tsr_retry <= 0) { |
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if (s->fcr & UART_FCR_FE) {
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s->tsr = fifo_get(s,XMIT_FIFO); |
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if (!s->xmit_fifo.count)
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s->lsr |= UART_LSR_THRE; |
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} else if ((s->lsr & UART_LSR_THRE)) { |
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return;
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} else {
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s->tsr = s->thr; |
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s->lsr |= UART_LSR_THRE; |
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s->lsr &= ~UART_LSR_TEMT; |
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} |
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} |
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if (s->mcr & UART_MCR_LOOP) {
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/* in loopback mode, say that we just received a char */
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serial_receive1(s, &s->tsr, 1);
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} else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) { |
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if ((s->tsr_retry >= 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) { |
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s->tsr_retry++; |
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qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time); |
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return;
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} else if (s->poll_msl < 0) { |
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/* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
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drop any further failed writes instantly, until we get one that goes through.
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This is to prevent guests that log to unconnected pipes or pty's from stalling. */
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s->tsr_retry = -1;
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} |
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} |
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else {
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s->tsr_retry = 0;
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} |
295 |
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s->last_xmit_ts = qemu_get_clock_ns(vm_clock); |
297 |
if (!(s->lsr & UART_LSR_THRE))
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qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time); |
299 |
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if (s->lsr & UART_LSR_THRE) {
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s->lsr |= UART_LSR_TEMT; |
302 |
s->thr_ipending = 1;
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serial_update_irq(s); |
304 |
} |
305 |
} |
306 |
|
307 |
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static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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SerialState *s = opaque; |
311 |
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addr &= 7;
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DPRINTF("write addr=0x%02x val=0x%02x\n", addr, val);
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switch(addr) {
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default:
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case 0: |
317 |
if (s->lcr & UART_LCR_DLAB) {
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s->divider = (s->divider & 0xff00) | val;
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serial_update_parameters(s); |
320 |
} else {
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s->thr = (uint8_t) val; |
322 |
if(s->fcr & UART_FCR_FE) {
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fifo_put(s, XMIT_FIFO, s->thr); |
324 |
s->thr_ipending = 0;
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s->lsr &= ~UART_LSR_TEMT; |
326 |
s->lsr &= ~UART_LSR_THRE; |
327 |
serial_update_irq(s); |
328 |
} else {
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s->thr_ipending = 0;
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s->lsr &= ~UART_LSR_THRE; |
331 |
serial_update_irq(s); |
332 |
} |
333 |
serial_xmit(s); |
334 |
} |
335 |
break;
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case 1: |
337 |
if (s->lcr & UART_LCR_DLAB) {
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s->divider = (s->divider & 0x00ff) | (val << 8); |
339 |
serial_update_parameters(s); |
340 |
} else {
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341 |
s->ier = val & 0x0f;
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342 |
/* If the backend device is a real serial port, turn polling of the modem
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status lines on physical port on or off depending on UART_IER_MSI state */
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if (s->poll_msl >= 0) { |
345 |
if (s->ier & UART_IER_MSI) {
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s->poll_msl = 1;
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serial_update_msl(s); |
348 |
} else {
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qemu_del_timer(s->modem_status_poll); |
350 |
s->poll_msl = 0;
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} |
352 |
} |
353 |
if (s->lsr & UART_LSR_THRE) {
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s->thr_ipending = 1;
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serial_update_irq(s); |
356 |
} |
357 |
} |
358 |
break;
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359 |
case 2: |
360 |
val = val & 0xFF;
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361 |
|
362 |
if (s->fcr == val)
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break;
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364 |
|
365 |
/* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
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366 |
if ((val ^ s->fcr) & UART_FCR_FE)
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val |= UART_FCR_XFR | UART_FCR_RFR; |
368 |
|
369 |
/* FIFO clear */
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370 |
|
371 |
if (val & UART_FCR_RFR) {
|
372 |
qemu_del_timer(s->fifo_timeout_timer); |
373 |
s->timeout_ipending=0;
|
374 |
fifo_clear(s,RECV_FIFO); |
375 |
} |
376 |
|
377 |
if (val & UART_FCR_XFR) {
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378 |
fifo_clear(s,XMIT_FIFO); |
379 |
} |
380 |
|
381 |
if (val & UART_FCR_FE) {
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382 |
s->iir |= UART_IIR_FE; |
383 |
/* Set RECV_FIFO trigger Level */
|
384 |
switch (val & 0xC0) { |
385 |
case UART_FCR_ITL_1:
|
386 |
s->recv_fifo.itl = 1;
|
387 |
break;
|
388 |
case UART_FCR_ITL_2:
|
389 |
s->recv_fifo.itl = 4;
|
390 |
break;
|
391 |
case UART_FCR_ITL_3:
|
392 |
s->recv_fifo.itl = 8;
|
393 |
break;
|
394 |
case UART_FCR_ITL_4:
|
395 |
s->recv_fifo.itl = 14;
|
396 |
break;
|
397 |
} |
398 |
} else
|
399 |
s->iir &= ~UART_IIR_FE; |
400 |
|
401 |
/* Set fcr - or at least the bits in it that are supposed to "stick" */
|
402 |
s->fcr = val & 0xC9;
|
403 |
serial_update_irq(s); |
404 |
break;
|
405 |
case 3: |
406 |
{ |
407 |
int break_enable;
|
408 |
s->lcr = val; |
409 |
serial_update_parameters(s); |
410 |
break_enable = (val >> 6) & 1; |
411 |
if (break_enable != s->last_break_enable) {
|
412 |
s->last_break_enable = break_enable; |
413 |
qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
414 |
&break_enable); |
415 |
} |
416 |
} |
417 |
break;
|
418 |
case 4: |
419 |
{ |
420 |
int flags;
|
421 |
int old_mcr = s->mcr;
|
422 |
s->mcr = val & 0x1f;
|
423 |
if (val & UART_MCR_LOOP)
|
424 |
break;
|
425 |
|
426 |
if (s->poll_msl >= 0 && old_mcr != s->mcr) { |
427 |
|
428 |
qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); |
429 |
|
430 |
flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); |
431 |
|
432 |
if (val & UART_MCR_RTS)
|
433 |
flags |= CHR_TIOCM_RTS; |
434 |
if (val & UART_MCR_DTR)
|
435 |
flags |= CHR_TIOCM_DTR; |
436 |
|
437 |
qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); |
438 |
/* Update the modem status after a one-character-send wait-time, since there may be a response
|
439 |
from the device/computer at the other end of the serial line */
|
440 |
qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time); |
441 |
} |
442 |
} |
443 |
break;
|
444 |
case 5: |
445 |
break;
|
446 |
case 6: |
447 |
break;
|
448 |
case 7: |
449 |
s->scr = val; |
450 |
break;
|
451 |
} |
452 |
} |
453 |
|
454 |
static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
455 |
{ |
456 |
SerialState *s = opaque; |
457 |
uint32_t ret; |
458 |
|
459 |
addr &= 7;
|
460 |
switch(addr) {
|
461 |
default:
|
462 |
case 0: |
463 |
if (s->lcr & UART_LCR_DLAB) {
|
464 |
ret = s->divider & 0xff;
|
465 |
} else {
|
466 |
if(s->fcr & UART_FCR_FE) {
|
467 |
ret = fifo_get(s,RECV_FIFO); |
468 |
if (s->recv_fifo.count == 0) |
469 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
470 |
else
|
471 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
|
472 |
s->timeout_ipending = 0;
|
473 |
} else {
|
474 |
ret = s->rbr; |
475 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
476 |
} |
477 |
serial_update_irq(s); |
478 |
if (!(s->mcr & UART_MCR_LOOP)) {
|
479 |
/* in loopback mode, don't receive any data */
|
480 |
qemu_chr_accept_input(s->chr); |
481 |
} |
482 |
} |
483 |
break;
|
484 |
case 1: |
485 |
if (s->lcr & UART_LCR_DLAB) {
|
486 |
ret = (s->divider >> 8) & 0xff; |
487 |
} else {
|
488 |
ret = s->ier; |
489 |
} |
490 |
break;
|
491 |
case 2: |
492 |
ret = s->iir; |
493 |
if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
|
494 |
s->thr_ipending = 0;
|
495 |
serial_update_irq(s); |
496 |
} |
497 |
break;
|
498 |
case 3: |
499 |
ret = s->lcr; |
500 |
break;
|
501 |
case 4: |
502 |
ret = s->mcr; |
503 |
break;
|
504 |
case 5: |
505 |
ret = s->lsr; |
506 |
/* Clear break and overrun interrupts */
|
507 |
if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
|
508 |
s->lsr &= ~(UART_LSR_BI|UART_LSR_OE); |
509 |
serial_update_irq(s); |
510 |
} |
511 |
break;
|
512 |
case 6: |
513 |
if (s->mcr & UART_MCR_LOOP) {
|
514 |
/* in loopback, the modem output pins are connected to the
|
515 |
inputs */
|
516 |
ret = (s->mcr & 0x0c) << 4; |
517 |
ret |= (s->mcr & 0x02) << 3; |
518 |
ret |= (s->mcr & 0x01) << 5; |
519 |
} else {
|
520 |
if (s->poll_msl >= 0) |
521 |
serial_update_msl(s); |
522 |
ret = s->msr; |
523 |
/* Clear delta bits & msr int after read, if they were set */
|
524 |
if (s->msr & UART_MSR_ANY_DELTA) {
|
525 |
s->msr &= 0xF0;
|
526 |
serial_update_irq(s); |
527 |
} |
528 |
} |
529 |
break;
|
530 |
case 7: |
531 |
ret = s->scr; |
532 |
break;
|
533 |
} |
534 |
DPRINTF("read addr=0x%02x val=0x%02x\n", addr, ret);
|
535 |
return ret;
|
536 |
} |
537 |
|
538 |
static int serial_can_receive(SerialState *s) |
539 |
{ |
540 |
if(s->fcr & UART_FCR_FE) {
|
541 |
if(s->recv_fifo.count < UART_FIFO_LENGTH)
|
542 |
/* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
|
543 |
advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
|
544 |
effectively overriding the ITL that the guest has set. */
|
545 |
return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1; |
546 |
else
|
547 |
return 0; |
548 |
} else {
|
549 |
return !(s->lsr & UART_LSR_DR);
|
550 |
} |
551 |
} |
552 |
|
553 |
static void serial_receive_break(SerialState *s) |
554 |
{ |
555 |
s->rbr = 0;
|
556 |
/* When the LSR_DR is set a null byte is pushed into the fifo */
|
557 |
fifo_put(s, RECV_FIFO, '\0');
|
558 |
s->lsr |= UART_LSR_BI | UART_LSR_DR; |
559 |
serial_update_irq(s); |
560 |
} |
561 |
|
562 |
/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
|
563 |
static void fifo_timeout_int (void *opaque) { |
564 |
SerialState *s = opaque; |
565 |
if (s->recv_fifo.count) {
|
566 |
s->timeout_ipending = 1;
|
567 |
serial_update_irq(s); |
568 |
} |
569 |
} |
570 |
|
571 |
static int serial_can_receive1(void *opaque) |
572 |
{ |
573 |
SerialState *s = opaque; |
574 |
return serial_can_receive(s);
|
575 |
} |
576 |
|
577 |
static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
578 |
{ |
579 |
SerialState *s = opaque; |
580 |
|
581 |
if (s->wakeup) {
|
582 |
qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER); |
583 |
} |
584 |
if(s->fcr & UART_FCR_FE) {
|
585 |
int i;
|
586 |
for (i = 0; i < size; i++) { |
587 |
fifo_put(s, RECV_FIFO, buf[i]); |
588 |
} |
589 |
s->lsr |= UART_LSR_DR; |
590 |
/* call the timeout receive callback in 4 char transmit time */
|
591 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
|
592 |
} else {
|
593 |
if (s->lsr & UART_LSR_DR)
|
594 |
s->lsr |= UART_LSR_OE; |
595 |
s->rbr = buf[0];
|
596 |
s->lsr |= UART_LSR_DR; |
597 |
} |
598 |
serial_update_irq(s); |
599 |
} |
600 |
|
601 |
static void serial_event(void *opaque, int event) |
602 |
{ |
603 |
SerialState *s = opaque; |
604 |
DPRINTF("event %x\n", event);
|
605 |
if (event == CHR_EVENT_BREAK)
|
606 |
serial_receive_break(s); |
607 |
} |
608 |
|
609 |
static void serial_pre_save(void *opaque) |
610 |
{ |
611 |
SerialState *s = opaque; |
612 |
s->fcr_vmstate = s->fcr; |
613 |
} |
614 |
|
615 |
static int serial_post_load(void *opaque, int version_id) |
616 |
{ |
617 |
SerialState *s = opaque; |
618 |
|
619 |
if (version_id < 3) { |
620 |
s->fcr_vmstate = 0;
|
621 |
} |
622 |
/* Initialize fcr via setter to perform essential side-effects */
|
623 |
serial_ioport_write(s, 0x02, s->fcr_vmstate);
|
624 |
serial_update_parameters(s); |
625 |
return 0; |
626 |
} |
627 |
|
628 |
const VMStateDescription vmstate_serial = {
|
629 |
.name = "serial",
|
630 |
.version_id = 3,
|
631 |
.minimum_version_id = 2,
|
632 |
.pre_save = serial_pre_save, |
633 |
.post_load = serial_post_load, |
634 |
.fields = (VMStateField []) { |
635 |
VMSTATE_UINT16_V(divider, SerialState, 2),
|
636 |
VMSTATE_UINT8(rbr, SerialState), |
637 |
VMSTATE_UINT8(ier, SerialState), |
638 |
VMSTATE_UINT8(iir, SerialState), |
639 |
VMSTATE_UINT8(lcr, SerialState), |
640 |
VMSTATE_UINT8(mcr, SerialState), |
641 |
VMSTATE_UINT8(lsr, SerialState), |
642 |
VMSTATE_UINT8(msr, SerialState), |
643 |
VMSTATE_UINT8(scr, SerialState), |
644 |
VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
|
645 |
VMSTATE_END_OF_LIST() |
646 |
} |
647 |
}; |
648 |
|
649 |
static void serial_reset(void *opaque) |
650 |
{ |
651 |
SerialState *s = opaque; |
652 |
|
653 |
s->rbr = 0;
|
654 |
s->ier = 0;
|
655 |
s->iir = UART_IIR_NO_INT; |
656 |
s->lcr = 0;
|
657 |
s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
658 |
s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; |
659 |
/* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
|
660 |
s->divider = 0x0C;
|
661 |
s->mcr = UART_MCR_OUT2; |
662 |
s->scr = 0;
|
663 |
s->tsr_retry = 0;
|
664 |
s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10; |
665 |
s->poll_msl = 0;
|
666 |
|
667 |
fifo_clear(s,RECV_FIFO); |
668 |
fifo_clear(s,XMIT_FIFO); |
669 |
|
670 |
s->last_xmit_ts = qemu_get_clock_ns(vm_clock); |
671 |
|
672 |
s->thr_ipending = 0;
|
673 |
s->last_break_enable = 0;
|
674 |
qemu_irq_lower(s->irq); |
675 |
} |
676 |
|
677 |
void serial_init_core(SerialState *s)
|
678 |
{ |
679 |
if (!s->chr) {
|
680 |
fprintf(stderr, "Can't create serial device, empty char device\n");
|
681 |
exit(1);
|
682 |
} |
683 |
|
684 |
s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s); |
685 |
|
686 |
s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s); |
687 |
s->transmit_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_xmit, s); |
688 |
|
689 |
qemu_register_reset(serial_reset, s); |
690 |
|
691 |
qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, |
692 |
serial_event, s); |
693 |
} |
694 |
|
695 |
void serial_exit_core(SerialState *s)
|
696 |
{ |
697 |
qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, NULL); |
698 |
qemu_unregister_reset(serial_reset, s); |
699 |
} |
700 |
|
701 |
/* Change the main reference oscillator frequency. */
|
702 |
void serial_set_frequency(SerialState *s, uint32_t frequency)
|
703 |
{ |
704 |
s->baudbase = frequency; |
705 |
serial_update_parameters(s); |
706 |
} |
707 |
|
708 |
static const MemoryRegionPortio serial_portio[] = { |
709 |
{ 0, 8, 1, .read = serial_ioport_read, .write = serial_ioport_write }, |
710 |
PORTIO_END_OF_LIST() |
711 |
}; |
712 |
|
713 |
const MemoryRegionOps serial_io_ops = {
|
714 |
.old_portio = serial_portio |
715 |
}; |
716 |
|
717 |
SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
718 |
CharDriverState *chr) |
719 |
{ |
720 |
SerialState *s; |
721 |
|
722 |
s = g_malloc0(sizeof(SerialState));
|
723 |
|
724 |
s->irq = irq; |
725 |
s->baudbase = baudbase; |
726 |
s->chr = chr; |
727 |
serial_init_core(s); |
728 |
|
729 |
vmstate_register(NULL, base, &vmstate_serial, s);
|
730 |
|
731 |
register_ioport_write(base, 8, 1, serial_ioport_write, s); |
732 |
register_ioport_read(base, 8, 1, serial_ioport_read, s); |
733 |
return s;
|
734 |
} |
735 |
|
736 |
/* Memory mapped interface */
|
737 |
static uint64_t serial_mm_read(void *opaque, hwaddr addr, |
738 |
unsigned size)
|
739 |
{ |
740 |
SerialState *s = opaque; |
741 |
return serial_ioport_read(s, addr >> s->it_shift);
|
742 |
} |
743 |
|
744 |
static void serial_mm_write(void *opaque, hwaddr addr, |
745 |
uint64_t value, unsigned size)
|
746 |
{ |
747 |
SerialState *s = opaque; |
748 |
value &= ~0u >> (32 - (size * 8)); |
749 |
serial_ioport_write(s, addr >> s->it_shift, value); |
750 |
} |
751 |
|
752 |
static const MemoryRegionOps serial_mm_ops[3] = { |
753 |
[DEVICE_NATIVE_ENDIAN] = { |
754 |
.read = serial_mm_read, |
755 |
.write = serial_mm_write, |
756 |
.endianness = DEVICE_NATIVE_ENDIAN, |
757 |
}, |
758 |
[DEVICE_LITTLE_ENDIAN] = { |
759 |
.read = serial_mm_read, |
760 |
.write = serial_mm_write, |
761 |
.endianness = DEVICE_LITTLE_ENDIAN, |
762 |
}, |
763 |
[DEVICE_BIG_ENDIAN] = { |
764 |
.read = serial_mm_read, |
765 |
.write = serial_mm_write, |
766 |
.endianness = DEVICE_BIG_ENDIAN, |
767 |
}, |
768 |
}; |
769 |
|
770 |
SerialState *serial_mm_init(MemoryRegion *address_space, |
771 |
hwaddr base, int it_shift,
|
772 |
qemu_irq irq, int baudbase,
|
773 |
CharDriverState *chr, enum device_endian end)
|
774 |
{ |
775 |
SerialState *s; |
776 |
|
777 |
s = g_malloc0(sizeof(SerialState));
|
778 |
|
779 |
s->it_shift = it_shift; |
780 |
s->irq = irq; |
781 |
s->baudbase = baudbase; |
782 |
s->chr = chr; |
783 |
|
784 |
serial_init_core(s); |
785 |
vmstate_register(NULL, base, &vmstate_serial, s);
|
786 |
|
787 |
memory_region_init_io(&s->io, &serial_mm_ops[end], s, |
788 |
"serial", 8 << it_shift); |
789 |
memory_region_add_subregion(address_space, base, &s->io); |
790 |
|
791 |
serial_update_msl(s); |
792 |
return s;
|
793 |
} |