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/*
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* Alpha emulation cpu definitions for qemu.
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#if !defined (__CPU_ALPHA_H__)
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#define __CPU_ALPHA_H__
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#include "config.h" |
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#include "qemu-common.h" |
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#define TARGET_LONG_BITS 64 |
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#define CPUArchState struct CPUAlphaState |
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#include "cpu-defs.h" |
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#include "softfloat.h" |
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#define TARGET_HAS_ICE 1 |
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#define ELF_MACHINE EM_ALPHA
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#define ICACHE_LINE_SIZE 32 |
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#define DCACHE_LINE_SIZE 32 |
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#define TARGET_PAGE_BITS 13 |
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#ifdef CONFIG_USER_ONLY
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/* ??? The kernel likes to give addresses in high memory. If the host has
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more virtual address space than the guest, this can lead to impossible
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allocations. Honor the long-standing assumption that only kernel addrs
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are negative, but otherwise allow allocations anywhere. This could lead
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to tricky emulation problems for programs doing tagged addressing, but
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that's far fewer than encounter the impossible allocation problem. */
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#define TARGET_PHYS_ADDR_SPACE_BITS 63 |
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#define TARGET_VIRT_ADDR_SPACE_BITS 63 |
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#else
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/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
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#define TARGET_PHYS_ADDR_SPACE_BITS 44 |
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#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) |
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#endif
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/* Alpha major type */
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enum {
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ALPHA_EV3 = 1,
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ALPHA_EV4 = 2,
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ALPHA_SIM = 3,
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ALPHA_LCA = 4,
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ALPHA_EV5 = 5, /* 21164 */ |
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ALPHA_EV45 = 6, /* 21064A */ |
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ALPHA_EV56 = 7, /* 21164A */ |
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}; |
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/* EV4 minor type */
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enum {
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ALPHA_EV4_2 = 0,
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ALPHA_EV4_3 = 1,
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}; |
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/* LCA minor type */
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enum {
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ALPHA_LCA_1 = 1, /* 21066 */ |
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ALPHA_LCA_2 = 2, /* 20166 */ |
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ALPHA_LCA_3 = 3, /* 21068 */ |
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ALPHA_LCA_4 = 4, /* 21068 */ |
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ALPHA_LCA_5 = 5, /* 21066A */ |
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ALPHA_LCA_6 = 6, /* 21068A */ |
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}; |
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/* EV5 minor type */
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enum {
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ALPHA_EV5_1 = 1, /* Rev BA, CA */ |
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ALPHA_EV5_2 = 2, /* Rev DA, EA */ |
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ALPHA_EV5_3 = 3, /* Pass 3 */ |
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ALPHA_EV5_4 = 4, /* Pass 3.2 */ |
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ALPHA_EV5_5 = 5, /* Pass 4 */ |
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}; |
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/* EV45 minor type */
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enum {
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ALPHA_EV45_1 = 1, /* Pass 1 */ |
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ALPHA_EV45_2 = 2, /* Pass 1.1 */ |
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ALPHA_EV45_3 = 3, /* Pass 2 */ |
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}; |
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/* EV56 minor type */
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enum {
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ALPHA_EV56_1 = 1, /* Pass 1 */ |
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ALPHA_EV56_2 = 2, /* Pass 2 */ |
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}; |
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enum {
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IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */ |
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IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */ |
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IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */ |
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IMPLVER_21364 = 3, /* EV7 & EV79 */ |
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}; |
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enum {
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AMASK_BWX = 0x00000001,
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AMASK_FIX = 0x00000002,
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AMASK_CIX = 0x00000004,
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AMASK_MVI = 0x00000100,
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AMASK_TRAP = 0x00000200,
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AMASK_PREFETCH = 0x00001000,
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}; |
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enum {
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VAX_ROUND_NORMAL = 0,
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VAX_ROUND_CHOPPED, |
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}; |
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enum {
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IEEE_ROUND_NORMAL = 0,
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IEEE_ROUND_DYNAMIC, |
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IEEE_ROUND_PLUS, |
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IEEE_ROUND_MINUS, |
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IEEE_ROUND_CHOPPED, |
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}; |
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/* IEEE floating-point operations encoding */
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/* Trap mode */
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enum {
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FP_TRAP_I = 0x0,
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FP_TRAP_U = 0x1,
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FP_TRAP_S = 0x4,
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FP_TRAP_SU = 0x5,
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FP_TRAP_SUI = 0x7,
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}; |
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/* Rounding mode */
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enum {
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FP_ROUND_CHOPPED = 0x0,
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FP_ROUND_MINUS = 0x1,
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FP_ROUND_NORMAL = 0x2,
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FP_ROUND_DYNAMIC = 0x3,
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}; |
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/* FPCR bits */
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#define FPCR_SUM (1ULL << 63) |
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#define FPCR_INED (1ULL << 62) |
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#define FPCR_UNFD (1ULL << 61) |
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#define FPCR_UNDZ (1ULL << 60) |
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#define FPCR_DYN_SHIFT 58 |
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#define FPCR_DYN_CHOPPED (0ULL << FPCR_DYN_SHIFT) |
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#define FPCR_DYN_MINUS (1ULL << FPCR_DYN_SHIFT) |
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#define FPCR_DYN_NORMAL (2ULL << FPCR_DYN_SHIFT) |
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#define FPCR_DYN_PLUS (3ULL << FPCR_DYN_SHIFT) |
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#define FPCR_DYN_MASK (3ULL << FPCR_DYN_SHIFT) |
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#define FPCR_IOV (1ULL << 57) |
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#define FPCR_INE (1ULL << 56) |
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#define FPCR_UNF (1ULL << 55) |
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#define FPCR_OVF (1ULL << 54) |
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#define FPCR_DZE (1ULL << 53) |
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#define FPCR_INV (1ULL << 52) |
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#define FPCR_OVFD (1ULL << 51) |
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#define FPCR_DZED (1ULL << 50) |
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#define FPCR_INVD (1ULL << 49) |
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#define FPCR_DNZ (1ULL << 48) |
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#define FPCR_DNOD (1ULL << 47) |
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#define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \
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| FPCR_OVF | FPCR_DZE | FPCR_INV) |
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/* The silly software trap enables implemented by the kernel emulation.
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These are more or less architecturally required, since the real hardware
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has read-as-zero bits in the FPCR when the features aren't implemented.
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For the purposes of QEMU, we pretend the FPCR can hold everything. */
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#define SWCR_TRAP_ENABLE_INV (1ULL << 1) |
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#define SWCR_TRAP_ENABLE_DZE (1ULL << 2) |
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#define SWCR_TRAP_ENABLE_OVF (1ULL << 3) |
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#define SWCR_TRAP_ENABLE_UNF (1ULL << 4) |
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#define SWCR_TRAP_ENABLE_INE (1ULL << 5) |
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#define SWCR_TRAP_ENABLE_DNO (1ULL << 6) |
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#define SWCR_TRAP_ENABLE_MASK ((1ULL << 7) - (1ULL << 1)) |
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#define SWCR_MAP_DMZ (1ULL << 12) |
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#define SWCR_MAP_UMZ (1ULL << 13) |
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#define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
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#define SWCR_STATUS_INV (1ULL << 17) |
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#define SWCR_STATUS_DZE (1ULL << 18) |
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#define SWCR_STATUS_OVF (1ULL << 19) |
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#define SWCR_STATUS_UNF (1ULL << 20) |
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#define SWCR_STATUS_INE (1ULL << 21) |
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#define SWCR_STATUS_DNO (1ULL << 22) |
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#define SWCR_STATUS_MASK ((1ULL << 23) - (1ULL << 17)) |
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#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
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/* MMU modes definitions */
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/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
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The Unix PALcode only exposes the kernel and user modes; presumably
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executive and supervisor are used by VMS.
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PALcode itself uses physical mode for code and kernel mode for data;
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there are PALmode instructions that can access data via physical mode
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or via an os-installed "alternate mode", which is one of the 4 above.
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QEMU does not currently properly distinguish between code/data when
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looking up addresses. To avoid having to address this issue, our
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emulated PALcode will cheat and use the KSEG mapping for its code+data
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rather than physical addresses.
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Moreover, we're only emulating Unix PALcode, and not attempting VMS.
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All of which allows us to drop all but kernel and user modes.
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Elide the unused MMU modes to save space. */
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#define NB_MMU_MODES 2 |
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
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#define MMU_KERNEL_IDX 0 |
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#define MMU_USER_IDX 1 |
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typedef struct CPUAlphaState CPUAlphaState; |
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struct CPUAlphaState {
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uint64_t ir[31];
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float64 fir[31];
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uint64_t pc; |
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uint64_t unique; |
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uint64_t lock_addr; |
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uint64_t lock_st_addr; |
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uint64_t lock_value; |
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float_status fp_status; |
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/* The following fields make up the FPCR, but in FP_STATUS format. */
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uint8_t fpcr_exc_status; |
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uint8_t fpcr_exc_mask; |
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uint8_t fpcr_dyn_round; |
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uint8_t fpcr_flush_to_zero; |
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uint8_t fpcr_dnod; |
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uint8_t fpcr_undz; |
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/* The Internal Processor Registers. Some of these we assume always
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exist for use in user-mode. */
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uint8_t ps; |
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uint8_t intr_flag; |
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uint8_t pal_mode; |
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uint8_t fen; |
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uint32_t pcc_ofs; |
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/* These pass data from the exception logic in the translator and
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helpers to the OS entry point. This is used for both system
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emulation and user-mode. */
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uint64_t trap_arg0; |
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uint64_t trap_arg1; |
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uint64_t trap_arg2; |
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#if !defined(CONFIG_USER_ONLY)
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/* The internal data required by our emulation of the Unix PALcode. */
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uint64_t exc_addr; |
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uint64_t palbr; |
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uint64_t ptbr; |
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uint64_t vptptr; |
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uint64_t sysval; |
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uint64_t usp; |
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uint64_t shadow[8];
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uint64_t scratch[24];
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#endif
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/* This alarm doesn't exist in real hardware; we wish it did. */
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struct QEMUTimer *alarm_timer;
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uint64_t alarm_expire; |
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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/* temporary fixed-point registers
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* used to emulate 64 bits target on 32 bits hosts
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*/
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target_ulong t0, t1; |
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#endif
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/* Those resources are used only in QEMU core */
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CPU_COMMON |
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int error_code;
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uint32_t features; |
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uint32_t amask; |
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int implver;
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}; |
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#define cpu_init cpu_alpha_init
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#define cpu_exec cpu_alpha_exec
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#define cpu_gen_code cpu_alpha_gen_code
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#define cpu_signal_handler cpu_alpha_signal_handler
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#include "cpu-all.h" |
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#include "cpu-qom.h" |
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enum {
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FEATURE_ASN = 0x00000001,
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FEATURE_SPS = 0x00000002,
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FEATURE_VIRBND = 0x00000004,
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FEATURE_TBCHK = 0x00000008,
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}; |
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enum {
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EXCP_RESET, |
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EXCP_MCHK, |
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EXCP_SMP_INTERRUPT, |
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EXCP_CLK_INTERRUPT, |
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EXCP_DEV_INTERRUPT, |
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EXCP_MMFAULT, |
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EXCP_UNALIGN, |
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EXCP_OPCDEC, |
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EXCP_ARITH, |
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EXCP_FEN, |
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EXCP_CALL_PAL, |
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/* For Usermode emulation. */
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EXCP_STL_C, |
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EXCP_STQ_C, |
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}; |
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/* Alpha-specific interrupt pending bits. */
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#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0
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#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1
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#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2
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/* OSF/1 Page table bits. */
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enum {
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PTE_VALID = 0x0001,
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PTE_FOR = 0x0002, /* used for page protection (fault on read) */ |
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PTE_FOW = 0x0004, /* used for page protection (fault on write) */ |
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PTE_FOE = 0x0008, /* used for page protection (fault on exec) */ |
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PTE_ASM = 0x0010,
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PTE_KRE = 0x0100,
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PTE_URE = 0x0200,
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PTE_KWE = 0x1000,
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PTE_UWE = 0x2000
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}; |
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/* Hardware interrupt (entInt) constants. */
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enum {
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INT_K_IP, |
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INT_K_CLK, |
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INT_K_MCHK, |
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INT_K_DEV, |
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INT_K_PERF, |
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}; |
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/* Memory management (entMM) constants. */
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enum {
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MM_K_TNV, |
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MM_K_ACV, |
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MM_K_FOR, |
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MM_K_FOE, |
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MM_K_FOW |
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}; |
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/* Arithmetic exception (entArith) constants. */
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enum {
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EXC_M_SWC = 1, /* Software completion */ |
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EXC_M_INV = 2, /* Invalid operation */ |
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EXC_M_DZE = 4, /* Division by zero */ |
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EXC_M_FOV = 8, /* Overflow */ |
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EXC_M_UNF = 16, /* Underflow */ |
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EXC_M_INE = 32, /* Inexact result */ |
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EXC_M_IOV = 64 /* Integer Overflow */ |
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}; |
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/* Processor status constants. */
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enum {
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/* Low 3 bits are interrupt mask level. */
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PS_INT_MASK = 7,
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/* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes;
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The Unix PALcode only uses bit 4. */
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PS_USER_MODE = 8
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}; |
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static inline int cpu_mmu_index(CPUAlphaState *env) |
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{ |
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if (env->pal_mode) {
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return MMU_KERNEL_IDX;
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} else if (env->ps & PS_USER_MODE) { |
394 |
return MMU_USER_IDX;
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} else {
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return MMU_KERNEL_IDX;
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} |
398 |
} |
399 |
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enum {
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IR_V0 = 0,
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IR_T0 = 1,
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IR_T1 = 2,
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IR_T2 = 3,
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IR_T3 = 4,
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IR_T4 = 5,
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IR_T5 = 6,
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IR_T6 = 7,
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IR_T7 = 8,
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IR_S0 = 9,
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IR_S1 = 10,
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IR_S2 = 11,
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IR_S3 = 12,
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IR_S4 = 13,
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IR_S5 = 14,
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IR_S6 = 15,
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IR_FP = IR_S6, |
418 |
IR_A0 = 16,
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IR_A1 = 17,
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IR_A2 = 18,
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IR_A3 = 19,
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422 |
IR_A4 = 20,
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IR_A5 = 21,
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IR_T8 = 22,
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IR_T9 = 23,
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IR_T10 = 24,
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427 |
IR_T11 = 25,
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428 |
IR_RA = 26,
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IR_T12 = 27,
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IR_PV = IR_T12, |
431 |
IR_AT = 28,
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432 |
IR_GP = 29,
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433 |
IR_SP = 30,
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IR_ZERO = 31,
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}; |
436 |
|
437 |
CPUAlphaState * cpu_alpha_init (const char *cpu_model); |
438 |
int cpu_alpha_exec(CPUAlphaState *s);
|
439 |
/* you can call this signal handler from your SIGBUS and SIGSEGV
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440 |
signal handlers to inform the virtual CPU of exceptions. non zero
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441 |
is returned if the signal was handled by the virtual CPU. */
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442 |
int cpu_alpha_signal_handler(int host_signum, void *pinfo, |
443 |
void *puc);
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int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw, |
445 |
int mmu_idx);
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#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
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void do_interrupt (CPUAlphaState *env);
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void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
|
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void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); |
450 |
void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); |
451 |
|
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uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); |
453 |
void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
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#ifndef CONFIG_USER_ONLY
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void swap_shadow_regs(CPUAlphaState *env);
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QEMU_NORETURN void cpu_unassigned_access(CPUAlphaState *env1,
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hwaddr addr, int is_write,
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int is_exec, int unused, int size); |
459 |
#endif
|
460 |
|
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/* Bits in TB->FLAGS that control how translation is processed. */
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enum {
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TB_FLAGS_PAL_MODE = 1,
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TB_FLAGS_FEN = 2,
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TB_FLAGS_USER_MODE = 8,
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466 |
|
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TB_FLAGS_AMASK_SHIFT = 4,
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TB_FLAGS_AMASK_BWX = AMASK_BWX << TB_FLAGS_AMASK_SHIFT, |
469 |
TB_FLAGS_AMASK_FIX = AMASK_FIX << TB_FLAGS_AMASK_SHIFT, |
470 |
TB_FLAGS_AMASK_CIX = AMASK_CIX << TB_FLAGS_AMASK_SHIFT, |
471 |
TB_FLAGS_AMASK_MVI = AMASK_MVI << TB_FLAGS_AMASK_SHIFT, |
472 |
TB_FLAGS_AMASK_TRAP = AMASK_TRAP << TB_FLAGS_AMASK_SHIFT, |
473 |
TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT, |
474 |
}; |
475 |
|
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static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, |
477 |
target_ulong *cs_base, int *pflags)
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{ |
479 |
int flags = 0; |
480 |
|
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*pc = env->pc; |
482 |
*cs_base = 0;
|
483 |
|
484 |
if (env->pal_mode) {
|
485 |
flags = TB_FLAGS_PAL_MODE; |
486 |
} else {
|
487 |
flags = env->ps & PS_USER_MODE; |
488 |
} |
489 |
if (env->fen) {
|
490 |
flags |= TB_FLAGS_FEN; |
491 |
} |
492 |
flags |= env->amask << TB_FLAGS_AMASK_SHIFT; |
493 |
|
494 |
*pflags = flags; |
495 |
} |
496 |
|
497 |
#if defined(CONFIG_USER_ONLY)
|
498 |
static inline void cpu_clone_regs(CPUAlphaState *env, target_ulong newsp) |
499 |
{ |
500 |
if (newsp) {
|
501 |
env->ir[IR_SP] = newsp; |
502 |
} |
503 |
env->ir[IR_V0] = 0;
|
504 |
env->ir[IR_A3] = 0;
|
505 |
} |
506 |
|
507 |
static inline void cpu_set_tls(CPUAlphaState *env, target_ulong newtls) |
508 |
{ |
509 |
env->unique = newtls; |
510 |
} |
511 |
#endif
|
512 |
|
513 |
static inline bool cpu_has_work(CPUAlphaState *env) |
514 |
{ |
515 |
/* Here we are checking to see if the CPU should wake up from HALT.
|
516 |
We will have gotten into this state only for WTINT from PALmode. */
|
517 |
/* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
|
518 |
asleep even if (some) interrupts have been asserted. For now,
|
519 |
assume that if a CPU really wants to stay asleep, it will mask
|
520 |
interrupts at the chipset level, which will prevent these bits
|
521 |
from being set in the first place. */
|
522 |
return env->interrupt_request & (CPU_INTERRUPT_HARD
|
523 |
| CPU_INTERRUPT_TIMER |
524 |
| CPU_INTERRUPT_SMP |
525 |
| CPU_INTERRUPT_MCHK); |
526 |
} |
527 |
|
528 |
#include "exec-all.h" |
529 |
|
530 |
static inline void cpu_pc_from_tb(CPUAlphaState *env, TranslationBlock *tb) |
531 |
{ |
532 |
env->pc = tb->pc; |
533 |
} |
534 |
|
535 |
#endif /* !defined (__CPU_ALPHA_H__) */ |