root / target-i386 / arch_memory_mapping.c @ a8170e5e
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/*
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* i386 memory mapping
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*
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* Copyright Fujitsu, Corp. 2011, 2012
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*
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* Authors:
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* Wen Congyang <wency@cn.fujitsu.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "cpu.h" |
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#include "cpu-all.h" |
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#include "memory_mapping.h" |
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/* PAE Paging or IA-32e Paging */
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static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr, |
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int32_t a20_mask, target_ulong start_line_addr) |
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{ |
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hwaddr pte_addr, start_paddr; |
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uint64_t pte; |
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target_ulong start_vaddr; |
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int i;
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for (i = 0; i < 512; i++) { |
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pte_addr = (pte_start_addr + i * 8) & a20_mask;
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pte = ldq_phys(pte_addr); |
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if (!(pte & PG_PRESENT_MASK)) {
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/* not present */
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continue;
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} |
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start_paddr = (pte & ~0xfff) & ~(0x1ULL << 63); |
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if (cpu_physical_memory_is_io(start_paddr)) {
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/* I/O region */
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continue;
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} |
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start_vaddr = start_line_addr | ((i & 0x1fff) << 12); |
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memory_mapping_list_add_merge_sorted(list, start_paddr, |
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start_vaddr, 1 << 12); |
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} |
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} |
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/* 32-bit Paging */
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static void walk_pte2(MemoryMappingList *list, |
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hwaddr pte_start_addr, int32_t a20_mask, |
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target_ulong start_line_addr) |
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{ |
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hwaddr pte_addr, start_paddr; |
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uint32_t pte; |
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target_ulong start_vaddr; |
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int i;
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for (i = 0; i < 1024; i++) { |
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pte_addr = (pte_start_addr + i * 4) & a20_mask;
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pte = ldl_phys(pte_addr); |
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if (!(pte & PG_PRESENT_MASK)) {
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/* not present */
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continue;
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} |
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start_paddr = pte & ~0xfff;
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if (cpu_physical_memory_is_io(start_paddr)) {
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/* I/O region */
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continue;
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} |
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start_vaddr = start_line_addr | ((i & 0x3ff) << 12); |
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memory_mapping_list_add_merge_sorted(list, start_paddr, |
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start_vaddr, 1 << 12); |
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} |
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} |
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/* PAE Paging or IA-32e Paging */
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static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr, |
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int32_t a20_mask, target_ulong start_line_addr) |
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{ |
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hwaddr pde_addr, pte_start_addr, start_paddr; |
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uint64_t pde; |
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target_ulong line_addr, start_vaddr; |
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int i;
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for (i = 0; i < 512; i++) { |
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pde_addr = (pde_start_addr + i * 8) & a20_mask;
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pde = ldq_phys(pde_addr); |
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if (!(pde & PG_PRESENT_MASK)) {
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/* not present */
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continue;
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} |
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line_addr = start_line_addr | ((i & 0x1ff) << 21); |
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if (pde & PG_PSE_MASK) {
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/* 2 MB page */
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start_paddr = (pde & ~0x1fffff) & ~(0x1ULL << 63); |
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if (cpu_physical_memory_is_io(start_paddr)) {
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/* I/O region */
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continue;
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} |
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start_vaddr = line_addr; |
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memory_mapping_list_add_merge_sorted(list, start_paddr, |
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start_vaddr, 1 << 21); |
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continue;
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} |
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pte_start_addr = (pde & ~0xfff) & a20_mask;
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walk_pte(list, pte_start_addr, a20_mask, line_addr); |
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} |
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} |
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/* 32-bit Paging */
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static void walk_pde2(MemoryMappingList *list, |
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hwaddr pde_start_addr, int32_t a20_mask, |
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bool pse)
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{ |
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hwaddr pde_addr, pte_start_addr, start_paddr; |
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uint32_t pde; |
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target_ulong line_addr, start_vaddr; |
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int i;
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for (i = 0; i < 1024; i++) { |
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pde_addr = (pde_start_addr + i * 4) & a20_mask;
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pde = ldl_phys(pde_addr); |
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if (!(pde & PG_PRESENT_MASK)) {
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/* not present */
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continue;
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} |
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line_addr = (((unsigned int)i & 0x3ff) << 22); |
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if ((pde & PG_PSE_MASK) && pse) {
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/* 4 MB page */
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start_paddr = (pde & ~0x3fffff) | ((pde & 0x1fe000) << 19); |
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if (cpu_physical_memory_is_io(start_paddr)) {
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/* I/O region */
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continue;
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} |
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start_vaddr = line_addr; |
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memory_mapping_list_add_merge_sorted(list, start_paddr, |
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start_vaddr, 1 << 22); |
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continue;
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} |
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pte_start_addr = (pde & ~0xfff) & a20_mask;
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walk_pte2(list, pte_start_addr, a20_mask, line_addr); |
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} |
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} |
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/* PAE Paging */
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static void walk_pdpe2(MemoryMappingList *list, |
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hwaddr pdpe_start_addr, int32_t a20_mask) |
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{ |
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hwaddr pdpe_addr, pde_start_addr; |
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uint64_t pdpe; |
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target_ulong line_addr; |
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int i;
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for (i = 0; i < 4; i++) { |
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pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
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pdpe = ldq_phys(pdpe_addr); |
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if (!(pdpe & PG_PRESENT_MASK)) {
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/* not present */
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continue;
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} |
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line_addr = (((unsigned int)i & 0x3) << 30); |
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pde_start_addr = (pdpe & ~0xfff) & a20_mask;
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walk_pde(list, pde_start_addr, a20_mask, line_addr); |
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} |
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} |
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#ifdef TARGET_X86_64
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/* IA-32e Paging */
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static void walk_pdpe(MemoryMappingList *list, |
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hwaddr pdpe_start_addr, int32_t a20_mask, |
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target_ulong start_line_addr) |
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{ |
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hwaddr pdpe_addr, pde_start_addr, start_paddr; |
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uint64_t pdpe; |
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target_ulong line_addr, start_vaddr; |
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int i;
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for (i = 0; i < 512; i++) { |
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pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
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pdpe = ldq_phys(pdpe_addr); |
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if (!(pdpe & PG_PRESENT_MASK)) {
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/* not present */
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continue;
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} |
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line_addr = start_line_addr | ((i & 0x1ffULL) << 30); |
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if (pdpe & PG_PSE_MASK) {
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/* 1 GB page */
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start_paddr = (pdpe & ~0x3fffffff) & ~(0x1ULL << 63); |
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if (cpu_physical_memory_is_io(start_paddr)) {
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/* I/O region */
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continue;
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} |
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start_vaddr = line_addr; |
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memory_mapping_list_add_merge_sorted(list, start_paddr, |
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start_vaddr, 1 << 30); |
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continue;
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} |
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pde_start_addr = (pdpe & ~0xfff) & a20_mask;
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walk_pde(list, pde_start_addr, a20_mask, line_addr); |
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} |
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} |
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/* IA-32e Paging */
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static void walk_pml4e(MemoryMappingList *list, |
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hwaddr pml4e_start_addr, int32_t a20_mask) |
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{ |
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hwaddr pml4e_addr, pdpe_start_addr; |
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uint64_t pml4e; |
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target_ulong line_addr; |
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int i;
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for (i = 0; i < 512; i++) { |
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pml4e_addr = (pml4e_start_addr + i * 8) & a20_mask;
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pml4e = ldq_phys(pml4e_addr); |
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if (!(pml4e & PG_PRESENT_MASK)) {
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/* not present */
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continue;
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} |
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line_addr = ((i & 0x1ffULL) << 39) | (0xffffULL << 48); |
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pdpe_start_addr = (pml4e & ~0xfff) & a20_mask;
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walk_pdpe(list, pdpe_start_addr, a20_mask, line_addr); |
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} |
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} |
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#endif
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int cpu_get_memory_mapping(MemoryMappingList *list, CPUArchState *env)
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{ |
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if (!cpu_paging_enabled(env)) {
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/* paging is disabled */
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return 0; |
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} |
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if (env->cr[4] & CR4_PAE_MASK) { |
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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hwaddr pml4e_addr; |
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pml4e_addr = (env->cr[3] & ~0xfff) & env->a20_mask; |
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walk_pml4e(list, pml4e_addr, env->a20_mask); |
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} else
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#endif
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{ |
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hwaddr pdpe_addr; |
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pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask; |
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walk_pdpe2(list, pdpe_addr, env->a20_mask); |
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} |
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} else {
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hwaddr pde_addr; |
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bool pse;
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pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask; |
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pse = !!(env->cr[4] & CR4_PSE_MASK);
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walk_pde2(list, pde_addr, env->a20_mask, pse); |
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} |
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return 0; |
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} |
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bool cpu_paging_enabled(CPUArchState *env)
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{ |
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return env->cr[0] & CR0_PG_MASK; |
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} |