root / target-microblaze / op_helper.c @ a8170e5e
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/*
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* Microblaze helper routines.
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*
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* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
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* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <assert.h> |
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#include "cpu.h" |
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#include "helper.h" |
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#include "host-utils.h" |
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#define D(x)
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#if !defined(CONFIG_USER_ONLY)
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#include "softmmu_exec.h" |
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#define MMUSUFFIX _mmu
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#define SHIFT 0 |
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#include "softmmu_template.h" |
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#define SHIFT 1 |
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#include "softmmu_template.h" |
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#define SHIFT 2 |
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#include "softmmu_template.h" |
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#define SHIFT 3 |
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#include "softmmu_template.h" |
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/* Try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx, |
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uintptr_t retaddr) |
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{ |
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TranslationBlock *tb; |
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int ret;
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ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx); |
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if (unlikely(ret)) {
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if (retaddr) {
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/* now we have a real cpu fault */
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tb = tb_find_pc(retaddr); |
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, retaddr); |
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} |
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} |
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cpu_loop_exit(env); |
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} |
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} |
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#endif
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void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
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{ |
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int test = ctrl & STREAM_TEST;
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int atomic = ctrl & STREAM_ATOMIC;
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int control = ctrl & STREAM_CONTROL;
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int nonblock = ctrl & STREAM_NONBLOCK;
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int exception = ctrl & STREAM_EXCEPTION;
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qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
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id, data, |
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test ? "t" : "", |
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nonblock ? "n" : "", |
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exception ? "e" : "", |
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control ? "c" : "", |
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atomic ? "a" : ""); |
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} |
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uint32_t helper_get(uint32_t id, uint32_t ctrl) |
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{ |
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int test = ctrl & STREAM_TEST;
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int atomic = ctrl & STREAM_ATOMIC;
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int control = ctrl & STREAM_CONTROL;
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int nonblock = ctrl & STREAM_NONBLOCK;
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int exception = ctrl & STREAM_EXCEPTION;
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qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
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id, |
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test ? "t" : "", |
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nonblock ? "n" : "", |
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exception ? "e" : "", |
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control ? "c" : "", |
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atomic ? "a" : ""); |
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return 0xdead0000 | id; |
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} |
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void helper_raise_exception(CPUMBState *env, uint32_t index)
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{ |
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env->exception_index = index; |
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cpu_loop_exit(env); |
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} |
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void helper_debug(CPUMBState *env)
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{ |
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int i;
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qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
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qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
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env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], |
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env->debug, env->imm, env->iflags); |
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qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
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env->btaken, env->btarget, |
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(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", |
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(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", |
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(env->sregs[SR_MSR] & MSR_EIP), |
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(env->sregs[SR_MSR] & MSR_IE)); |
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for (i = 0; i < 32; i++) { |
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qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
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if ((i + 1) % 4 == 0) |
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qemu_log("\n");
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} |
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qemu_log("\n\n");
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} |
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static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin) |
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{ |
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uint32_t cout = 0;
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if ((b == ~0) && cin) |
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cout = 1;
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else if ((~0 - a) < (b + cin)) |
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cout = 1;
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return cout;
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} |
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uint32_t helper_cmp(uint32_t a, uint32_t b) |
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{ |
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uint32_t t; |
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t = b + ~a + 1;
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if ((b & 0x80000000) ^ (a & 0x80000000)) |
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t = (t & 0x7fffffff) | (b & 0x80000000); |
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return t;
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} |
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uint32_t helper_cmpu(uint32_t a, uint32_t b) |
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{ |
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uint32_t t; |
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t = b + ~a + 1;
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if ((b & 0x80000000) ^ (a & 0x80000000)) |
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t = (t & 0x7fffffff) | (a & 0x80000000); |
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return t;
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} |
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uint32_t helper_clz(uint32_t t0) |
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{ |
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return clz32(t0);
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} |
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uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf) |
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{ |
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uint32_t ncf; |
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ncf = compute_carry(a, b, cf); |
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return ncf;
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} |
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static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) |
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{ |
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if (b == 0) { |
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env->sregs[SR_MSR] |= MSR_DZ; |
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if ((env->sregs[SR_MSR] & MSR_EE)
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&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
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env->sregs[SR_ESR] = ESR_EC_DIVZERO; |
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helper_raise_exception(env, EXCP_HW_EXCP); |
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} |
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return 0; |
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} |
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env->sregs[SR_MSR] &= ~MSR_DZ; |
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return 1; |
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} |
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uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) |
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{ |
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if (!div_prepare(env, a, b)) {
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return 0; |
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} |
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return (int32_t)a / (int32_t)b;
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} |
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uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) |
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{ |
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if (!div_prepare(env, a, b)) {
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return 0; |
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} |
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return a / b;
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} |
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/* raise FPU exception. */
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static void raise_fpu_exception(CPUMBState *env) |
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{ |
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env->sregs[SR_ESR] = ESR_EC_FPU; |
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helper_raise_exception(env, EXCP_HW_EXCP); |
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} |
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static void update_fpu_flags(CPUMBState *env, int flags) |
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{ |
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int raise = 0; |
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if (flags & float_flag_invalid) {
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env->sregs[SR_FSR] |= FSR_IO; |
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raise = 1;
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} |
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if (flags & float_flag_divbyzero) {
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env->sregs[SR_FSR] |= FSR_DZ; |
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raise = 1;
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} |
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if (flags & float_flag_overflow) {
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env->sregs[SR_FSR] |= FSR_OF; |
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raise = 1;
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} |
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if (flags & float_flag_underflow) {
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env->sregs[SR_FSR] |= FSR_UF; |
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raise = 1;
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} |
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if (raise
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&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
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&& (env->sregs[SR_MSR] & MSR_EE)) { |
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raise_fpu_exception(env); |
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} |
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} |
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uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b) |
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{ |
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CPU_FloatU fd, fa, fb; |
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a; |
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fb.l = b; |
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fd.f = float32_add(fa.f, fb.f, &env->fp_status); |
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flags = get_float_exception_flags(&env->fp_status); |
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update_fpu_flags(env, flags); |
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return fd.l;
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} |
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uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b) |
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{ |
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CPU_FloatU fd, fa, fb; |
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a; |
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fb.l = b; |
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fd.f = float32_sub(fb.f, fa.f, &env->fp_status); |
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flags = get_float_exception_flags(&env->fp_status); |
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update_fpu_flags(env, flags); |
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return fd.l;
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} |
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uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b) |
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{ |
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CPU_FloatU fd, fa, fb; |
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a; |
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fb.l = b; |
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fd.f = float32_mul(fa.f, fb.f, &env->fp_status); |
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flags = get_float_exception_flags(&env->fp_status); |
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update_fpu_flags(env, flags); |
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return fd.l;
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} |
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uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b) |
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{ |
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CPU_FloatU fd, fa, fb; |
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a; |
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fb.l = b; |
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fd.f = float32_div(fb.f, fa.f, &env->fp_status); |
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flags = get_float_exception_flags(&env->fp_status); |
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update_fpu_flags(env, flags); |
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return fd.l;
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} |
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uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b) |
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{ |
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CPU_FloatU fa, fb; |
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uint32_t r = 0;
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fa.l = a; |
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fb.l = b; |
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if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
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update_fpu_flags(env, float_flag_invalid); |
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r = 1;
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} |
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if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
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r = 1;
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} |
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return r;
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} |
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uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b) |
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{ |
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CPU_FloatU fa, fb; |
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int r;
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a; |
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fb.l = b; |
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r = float32_lt(fb.f, fa.f, &env->fp_status); |
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flags = get_float_exception_flags(&env->fp_status); |
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update_fpu_flags(env, flags & float_flag_invalid); |
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return r;
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} |
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uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b) |
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{ |
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CPU_FloatU fa, fb; |
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int flags;
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int r;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a; |
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fb.l = b; |
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r = float32_eq_quiet(fa.f, fb.f, &env->fp_status); |
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flags = get_float_exception_flags(&env->fp_status); |
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update_fpu_flags(env, flags & float_flag_invalid); |
345 |
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return r;
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} |
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uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b) |
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{ |
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CPU_FloatU fa, fb; |
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int flags;
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int r;
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fa.l = a; |
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fb.l = b; |
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set_float_exception_flags(0, &env->fp_status);
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r = float32_le(fa.f, fb.f, &env->fp_status); |
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flags = get_float_exception_flags(&env->fp_status); |
360 |
update_fpu_flags(env, flags & float_flag_invalid); |
361 |
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return r;
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} |
365 |
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uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b) |
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{ |
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CPU_FloatU fa, fb; |
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int flags, r;
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fa.l = a; |
372 |
fb.l = b; |
373 |
set_float_exception_flags(0, &env->fp_status);
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r = float32_lt(fa.f, fb.f, &env->fp_status); |
375 |
flags = get_float_exception_flags(&env->fp_status); |
376 |
update_fpu_flags(env, flags & float_flag_invalid); |
377 |
return r;
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} |
379 |
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380 |
uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b) |
381 |
{ |
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CPU_FloatU fa, fb; |
383 |
int flags, r;
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384 |
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fa.l = a; |
386 |
fb.l = b; |
387 |
set_float_exception_flags(0, &env->fp_status);
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r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status); |
389 |
flags = get_float_exception_flags(&env->fp_status); |
390 |
update_fpu_flags(env, flags & float_flag_invalid); |
391 |
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392 |
return r;
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} |
394 |
|
395 |
uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b) |
396 |
{ |
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CPU_FloatU fa, fb; |
398 |
int flags, r;
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|
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fa.l = a; |
401 |
fb.l = b; |
402 |
set_float_exception_flags(0, &env->fp_status);
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r = !float32_lt(fa.f, fb.f, &env->fp_status); |
404 |
flags = get_float_exception_flags(&env->fp_status); |
405 |
update_fpu_flags(env, flags & float_flag_invalid); |
406 |
|
407 |
return r;
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408 |
} |
409 |
|
410 |
uint32_t helper_flt(CPUMBState *env, uint32_t a) |
411 |
{ |
412 |
CPU_FloatU fd, fa; |
413 |
|
414 |
fa.l = a; |
415 |
fd.f = int32_to_float32(fa.l, &env->fp_status); |
416 |
return fd.l;
|
417 |
} |
418 |
|
419 |
uint32_t helper_fint(CPUMBState *env, uint32_t a) |
420 |
{ |
421 |
CPU_FloatU fa; |
422 |
uint32_t r; |
423 |
int flags;
|
424 |
|
425 |
set_float_exception_flags(0, &env->fp_status);
|
426 |
fa.l = a; |
427 |
r = float32_to_int32(fa.f, &env->fp_status); |
428 |
flags = get_float_exception_flags(&env->fp_status); |
429 |
update_fpu_flags(env, flags); |
430 |
|
431 |
return r;
|
432 |
} |
433 |
|
434 |
uint32_t helper_fsqrt(CPUMBState *env, uint32_t a) |
435 |
{ |
436 |
CPU_FloatU fd, fa; |
437 |
int flags;
|
438 |
|
439 |
set_float_exception_flags(0, &env->fp_status);
|
440 |
fa.l = a; |
441 |
fd.l = float32_sqrt(fa.f, &env->fp_status); |
442 |
flags = get_float_exception_flags(&env->fp_status); |
443 |
update_fpu_flags(env, flags); |
444 |
|
445 |
return fd.l;
|
446 |
} |
447 |
|
448 |
uint32_t helper_pcmpbf(uint32_t a, uint32_t b) |
449 |
{ |
450 |
unsigned int i; |
451 |
uint32_t mask = 0xff000000;
|
452 |
|
453 |
for (i = 0; i < 4; i++) { |
454 |
if ((a & mask) == (b & mask))
|
455 |
return i + 1; |
456 |
mask >>= 8;
|
457 |
} |
458 |
return 0; |
459 |
} |
460 |
|
461 |
void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
|
462 |
uint32_t mask) |
463 |
{ |
464 |
if (addr & mask) {
|
465 |
qemu_log_mask(CPU_LOG_INT, |
466 |
"unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
|
467 |
addr, mask, wr, dr); |
468 |
env->sregs[SR_EAR] = addr; |
469 |
env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
|
470 |
| (dr & 31) << 5; |
471 |
if (mask == 3) { |
472 |
env->sregs[SR_ESR] |= 1 << 11; |
473 |
} |
474 |
if (!(env->sregs[SR_MSR] & MSR_EE)) {
|
475 |
return;
|
476 |
} |
477 |
helper_raise_exception(env, EXCP_HW_EXCP); |
478 |
} |
479 |
} |
480 |
|
481 |
void helper_stackprot(CPUMBState *env, uint32_t addr)
|
482 |
{ |
483 |
if (addr < env->slr || addr > env->shr) {
|
484 |
qemu_log("Stack protector violation at %x %x %x\n",
|
485 |
addr, env->slr, env->shr); |
486 |
env->sregs[SR_EAR] = addr; |
487 |
env->sregs[SR_ESR] = ESR_EC_STACKPROT; |
488 |
helper_raise_exception(env, EXCP_HW_EXCP); |
489 |
} |
490 |
} |
491 |
|
492 |
#if !defined(CONFIG_USER_ONLY)
|
493 |
/* Writes/reads to the MMU's special regs end up here. */
|
494 |
uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn) |
495 |
{ |
496 |
return mmu_read(env, rn);
|
497 |
} |
498 |
|
499 |
void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
|
500 |
{ |
501 |
mmu_write(env, rn, v); |
502 |
} |
503 |
|
504 |
void cpu_unassigned_access(CPUMBState *env, hwaddr addr,
|
505 |
int is_write, int is_exec, int is_asi, int size) |
506 |
{ |
507 |
qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n", |
508 |
addr, is_write, is_exec); |
509 |
if (!(env->sregs[SR_MSR] & MSR_EE)) {
|
510 |
return;
|
511 |
} |
512 |
|
513 |
env->sregs[SR_EAR] = addr; |
514 |
if (is_exec) {
|
515 |
if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { |
516 |
env->sregs[SR_ESR] = ESR_EC_INSN_BUS; |
517 |
helper_raise_exception(env, EXCP_HW_EXCP); |
518 |
} |
519 |
} else {
|
520 |
if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) { |
521 |
env->sregs[SR_ESR] = ESR_EC_DATA_BUS; |
522 |
helper_raise_exception(env, EXCP_HW_EXCP); |
523 |
} |
524 |
} |
525 |
} |
526 |
#endif
|