root / target-mips / op_helper.c @ a8170e5e
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/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdlib.h> |
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#include "cpu.h" |
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#include "host-utils.h" |
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#include "helper.h" |
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#if !defined(CONFIG_USER_ONLY)
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#include "softmmu_exec.h" |
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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#ifndef CONFIG_USER_ONLY
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static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global); |
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#endif
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/*****************************************************************************/
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/* Exceptions processing helpers */
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void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
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int error_code)
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{
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#if 1 |
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if (exception < 0x100) |
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qemu_log("%s: %d %d\n", __func__, exception, error_code);
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#endif
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env->exception_index = exception; |
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env->error_code = error_code; |
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cpu_loop_exit(env); |
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} |
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void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
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{
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helper_raise_exception_err(env, exception, 0);
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} |
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#if !defined(CONFIG_USER_ONLY)
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static void do_restore_state(CPUMIPSState *env, uintptr_t pc) |
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{
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TranslationBlock *tb; |
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tb = tb_find_pc (pc); |
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if (tb) {
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cpu_restore_state(tb, env, pc); |
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} |
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} |
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#endif
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#if defined(CONFIG_USER_ONLY)
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#define HELPER_LD(name, insn, type) \
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static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ |
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int mem_idx) \
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{ \
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return (type) insn##_raw(addr); \ |
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} |
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#else
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#define HELPER_LD(name, insn, type) \
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static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ |
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int mem_idx) \
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{ \
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switch (mem_idx) \
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{ \
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case 0: return (type) cpu_##insn##_kernel(env, addr); break; \ |
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case 1: return (type) cpu_##insn##_super(env, addr); break; \ |
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default: \
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case 2: return (type) cpu_##insn##_user(env, addr); break; \ |
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} \ |
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} |
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#endif
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HELPER_LD(lbu, ldub, uint8_t) |
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HELPER_LD(lw, ldl, int32_t) |
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#ifdef TARGET_MIPS64
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HELPER_LD(ld, ldq, int64_t) |
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#endif
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#undef HELPER_LD
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#if defined(CONFIG_USER_ONLY)
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#define HELPER_ST(name, insn, type) \
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static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ |
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type val, int mem_idx) \
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{ \
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insn##_raw(addr, val); \ |
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} |
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#else
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#define HELPER_ST(name, insn, type) \
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static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ |
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type val, int mem_idx) \
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{ \
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switch (mem_idx) \
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{ \
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case 0: cpu_##insn##_kernel(env, addr, val); break; \ |
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case 1: cpu_##insn##_super(env, addr, val); break; \ |
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default: \
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case 2: cpu_##insn##_user(env, addr, val); break; \ |
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} \ |
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} |
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#endif
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HELPER_ST(sb, stb, uint8_t) |
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HELPER_ST(sw, stl, uint32_t) |
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#ifdef TARGET_MIPS64
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HELPER_ST(sd, stq, uint64_t) |
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#endif
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#undef HELPER_ST
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target_ulong helper_clo (target_ulong arg1) |
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{
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return clo32(arg1);
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} |
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target_ulong helper_clz (target_ulong arg1) |
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{
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return clz32(arg1);
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} |
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#if defined(TARGET_MIPS64)
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target_ulong helper_dclo (target_ulong arg1) |
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{
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return clo64(arg1);
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} |
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target_ulong helper_dclz (target_ulong arg1) |
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{
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return clz64(arg1);
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} |
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#endif /* TARGET_MIPS64 */ |
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/* 64 bits arithmetic for 32 bits hosts */
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static inline uint64_t get_HILO(CPUMIPSState *env) |
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{
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return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; |
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} |
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static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) |
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{
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target_ulong tmp; |
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env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
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tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
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return tmp;
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} |
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static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) |
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{
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target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
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env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
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return tmp;
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} |
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/* Multiplication variants of the vr54xx. */
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target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * |
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(int64_t)(int32_t)arg2)); |
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} |
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target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * |
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(uint64_t)(uint32_t)arg2); |
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} |
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target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2); |
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} |
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target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2); |
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} |
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target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
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(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
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} |
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target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
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(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
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} |
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target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2); |
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} |
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target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2); |
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} |
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target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
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(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
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} |
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target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
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(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
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} |
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target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
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} |
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target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
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(uint64_t)(uint32_t)arg2); |
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} |
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target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * |
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(int64_t)(int32_t)arg2); |
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} |
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target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{
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return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * |
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(uint64_t)(uint32_t)arg2); |
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} |
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#ifdef TARGET_MIPS64
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void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
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{
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muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); |
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} |
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void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
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{
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mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); |
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} |
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#endif
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#ifndef CONFIG_USER_ONLY
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static inline hwaddr do_translate_address(CPUMIPSState *env, |
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target_ulong address, |
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int rw)
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{
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hwaddr lladdr; |
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lladdr = cpu_mips_translate_address(env, address, rw); |
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if (lladdr == -1LL) { |
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cpu_loop_exit(env); |
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} else {
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return lladdr;
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} |
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} |
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#define HELPER_LD_ATOMIC(name, insn) \
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target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \ |
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{ \
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env->lladdr = do_translate_address(env, arg, 0); \
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env->llval = do_##insn(env, arg, mem_idx); \ |
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return env->llval; \
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} |
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HELPER_LD_ATOMIC(ll, lw) |
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#ifdef TARGET_MIPS64
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HELPER_LD_ATOMIC(lld, ld) |
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#endif
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#undef HELPER_LD_ATOMIC
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#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
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target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \ |
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target_ulong arg2, int mem_idx) \
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{ \
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target_long tmp; \ |
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\ |
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if (arg2 & almask) { \
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env->CP0_BadVAddr = arg2; \ |
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helper_raise_exception(env, EXCP_AdES); \ |
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} \ |
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if (do_translate_address(env, arg2, 1) == env->lladdr) { \ |
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tmp = do_##ld_insn(env, arg2, mem_idx); \ |
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if (tmp == env->llval) { \
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do_##st_insn(env, arg2, arg1, mem_idx); \ |
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return 1; \ |
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} \ |
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} \ |
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return 0; \ |
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} |
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HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
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#ifdef TARGET_MIPS64
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HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
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#endif
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#undef HELPER_ST_ATOMIC
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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#define GET_LMASK(v) ((v) & 3) |
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#define GET_OFFSET(addr, offset) (addr + (offset))
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#else
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#define GET_LMASK(v) (((v) & 3) ^ 3) |
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#define GET_OFFSET(addr, offset) (addr - (offset))
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#endif
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target_ulong helper_lwl(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2, int mem_idx)
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{
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target_ulong tmp; |
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tmp = do_lbu(env, arg2, mem_idx); |
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arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); |
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|
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if (GET_LMASK(arg2) <= 2) { |
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tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx);
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arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); |
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} |
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|
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if (GET_LMASK(arg2) <= 1) { |
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tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx);
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arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); |
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} |
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|
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if (GET_LMASK(arg2) == 0) { |
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tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx);
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arg1 = (arg1 & 0xFFFFFF00) | tmp;
|
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} |
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return (int32_t)arg1;
|
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} |
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|
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target_ulong helper_lwr(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2, int mem_idx)
|
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{
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target_ulong tmp; |
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|
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tmp = do_lbu(env, arg2, mem_idx); |
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arg1 = (arg1 & 0xFFFFFF00) | tmp;
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|
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if (GET_LMASK(arg2) >= 1) { |
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tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx);
|
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arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); |
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} |
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|
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if (GET_LMASK(arg2) >= 2) { |
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tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx);
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arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); |
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} |
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|
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if (GET_LMASK(arg2) == 3) { |
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tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx);
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arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); |
| 384 |
} |
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return (int32_t)arg1;
|
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} |
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|
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void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
|
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int mem_idx)
|
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{
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do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
|
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|
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if (GET_LMASK(arg2) <= 2) |
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do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); |
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|
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if (GET_LMASK(arg2) <= 1) |
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do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); |
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|
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if (GET_LMASK(arg2) == 0) |
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do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
|
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} |
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|
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void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
|
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int mem_idx)
|
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{
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do_sb(env, arg2, (uint8_t)arg1, mem_idx); |
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|
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if (GET_LMASK(arg2) >= 1) |
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do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
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|
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if (GET_LMASK(arg2) >= 2) |
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do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
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|
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if (GET_LMASK(arg2) == 3) |
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do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
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} |
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|
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#if defined(TARGET_MIPS64)
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/* "half" load and stores. We must do the memory access inline,
|
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or fault handling won't work. */
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|
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#ifdef TARGET_WORDS_BIGENDIAN
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#define GET_LMASK64(v) ((v) & 7) |
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#else
|
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#define GET_LMASK64(v) (((v) & 7) ^ 7) |
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#endif
|
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|
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target_ulong helper_ldl(CPUMIPSState *env, target_ulong arg1, |
| 429 |
target_ulong arg2, int mem_idx)
|
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{
|
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uint64_t tmp; |
| 432 |
|
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tmp = do_lbu(env, arg2, mem_idx); |
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arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); |
| 435 |
|
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if (GET_LMASK64(arg2) <= 6) { |
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tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx);
|
| 438 |
arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); |
| 439 |
} |
| 440 |
|
| 441 |
if (GET_LMASK64(arg2) <= 5) { |
| 442 |
tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx);
|
| 443 |
arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); |
| 444 |
} |
| 445 |
|
| 446 |
if (GET_LMASK64(arg2) <= 4) { |
| 447 |
tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx);
|
| 448 |
arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); |
| 449 |
} |
| 450 |
|
| 451 |
if (GET_LMASK64(arg2) <= 3) { |
| 452 |
tmp = do_lbu(env, GET_OFFSET(arg2, 4), mem_idx);
|
| 453 |
arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); |
| 454 |
} |
| 455 |
|
| 456 |
if (GET_LMASK64(arg2) <= 2) { |
| 457 |
tmp = do_lbu(env, GET_OFFSET(arg2, 5), mem_idx);
|
| 458 |
arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); |
| 459 |
} |
| 460 |
|
| 461 |
if (GET_LMASK64(arg2) <= 1) { |
| 462 |
tmp = do_lbu(env, GET_OFFSET(arg2, 6), mem_idx);
|
| 463 |
arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); |
| 464 |
} |
| 465 |
|
| 466 |
if (GET_LMASK64(arg2) == 0) { |
| 467 |
tmp = do_lbu(env, GET_OFFSET(arg2, 7), mem_idx);
|
| 468 |
arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
|
| 469 |
} |
| 470 |
|
| 471 |
return arg1;
|
| 472 |
} |
| 473 |
|
| 474 |
target_ulong helper_ldr(CPUMIPSState *env, target_ulong arg1, |
| 475 |
target_ulong arg2, int mem_idx)
|
| 476 |
{
|
| 477 |
uint64_t tmp; |
| 478 |
|
| 479 |
tmp = do_lbu(env, arg2, mem_idx); |
| 480 |
arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
|
| 481 |
|
| 482 |
if (GET_LMASK64(arg2) >= 1) { |
| 483 |
tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx);
|
| 484 |
arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); |
| 485 |
} |
| 486 |
|
| 487 |
if (GET_LMASK64(arg2) >= 2) { |
| 488 |
tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx);
|
| 489 |
arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); |
| 490 |
} |
| 491 |
|
| 492 |
if (GET_LMASK64(arg2) >= 3) { |
| 493 |
tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx);
|
| 494 |
arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); |
| 495 |
} |
| 496 |
|
| 497 |
if (GET_LMASK64(arg2) >= 4) { |
| 498 |
tmp = do_lbu(env, GET_OFFSET(arg2, -4), mem_idx);
|
| 499 |
arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); |
| 500 |
} |
| 501 |
|
| 502 |
if (GET_LMASK64(arg2) >= 5) { |
| 503 |
tmp = do_lbu(env, GET_OFFSET(arg2, -5), mem_idx);
|
| 504 |
arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); |
| 505 |
} |
| 506 |
|
| 507 |
if (GET_LMASK64(arg2) >= 6) { |
| 508 |
tmp = do_lbu(env, GET_OFFSET(arg2, -6), mem_idx);
|
| 509 |
arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); |
| 510 |
} |
| 511 |
|
| 512 |
if (GET_LMASK64(arg2) == 7) { |
| 513 |
tmp = do_lbu(env, GET_OFFSET(arg2, -7), mem_idx);
|
| 514 |
arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); |
| 515 |
} |
| 516 |
|
| 517 |
return arg1;
|
| 518 |
} |
| 519 |
|
| 520 |
void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
|
| 521 |
int mem_idx)
|
| 522 |
{
|
| 523 |
do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
|
| 524 |
|
| 525 |
if (GET_LMASK64(arg2) <= 6) |
| 526 |
do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); |
| 527 |
|
| 528 |
if (GET_LMASK64(arg2) <= 5) |
| 529 |
do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); |
| 530 |
|
| 531 |
if (GET_LMASK64(arg2) <= 4) |
| 532 |
do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); |
| 533 |
|
| 534 |
if (GET_LMASK64(arg2) <= 3) |
| 535 |
do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); |
| 536 |
|
| 537 |
if (GET_LMASK64(arg2) <= 2) |
| 538 |
do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); |
| 539 |
|
| 540 |
if (GET_LMASK64(arg2) <= 1) |
| 541 |
do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); |
| 542 |
|
| 543 |
if (GET_LMASK64(arg2) <= 0) |
| 544 |
do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
|
| 545 |
} |
| 546 |
|
| 547 |
void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
|
| 548 |
int mem_idx)
|
| 549 |
{
|
| 550 |
do_sb(env, arg2, (uint8_t)arg1, mem_idx); |
| 551 |
|
| 552 |
if (GET_LMASK64(arg2) >= 1) |
| 553 |
do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
| 554 |
|
| 555 |
if (GET_LMASK64(arg2) >= 2) |
| 556 |
do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
| 557 |
|
| 558 |
if (GET_LMASK64(arg2) >= 3) |
| 559 |
do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
| 560 |
|
| 561 |
if (GET_LMASK64(arg2) >= 4) |
| 562 |
do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); |
| 563 |
|
| 564 |
if (GET_LMASK64(arg2) >= 5) |
| 565 |
do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); |
| 566 |
|
| 567 |
if (GET_LMASK64(arg2) >= 6) |
| 568 |
do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); |
| 569 |
|
| 570 |
if (GET_LMASK64(arg2) == 7) |
| 571 |
do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); |
| 572 |
} |
| 573 |
#endif /* TARGET_MIPS64 */ |
| 574 |
|
| 575 |
static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 }; |
| 576 |
|
| 577 |
void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
|
| 578 |
uint32_t mem_idx) |
| 579 |
{
|
| 580 |
target_ulong base_reglist = reglist & 0xf;
|
| 581 |
target_ulong do_r31 = reglist & 0x10;
|
| 582 |
#ifdef CONFIG_USER_ONLY
|
| 583 |
#undef ldfun
|
| 584 |
#define ldfun(env, addr) ldl_raw(addr)
|
| 585 |
#else
|
| 586 |
uint32_t (*ldfun)(CPUMIPSState *env, target_ulong); |
| 587 |
|
| 588 |
switch (mem_idx)
|
| 589 |
{
|
| 590 |
case 0: ldfun = cpu_ldl_kernel; break; |
| 591 |
case 1: ldfun = cpu_ldl_super; break; |
| 592 |
default:
|
| 593 |
case 2: ldfun = cpu_ldl_user; break; |
| 594 |
} |
| 595 |
#endif
|
| 596 |
|
| 597 |
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
| 598 |
target_ulong i; |
| 599 |
|
| 600 |
for (i = 0; i < base_reglist; i++) { |
| 601 |
env->active_tc.gpr[multiple_regs[i]] = (target_long)ldfun(env, addr); |
| 602 |
addr += 4;
|
| 603 |
} |
| 604 |
} |
| 605 |
|
| 606 |
if (do_r31) {
|
| 607 |
env->active_tc.gpr[31] = (target_long)ldfun(env, addr);
|
| 608 |
} |
| 609 |
} |
| 610 |
|
| 611 |
void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
|
| 612 |
uint32_t mem_idx) |
| 613 |
{
|
| 614 |
target_ulong base_reglist = reglist & 0xf;
|
| 615 |
target_ulong do_r31 = reglist & 0x10;
|
| 616 |
#ifdef CONFIG_USER_ONLY
|
| 617 |
#undef stfun
|
| 618 |
#define stfun(env, addr, val) stl_raw(addr, val)
|
| 619 |
#else
|
| 620 |
void (*stfun)(CPUMIPSState *env, target_ulong, uint32_t);
|
| 621 |
|
| 622 |
switch (mem_idx)
|
| 623 |
{
|
| 624 |
case 0: stfun = cpu_stl_kernel; break; |
| 625 |
case 1: stfun = cpu_stl_super; break; |
| 626 |
default:
|
| 627 |
case 2: stfun = cpu_stl_user; break; |
| 628 |
} |
| 629 |
#endif
|
| 630 |
|
| 631 |
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
| 632 |
target_ulong i; |
| 633 |
|
| 634 |
for (i = 0; i < base_reglist; i++) { |
| 635 |
stfun(env, addr, env->active_tc.gpr[multiple_regs[i]]); |
| 636 |
addr += 4;
|
| 637 |
} |
| 638 |
} |
| 639 |
|
| 640 |
if (do_r31) {
|
| 641 |
stfun(env, addr, env->active_tc.gpr[31]);
|
| 642 |
} |
| 643 |
} |
| 644 |
|
| 645 |
#if defined(TARGET_MIPS64)
|
| 646 |
void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
|
| 647 |
uint32_t mem_idx) |
| 648 |
{
|
| 649 |
target_ulong base_reglist = reglist & 0xf;
|
| 650 |
target_ulong do_r31 = reglist & 0x10;
|
| 651 |
#ifdef CONFIG_USER_ONLY
|
| 652 |
#undef ldfun
|
| 653 |
#define ldfun(env, addr) ldq_raw(addr)
|
| 654 |
#else
|
| 655 |
uint64_t (*ldfun)(CPUMIPSState *env, target_ulong); |
| 656 |
|
| 657 |
switch (mem_idx)
|
| 658 |
{
|
| 659 |
case 0: ldfun = cpu_ldq_kernel; break; |
| 660 |
case 1: ldfun = cpu_ldq_super; break; |
| 661 |
default:
|
| 662 |
case 2: ldfun = cpu_ldq_user; break; |
| 663 |
} |
| 664 |
#endif
|
| 665 |
|
| 666 |
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
| 667 |
target_ulong i; |
| 668 |
|
| 669 |
for (i = 0; i < base_reglist; i++) { |
| 670 |
env->active_tc.gpr[multiple_regs[i]] = ldfun(env, addr); |
| 671 |
addr += 8;
|
| 672 |
} |
| 673 |
} |
| 674 |
|
| 675 |
if (do_r31) {
|
| 676 |
env->active_tc.gpr[31] = ldfun(env, addr);
|
| 677 |
} |
| 678 |
} |
| 679 |
|
| 680 |
void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
|
| 681 |
uint32_t mem_idx) |
| 682 |
{
|
| 683 |
target_ulong base_reglist = reglist & 0xf;
|
| 684 |
target_ulong do_r31 = reglist & 0x10;
|
| 685 |
#ifdef CONFIG_USER_ONLY
|
| 686 |
#undef stfun
|
| 687 |
#define stfun(env, addr, val) stq_raw(addr, val)
|
| 688 |
#else
|
| 689 |
void (*stfun)(CPUMIPSState *env, target_ulong, uint64_t);
|
| 690 |
|
| 691 |
switch (mem_idx)
|
| 692 |
{
|
| 693 |
case 0: stfun = cpu_stq_kernel; break; |
| 694 |
case 1: stfun = cpu_stq_super; break; |
| 695 |
default:
|
| 696 |
case 2: stfun = cpu_stq_user; break; |
| 697 |
} |
| 698 |
#endif
|
| 699 |
|
| 700 |
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
| 701 |
target_ulong i; |
| 702 |
|
| 703 |
for (i = 0; i < base_reglist; i++) { |
| 704 |
stfun(env, addr, env->active_tc.gpr[multiple_regs[i]]); |
| 705 |
addr += 8;
|
| 706 |
} |
| 707 |
} |
| 708 |
|
| 709 |
if (do_r31) {
|
| 710 |
stfun(env, addr, env->active_tc.gpr[31]);
|
| 711 |
} |
| 712 |
} |
| 713 |
#endif
|
| 714 |
|
| 715 |
#ifndef CONFIG_USER_ONLY
|
| 716 |
/* SMP helpers. */
|
| 717 |
static bool mips_vpe_is_wfi(MIPSCPU *c) |
| 718 |
{
|
| 719 |
CPUMIPSState *env = &c->env; |
| 720 |
|
| 721 |
/* If the VPE is halted but otherwise active, it means it's waiting for
|
| 722 |
an interrupt. */
|
| 723 |
return env->halted && mips_vpe_active(env);
|
| 724 |
} |
| 725 |
|
| 726 |
static inline void mips_vpe_wake(CPUMIPSState *c) |
| 727 |
{
|
| 728 |
/* Dont set ->halted = 0 directly, let it be done via cpu_has_work
|
| 729 |
because there might be other conditions that state that c should
|
| 730 |
be sleeping. */
|
| 731 |
cpu_interrupt(c, CPU_INTERRUPT_WAKE); |
| 732 |
} |
| 733 |
|
| 734 |
static inline void mips_vpe_sleep(MIPSCPU *cpu) |
| 735 |
{
|
| 736 |
CPUMIPSState *c = &cpu->env; |
| 737 |
|
| 738 |
/* The VPE was shut off, really go to bed.
|
| 739 |
Reset any old _WAKE requests. */
|
| 740 |
c->halted = 1;
|
| 741 |
cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE); |
| 742 |
} |
| 743 |
|
| 744 |
static inline void mips_tc_wake(MIPSCPU *cpu, int tc) |
| 745 |
{
|
| 746 |
CPUMIPSState *c = &cpu->env; |
| 747 |
|
| 748 |
/* FIXME: TC reschedule. */
|
| 749 |
if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
|
| 750 |
mips_vpe_wake(c); |
| 751 |
} |
| 752 |
} |
| 753 |
|
| 754 |
static inline void mips_tc_sleep(MIPSCPU *cpu, int tc) |
| 755 |
{
|
| 756 |
CPUMIPSState *c = &cpu->env; |
| 757 |
|
| 758 |
/* FIXME: TC reschedule. */
|
| 759 |
if (!mips_vpe_active(c)) {
|
| 760 |
mips_vpe_sleep(cpu); |
| 761 |
} |
| 762 |
} |
| 763 |
|
| 764 |
/* tc should point to an int with the value of the global TC index.
|
| 765 |
This function will transform it into a local index within the
|
| 766 |
returned CPUMIPSState.
|
| 767 |
|
| 768 |
FIXME: This code assumes that all VPEs have the same number of TCs,
|
| 769 |
which depends on runtime setup. Can probably be fixed by
|
| 770 |
walking the list of CPUMIPSStates. */
|
| 771 |
static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) |
| 772 |
{
|
| 773 |
CPUMIPSState *other; |
| 774 |
int vpe_idx, nr_threads = env->nr_threads;
|
| 775 |
int tc_idx = *tc;
|
| 776 |
|
| 777 |
if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { |
| 778 |
/* Not allowed to address other CPUs. */
|
| 779 |
*tc = env->current_tc; |
| 780 |
return env;
|
| 781 |
} |
| 782 |
|
| 783 |
vpe_idx = tc_idx / nr_threads; |
| 784 |
*tc = tc_idx % nr_threads; |
| 785 |
other = qemu_get_cpu(vpe_idx); |
| 786 |
return other ? other : env;
|
| 787 |
} |
| 788 |
|
| 789 |
/* The per VPE CP0_Status register shares some fields with the per TC
|
| 790 |
CP0_TCStatus registers. These fields are wired to the same registers,
|
| 791 |
so changes to either of them should be reflected on both registers.
|
| 792 |
|
| 793 |
Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
|
| 794 |
|
| 795 |
These helper call synchronizes the regs for a given cpu. */
|
| 796 |
|
| 797 |
/* Called for updates to CP0_Status. */
|
| 798 |
static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) |
| 799 |
{
|
| 800 |
int32_t tcstatus, *tcst; |
| 801 |
uint32_t v = cpu->CP0_Status; |
| 802 |
uint32_t cu, mx, asid, ksu; |
| 803 |
uint32_t mask = ((1 << CP0TCSt_TCU3)
|
| 804 |
| (1 << CP0TCSt_TCU2)
|
| 805 |
| (1 << CP0TCSt_TCU1)
|
| 806 |
| (1 << CP0TCSt_TCU0)
|
| 807 |
| (1 << CP0TCSt_TMX)
|
| 808 |
| (3 << CP0TCSt_TKSU)
|
| 809 |
| (0xff << CP0TCSt_TASID));
|
| 810 |
|
| 811 |
cu = (v >> CP0St_CU0) & 0xf;
|
| 812 |
mx = (v >> CP0St_MX) & 0x1;
|
| 813 |
ksu = (v >> CP0St_KSU) & 0x3;
|
| 814 |
asid = env->CP0_EntryHi & 0xff;
|
| 815 |
|
| 816 |
tcstatus = cu << CP0TCSt_TCU0; |
| 817 |
tcstatus |= mx << CP0TCSt_TMX; |
| 818 |
tcstatus |= ksu << CP0TCSt_TKSU; |
| 819 |
tcstatus |= asid; |
| 820 |
|
| 821 |
if (tc == cpu->current_tc) {
|
| 822 |
tcst = &cpu->active_tc.CP0_TCStatus; |
| 823 |
} else {
|
| 824 |
tcst = &cpu->tcs[tc].CP0_TCStatus; |
| 825 |
} |
| 826 |
|
| 827 |
*tcst &= ~mask; |
| 828 |
*tcst |= tcstatus; |
| 829 |
compute_hflags(cpu); |
| 830 |
} |
| 831 |
|
| 832 |
/* Called for updates to CP0_TCStatus. */
|
| 833 |
static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, |
| 834 |
target_ulong v) |
| 835 |
{
|
| 836 |
uint32_t status; |
| 837 |
uint32_t tcu, tmx, tasid, tksu; |
| 838 |
uint32_t mask = ((1 << CP0St_CU3)
|
| 839 |
| (1 << CP0St_CU2)
|
| 840 |
| (1 << CP0St_CU1)
|
| 841 |
| (1 << CP0St_CU0)
|
| 842 |
| (1 << CP0St_MX)
|
| 843 |
| (3 << CP0St_KSU));
|
| 844 |
|
| 845 |
tcu = (v >> CP0TCSt_TCU0) & 0xf;
|
| 846 |
tmx = (v >> CP0TCSt_TMX) & 0x1;
|
| 847 |
tasid = v & 0xff;
|
| 848 |
tksu = (v >> CP0TCSt_TKSU) & 0x3;
|
| 849 |
|
| 850 |
status = tcu << CP0St_CU0; |
| 851 |
status |= tmx << CP0St_MX; |
| 852 |
status |= tksu << CP0St_KSU; |
| 853 |
|
| 854 |
cpu->CP0_Status &= ~mask; |
| 855 |
cpu->CP0_Status |= status; |
| 856 |
|
| 857 |
/* Sync the TASID with EntryHi. */
|
| 858 |
cpu->CP0_EntryHi &= ~0xff;
|
| 859 |
cpu->CP0_EntryHi = tasid; |
| 860 |
|
| 861 |
compute_hflags(cpu); |
| 862 |
} |
| 863 |
|
| 864 |
/* Called for updates to CP0_EntryHi. */
|
| 865 |
static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) |
| 866 |
{
|
| 867 |
int32_t *tcst; |
| 868 |
uint32_t asid, v = cpu->CP0_EntryHi; |
| 869 |
|
| 870 |
asid = v & 0xff;
|
| 871 |
|
| 872 |
if (tc == cpu->current_tc) {
|
| 873 |
tcst = &cpu->active_tc.CP0_TCStatus; |
| 874 |
} else {
|
| 875 |
tcst = &cpu->tcs[tc].CP0_TCStatus; |
| 876 |
} |
| 877 |
|
| 878 |
*tcst &= ~0xff;
|
| 879 |
*tcst |= asid; |
| 880 |
} |
| 881 |
|
| 882 |
/* CP0 helpers */
|
| 883 |
target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) |
| 884 |
{
|
| 885 |
return env->mvp->CP0_MVPControl;
|
| 886 |
} |
| 887 |
|
| 888 |
target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env) |
| 889 |
{
|
| 890 |
return env->mvp->CP0_MVPConf0;
|
| 891 |
} |
| 892 |
|
| 893 |
target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env) |
| 894 |
{
|
| 895 |
return env->mvp->CP0_MVPConf1;
|
| 896 |
} |
| 897 |
|
| 898 |
target_ulong helper_mfc0_random(CPUMIPSState *env) |
| 899 |
{
|
| 900 |
return (int32_t)cpu_mips_get_random(env);
|
| 901 |
} |
| 902 |
|
| 903 |
target_ulong helper_mfc0_tcstatus(CPUMIPSState *env) |
| 904 |
{
|
| 905 |
return env->active_tc.CP0_TCStatus;
|
| 906 |
} |
| 907 |
|
| 908 |
target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) |
| 909 |
{
|
| 910 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 911 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 912 |
|
| 913 |
if (other_tc == other->current_tc)
|
| 914 |
return other->active_tc.CP0_TCStatus;
|
| 915 |
else
|
| 916 |
return other->tcs[other_tc].CP0_TCStatus;
|
| 917 |
} |
| 918 |
|
| 919 |
target_ulong helper_mfc0_tcbind(CPUMIPSState *env) |
| 920 |
{
|
| 921 |
return env->active_tc.CP0_TCBind;
|
| 922 |
} |
| 923 |
|
| 924 |
target_ulong helper_mftc0_tcbind(CPUMIPSState *env) |
| 925 |
{
|
| 926 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 927 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 928 |
|
| 929 |
if (other_tc == other->current_tc)
|
| 930 |
return other->active_tc.CP0_TCBind;
|
| 931 |
else
|
| 932 |
return other->tcs[other_tc].CP0_TCBind;
|
| 933 |
} |
| 934 |
|
| 935 |
target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) |
| 936 |
{
|
| 937 |
return env->active_tc.PC;
|
| 938 |
} |
| 939 |
|
| 940 |
target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) |
| 941 |
{
|
| 942 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 943 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 944 |
|
| 945 |
if (other_tc == other->current_tc)
|
| 946 |
return other->active_tc.PC;
|
| 947 |
else
|
| 948 |
return other->tcs[other_tc].PC;
|
| 949 |
} |
| 950 |
|
| 951 |
target_ulong helper_mfc0_tchalt(CPUMIPSState *env) |
| 952 |
{
|
| 953 |
return env->active_tc.CP0_TCHalt;
|
| 954 |
} |
| 955 |
|
| 956 |
target_ulong helper_mftc0_tchalt(CPUMIPSState *env) |
| 957 |
{
|
| 958 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 959 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 960 |
|
| 961 |
if (other_tc == other->current_tc)
|
| 962 |
return other->active_tc.CP0_TCHalt;
|
| 963 |
else
|
| 964 |
return other->tcs[other_tc].CP0_TCHalt;
|
| 965 |
} |
| 966 |
|
| 967 |
target_ulong helper_mfc0_tccontext(CPUMIPSState *env) |
| 968 |
{
|
| 969 |
return env->active_tc.CP0_TCContext;
|
| 970 |
} |
| 971 |
|
| 972 |
target_ulong helper_mftc0_tccontext(CPUMIPSState *env) |
| 973 |
{
|
| 974 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 975 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 976 |
|
| 977 |
if (other_tc == other->current_tc)
|
| 978 |
return other->active_tc.CP0_TCContext;
|
| 979 |
else
|
| 980 |
return other->tcs[other_tc].CP0_TCContext;
|
| 981 |
} |
| 982 |
|
| 983 |
target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) |
| 984 |
{
|
| 985 |
return env->active_tc.CP0_TCSchedule;
|
| 986 |
} |
| 987 |
|
| 988 |
target_ulong helper_mftc0_tcschedule(CPUMIPSState *env) |
| 989 |
{
|
| 990 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 991 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 992 |
|
| 993 |
if (other_tc == other->current_tc)
|
| 994 |
return other->active_tc.CP0_TCSchedule;
|
| 995 |
else
|
| 996 |
return other->tcs[other_tc].CP0_TCSchedule;
|
| 997 |
} |
| 998 |
|
| 999 |
target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) |
| 1000 |
{
|
| 1001 |
return env->active_tc.CP0_TCScheFBack;
|
| 1002 |
} |
| 1003 |
|
| 1004 |
target_ulong helper_mftc0_tcschefback(CPUMIPSState *env) |
| 1005 |
{
|
| 1006 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1007 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1008 |
|
| 1009 |
if (other_tc == other->current_tc)
|
| 1010 |
return other->active_tc.CP0_TCScheFBack;
|
| 1011 |
else
|
| 1012 |
return other->tcs[other_tc].CP0_TCScheFBack;
|
| 1013 |
} |
| 1014 |
|
| 1015 |
target_ulong helper_mfc0_count(CPUMIPSState *env) |
| 1016 |
{
|
| 1017 |
return (int32_t)cpu_mips_get_count(env);
|
| 1018 |
} |
| 1019 |
|
| 1020 |
target_ulong helper_mftc0_entryhi(CPUMIPSState *env) |
| 1021 |
{
|
| 1022 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1023 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1024 |
|
| 1025 |
return other->CP0_EntryHi;
|
| 1026 |
} |
| 1027 |
|
| 1028 |
target_ulong helper_mftc0_cause(CPUMIPSState *env) |
| 1029 |
{
|
| 1030 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1031 |
int32_t tccause; |
| 1032 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1033 |
|
| 1034 |
if (other_tc == other->current_tc) {
|
| 1035 |
tccause = other->CP0_Cause; |
| 1036 |
} else {
|
| 1037 |
tccause = other->CP0_Cause; |
| 1038 |
} |
| 1039 |
|
| 1040 |
return tccause;
|
| 1041 |
} |
| 1042 |
|
| 1043 |
target_ulong helper_mftc0_status(CPUMIPSState *env) |
| 1044 |
{
|
| 1045 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1046 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1047 |
|
| 1048 |
return other->CP0_Status;
|
| 1049 |
} |
| 1050 |
|
| 1051 |
target_ulong helper_mfc0_lladdr(CPUMIPSState *env) |
| 1052 |
{
|
| 1053 |
return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
|
| 1054 |
} |
| 1055 |
|
| 1056 |
target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel) |
| 1057 |
{
|
| 1058 |
return (int32_t)env->CP0_WatchLo[sel];
|
| 1059 |
} |
| 1060 |
|
| 1061 |
target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) |
| 1062 |
{
|
| 1063 |
return env->CP0_WatchHi[sel];
|
| 1064 |
} |
| 1065 |
|
| 1066 |
target_ulong helper_mfc0_debug(CPUMIPSState *env) |
| 1067 |
{
|
| 1068 |
target_ulong t0 = env->CP0_Debug; |
| 1069 |
if (env->hflags & MIPS_HFLAG_DM)
|
| 1070 |
t0 |= 1 << CP0DB_DM;
|
| 1071 |
|
| 1072 |
return t0;
|
| 1073 |
} |
| 1074 |
|
| 1075 |
target_ulong helper_mftc0_debug(CPUMIPSState *env) |
| 1076 |
{
|
| 1077 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1078 |
int32_t tcstatus; |
| 1079 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1080 |
|
| 1081 |
if (other_tc == other->current_tc)
|
| 1082 |
tcstatus = other->active_tc.CP0_Debug_tcstatus; |
| 1083 |
else
|
| 1084 |
tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus; |
| 1085 |
|
| 1086 |
/* XXX: Might be wrong, check with EJTAG spec. */
|
| 1087 |
return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
| 1088 |
(tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
| 1089 |
} |
| 1090 |
|
| 1091 |
#if defined(TARGET_MIPS64)
|
| 1092 |
target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env) |
| 1093 |
{
|
| 1094 |
return env->active_tc.PC;
|
| 1095 |
} |
| 1096 |
|
| 1097 |
target_ulong helper_dmfc0_tchalt(CPUMIPSState *env) |
| 1098 |
{
|
| 1099 |
return env->active_tc.CP0_TCHalt;
|
| 1100 |
} |
| 1101 |
|
| 1102 |
target_ulong helper_dmfc0_tccontext(CPUMIPSState *env) |
| 1103 |
{
|
| 1104 |
return env->active_tc.CP0_TCContext;
|
| 1105 |
} |
| 1106 |
|
| 1107 |
target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env) |
| 1108 |
{
|
| 1109 |
return env->active_tc.CP0_TCSchedule;
|
| 1110 |
} |
| 1111 |
|
| 1112 |
target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env) |
| 1113 |
{
|
| 1114 |
return env->active_tc.CP0_TCScheFBack;
|
| 1115 |
} |
| 1116 |
|
| 1117 |
target_ulong helper_dmfc0_lladdr(CPUMIPSState *env) |
| 1118 |
{
|
| 1119 |
return env->lladdr >> env->CP0_LLAddr_shift;
|
| 1120 |
} |
| 1121 |
|
| 1122 |
target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) |
| 1123 |
{
|
| 1124 |
return env->CP0_WatchLo[sel];
|
| 1125 |
} |
| 1126 |
#endif /* TARGET_MIPS64 */ |
| 1127 |
|
| 1128 |
void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
|
| 1129 |
{
|
| 1130 |
int num = 1; |
| 1131 |
unsigned int tmp = env->tlb->nb_tlb; |
| 1132 |
|
| 1133 |
do {
|
| 1134 |
tmp >>= 1;
|
| 1135 |
num <<= 1;
|
| 1136 |
} while (tmp);
|
| 1137 |
env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1)); |
| 1138 |
} |
| 1139 |
|
| 1140 |
void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
|
| 1141 |
{
|
| 1142 |
uint32_t mask = 0;
|
| 1143 |
uint32_t newval; |
| 1144 |
|
| 1145 |
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) |
| 1146 |
mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | |
| 1147 |
(1 << CP0MVPCo_EVP);
|
| 1148 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 1149 |
mask |= (1 << CP0MVPCo_STLB);
|
| 1150 |
newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); |
| 1151 |
|
| 1152 |
// TODO: Enable/disable shared TLB, enable/disable VPEs.
|
| 1153 |
|
| 1154 |
env->mvp->CP0_MVPControl = newval; |
| 1155 |
} |
| 1156 |
|
| 1157 |
void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
|
| 1158 |
{
|
| 1159 |
uint32_t mask; |
| 1160 |
uint32_t newval; |
| 1161 |
|
| 1162 |
mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | |
| 1163 |
(1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); |
| 1164 |
newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); |
| 1165 |
|
| 1166 |
/* Yield scheduler intercept not implemented. */
|
| 1167 |
/* Gating storage scheduler intercept not implemented. */
|
| 1168 |
|
| 1169 |
// TODO: Enable/disable TCs.
|
| 1170 |
|
| 1171 |
env->CP0_VPEControl = newval; |
| 1172 |
} |
| 1173 |
|
| 1174 |
void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
|
| 1175 |
{
|
| 1176 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1177 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1178 |
uint32_t mask; |
| 1179 |
uint32_t newval; |
| 1180 |
|
| 1181 |
mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | |
| 1182 |
(1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); |
| 1183 |
newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask); |
| 1184 |
|
| 1185 |
/* TODO: Enable/disable TCs. */
|
| 1186 |
|
| 1187 |
other->CP0_VPEControl = newval; |
| 1188 |
} |
| 1189 |
|
| 1190 |
target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env) |
| 1191 |
{
|
| 1192 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1193 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1194 |
/* FIXME: Mask away return zero on read bits. */
|
| 1195 |
return other->CP0_VPEControl;
|
| 1196 |
} |
| 1197 |
|
| 1198 |
target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env) |
| 1199 |
{
|
| 1200 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1201 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1202 |
|
| 1203 |
return other->CP0_VPEConf0;
|
| 1204 |
} |
| 1205 |
|
| 1206 |
void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
|
| 1207 |
{
|
| 1208 |
uint32_t mask = 0;
|
| 1209 |
uint32_t newval; |
| 1210 |
|
| 1211 |
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { |
| 1212 |
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) |
| 1213 |
mask |= (0xff << CP0VPEC0_XTC);
|
| 1214 |
mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
| 1215 |
} |
| 1216 |
newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); |
| 1217 |
|
| 1218 |
// TODO: TC exclusive handling due to ERL/EXL.
|
| 1219 |
|
| 1220 |
env->CP0_VPEConf0 = newval; |
| 1221 |
} |
| 1222 |
|
| 1223 |
void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
|
| 1224 |
{
|
| 1225 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1226 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1227 |
uint32_t mask = 0;
|
| 1228 |
uint32_t newval; |
| 1229 |
|
| 1230 |
mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
| 1231 |
newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask); |
| 1232 |
|
| 1233 |
/* TODO: TC exclusive handling due to ERL/EXL. */
|
| 1234 |
other->CP0_VPEConf0 = newval; |
| 1235 |
} |
| 1236 |
|
| 1237 |
void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
|
| 1238 |
{
|
| 1239 |
uint32_t mask = 0;
|
| 1240 |
uint32_t newval; |
| 1241 |
|
| 1242 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 1243 |
mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | |
| 1244 |
(0xff << CP0VPEC1_NCP1);
|
| 1245 |
newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); |
| 1246 |
|
| 1247 |
/* UDI not implemented. */
|
| 1248 |
/* CP2 not implemented. */
|
| 1249 |
|
| 1250 |
// TODO: Handle FPU (CP1) binding.
|
| 1251 |
|
| 1252 |
env->CP0_VPEConf1 = newval; |
| 1253 |
} |
| 1254 |
|
| 1255 |
void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
|
| 1256 |
{
|
| 1257 |
/* Yield qualifier inputs not implemented. */
|
| 1258 |
env->CP0_YQMask = 0x00000000;
|
| 1259 |
} |
| 1260 |
|
| 1261 |
void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
|
| 1262 |
{
|
| 1263 |
env->CP0_VPEOpt = arg1 & 0x0000ffff;
|
| 1264 |
} |
| 1265 |
|
| 1266 |
void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
|
| 1267 |
{
|
| 1268 |
/* Large physaddr (PABITS) not implemented */
|
| 1269 |
/* 1k pages not implemented */
|
| 1270 |
env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
|
| 1271 |
} |
| 1272 |
|
| 1273 |
void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
|
| 1274 |
{
|
| 1275 |
uint32_t mask = env->CP0_TCStatus_rw_bitmask; |
| 1276 |
uint32_t newval; |
| 1277 |
|
| 1278 |
newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); |
| 1279 |
|
| 1280 |
env->active_tc.CP0_TCStatus = newval; |
| 1281 |
sync_c0_tcstatus(env, env->current_tc, newval); |
| 1282 |
} |
| 1283 |
|
| 1284 |
void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
|
| 1285 |
{
|
| 1286 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1287 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1288 |
|
| 1289 |
if (other_tc == other->current_tc)
|
| 1290 |
other->active_tc.CP0_TCStatus = arg1; |
| 1291 |
else
|
| 1292 |
other->tcs[other_tc].CP0_TCStatus = arg1; |
| 1293 |
sync_c0_tcstatus(other, other_tc, arg1); |
| 1294 |
} |
| 1295 |
|
| 1296 |
void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
|
| 1297 |
{
|
| 1298 |
uint32_t mask = (1 << CP0TCBd_TBE);
|
| 1299 |
uint32_t newval; |
| 1300 |
|
| 1301 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 1302 |
mask |= (1 << CP0TCBd_CurVPE);
|
| 1303 |
newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
| 1304 |
env->active_tc.CP0_TCBind = newval; |
| 1305 |
} |
| 1306 |
|
| 1307 |
void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
|
| 1308 |
{
|
| 1309 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1310 |
uint32_t mask = (1 << CP0TCBd_TBE);
|
| 1311 |
uint32_t newval; |
| 1312 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1313 |
|
| 1314 |
if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 1315 |
mask |= (1 << CP0TCBd_CurVPE);
|
| 1316 |
if (other_tc == other->current_tc) {
|
| 1317 |
newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
| 1318 |
other->active_tc.CP0_TCBind = newval; |
| 1319 |
} else {
|
| 1320 |
newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask); |
| 1321 |
other->tcs[other_tc].CP0_TCBind = newval; |
| 1322 |
} |
| 1323 |
} |
| 1324 |
|
| 1325 |
void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
|
| 1326 |
{
|
| 1327 |
env->active_tc.PC = arg1; |
| 1328 |
env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
|
| 1329 |
env->lladdr = 0ULL;
|
| 1330 |
/* MIPS16 not implemented. */
|
| 1331 |
} |
| 1332 |
|
| 1333 |
void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
|
| 1334 |
{
|
| 1335 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1336 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1337 |
|
| 1338 |
if (other_tc == other->current_tc) {
|
| 1339 |
other->active_tc.PC = arg1; |
| 1340 |
other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
|
| 1341 |
other->lladdr = 0ULL;
|
| 1342 |
/* MIPS16 not implemented. */
|
| 1343 |
} else {
|
| 1344 |
other->tcs[other_tc].PC = arg1; |
| 1345 |
other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
|
| 1346 |
other->lladdr = 0ULL;
|
| 1347 |
/* MIPS16 not implemented. */
|
| 1348 |
} |
| 1349 |
} |
| 1350 |
|
| 1351 |
void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
|
| 1352 |
{
|
| 1353 |
MIPSCPU *cpu = mips_env_get_cpu(env); |
| 1354 |
|
| 1355 |
env->active_tc.CP0_TCHalt = arg1 & 0x1;
|
| 1356 |
|
| 1357 |
// TODO: Halt TC / Restart (if allocated+active) TC.
|
| 1358 |
if (env->active_tc.CP0_TCHalt & 1) { |
| 1359 |
mips_tc_sleep(cpu, env->current_tc); |
| 1360 |
} else {
|
| 1361 |
mips_tc_wake(cpu, env->current_tc); |
| 1362 |
} |
| 1363 |
} |
| 1364 |
|
| 1365 |
void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
|
| 1366 |
{
|
| 1367 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1368 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1369 |
MIPSCPU *other_cpu = mips_env_get_cpu(other); |
| 1370 |
|
| 1371 |
// TODO: Halt TC / Restart (if allocated+active) TC.
|
| 1372 |
|
| 1373 |
if (other_tc == other->current_tc)
|
| 1374 |
other->active_tc.CP0_TCHalt = arg1; |
| 1375 |
else
|
| 1376 |
other->tcs[other_tc].CP0_TCHalt = arg1; |
| 1377 |
|
| 1378 |
if (arg1 & 1) { |
| 1379 |
mips_tc_sleep(other_cpu, other_tc); |
| 1380 |
} else {
|
| 1381 |
mips_tc_wake(other_cpu, other_tc); |
| 1382 |
} |
| 1383 |
} |
| 1384 |
|
| 1385 |
void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
|
| 1386 |
{
|
| 1387 |
env->active_tc.CP0_TCContext = arg1; |
| 1388 |
} |
| 1389 |
|
| 1390 |
void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
|
| 1391 |
{
|
| 1392 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1393 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1394 |
|
| 1395 |
if (other_tc == other->current_tc)
|
| 1396 |
other->active_tc.CP0_TCContext = arg1; |
| 1397 |
else
|
| 1398 |
other->tcs[other_tc].CP0_TCContext = arg1; |
| 1399 |
} |
| 1400 |
|
| 1401 |
void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
|
| 1402 |
{
|
| 1403 |
env->active_tc.CP0_TCSchedule = arg1; |
| 1404 |
} |
| 1405 |
|
| 1406 |
void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
|
| 1407 |
{
|
| 1408 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1409 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1410 |
|
| 1411 |
if (other_tc == other->current_tc)
|
| 1412 |
other->active_tc.CP0_TCSchedule = arg1; |
| 1413 |
else
|
| 1414 |
other->tcs[other_tc].CP0_TCSchedule = arg1; |
| 1415 |
} |
| 1416 |
|
| 1417 |
void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
|
| 1418 |
{
|
| 1419 |
env->active_tc.CP0_TCScheFBack = arg1; |
| 1420 |
} |
| 1421 |
|
| 1422 |
void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
|
| 1423 |
{
|
| 1424 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1425 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1426 |
|
| 1427 |
if (other_tc == other->current_tc)
|
| 1428 |
other->active_tc.CP0_TCScheFBack = arg1; |
| 1429 |
else
|
| 1430 |
other->tcs[other_tc].CP0_TCScheFBack = arg1; |
| 1431 |
} |
| 1432 |
|
| 1433 |
void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
|
| 1434 |
{
|
| 1435 |
/* Large physaddr (PABITS) not implemented */
|
| 1436 |
/* 1k pages not implemented */
|
| 1437 |
env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
|
| 1438 |
} |
| 1439 |
|
| 1440 |
void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
|
| 1441 |
{
|
| 1442 |
env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); |
| 1443 |
} |
| 1444 |
|
| 1445 |
void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
|
| 1446 |
{
|
| 1447 |
/* 1k pages not implemented */
|
| 1448 |
env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); |
| 1449 |
} |
| 1450 |
|
| 1451 |
void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
|
| 1452 |
{
|
| 1453 |
/* SmartMIPS not implemented */
|
| 1454 |
/* Large physaddr (PABITS) not implemented */
|
| 1455 |
/* 1k pages not implemented */
|
| 1456 |
env->CP0_PageGrain = 0;
|
| 1457 |
} |
| 1458 |
|
| 1459 |
void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
|
| 1460 |
{
|
| 1461 |
env->CP0_Wired = arg1 % env->tlb->nb_tlb; |
| 1462 |
} |
| 1463 |
|
| 1464 |
void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
|
| 1465 |
{
|
| 1466 |
env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; |
| 1467 |
} |
| 1468 |
|
| 1469 |
void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
|
| 1470 |
{
|
| 1471 |
env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; |
| 1472 |
} |
| 1473 |
|
| 1474 |
void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
|
| 1475 |
{
|
| 1476 |
env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; |
| 1477 |
} |
| 1478 |
|
| 1479 |
void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
|
| 1480 |
{
|
| 1481 |
env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; |
| 1482 |
} |
| 1483 |
|
| 1484 |
void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
|
| 1485 |
{
|
| 1486 |
env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; |
| 1487 |
} |
| 1488 |
|
| 1489 |
void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
|
| 1490 |
{
|
| 1491 |
env->CP0_HWREna = arg1 & 0x0000000F;
|
| 1492 |
} |
| 1493 |
|
| 1494 |
void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
|
| 1495 |
{
|
| 1496 |
cpu_mips_store_count(env, arg1); |
| 1497 |
} |
| 1498 |
|
| 1499 |
void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
|
| 1500 |
{
|
| 1501 |
target_ulong old, val; |
| 1502 |
|
| 1503 |
/* 1k pages not implemented */
|
| 1504 |
val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF); |
| 1505 |
#if defined(TARGET_MIPS64)
|
| 1506 |
val &= env->SEGMask; |
| 1507 |
#endif
|
| 1508 |
old = env->CP0_EntryHi; |
| 1509 |
env->CP0_EntryHi = val; |
| 1510 |
if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
| 1511 |
sync_c0_entryhi(env, env->current_tc); |
| 1512 |
} |
| 1513 |
/* If the ASID changes, flush qemu's TLB. */
|
| 1514 |
if ((old & 0xFF) != (val & 0xFF)) |
| 1515 |
cpu_mips_tlb_flush(env, 1);
|
| 1516 |
} |
| 1517 |
|
| 1518 |
void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
|
| 1519 |
{
|
| 1520 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1521 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1522 |
|
| 1523 |
other->CP0_EntryHi = arg1; |
| 1524 |
sync_c0_entryhi(other, other_tc); |
| 1525 |
} |
| 1526 |
|
| 1527 |
void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
|
| 1528 |
{
|
| 1529 |
cpu_mips_store_compare(env, arg1); |
| 1530 |
} |
| 1531 |
|
| 1532 |
void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
|
| 1533 |
{
|
| 1534 |
uint32_t val, old; |
| 1535 |
uint32_t mask = env->CP0_Status_rw_bitmask; |
| 1536 |
|
| 1537 |
val = arg1 & mask; |
| 1538 |
old = env->CP0_Status; |
| 1539 |
env->CP0_Status = (env->CP0_Status & ~mask) | val; |
| 1540 |
if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
| 1541 |
sync_c0_status(env, env, env->current_tc); |
| 1542 |
} else {
|
| 1543 |
compute_hflags(env); |
| 1544 |
} |
| 1545 |
|
| 1546 |
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
| 1547 |
qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
|
| 1548 |
old, old & env->CP0_Cause & CP0Ca_IP_mask, |
| 1549 |
val, val & env->CP0_Cause & CP0Ca_IP_mask, |
| 1550 |
env->CP0_Cause); |
| 1551 |
switch (env->hflags & MIPS_HFLAG_KSU) {
|
| 1552 |
case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; |
| 1553 |
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; |
| 1554 |
case MIPS_HFLAG_KM: qemu_log("\n"); break; |
| 1555 |
default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
| 1556 |
} |
| 1557 |
} |
| 1558 |
} |
| 1559 |
|
| 1560 |
void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
|
| 1561 |
{
|
| 1562 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1563 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1564 |
|
| 1565 |
other->CP0_Status = arg1 & ~0xf1000018;
|
| 1566 |
sync_c0_status(env, other, other_tc); |
| 1567 |
} |
| 1568 |
|
| 1569 |
void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
|
| 1570 |
{
|
| 1571 |
/* vectored interrupts not implemented, no performance counters. */
|
| 1572 |
env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0); |
| 1573 |
} |
| 1574 |
|
| 1575 |
void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
|
| 1576 |
{
|
| 1577 |
uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); |
| 1578 |
env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); |
| 1579 |
} |
| 1580 |
|
| 1581 |
static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1) |
| 1582 |
{
|
| 1583 |
uint32_t mask = 0x00C00300;
|
| 1584 |
uint32_t old = cpu->CP0_Cause; |
| 1585 |
int i;
|
| 1586 |
|
| 1587 |
if (cpu->insn_flags & ISA_MIPS32R2) {
|
| 1588 |
mask |= 1 << CP0Ca_DC;
|
| 1589 |
} |
| 1590 |
|
| 1591 |
cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask); |
| 1592 |
|
| 1593 |
if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) { |
| 1594 |
if (cpu->CP0_Cause & (1 << CP0Ca_DC)) { |
| 1595 |
cpu_mips_stop_count(cpu); |
| 1596 |
} else {
|
| 1597 |
cpu_mips_start_count(cpu); |
| 1598 |
} |
| 1599 |
} |
| 1600 |
|
| 1601 |
/* Set/reset software interrupts */
|
| 1602 |
for (i = 0 ; i < 2 ; i++) { |
| 1603 |
if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) { |
| 1604 |
cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
|
| 1605 |
} |
| 1606 |
} |
| 1607 |
} |
| 1608 |
|
| 1609 |
void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
|
| 1610 |
{
|
| 1611 |
mtc0_cause(env, arg1); |
| 1612 |
} |
| 1613 |
|
| 1614 |
void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
|
| 1615 |
{
|
| 1616 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1617 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1618 |
|
| 1619 |
mtc0_cause(other, arg1); |
| 1620 |
} |
| 1621 |
|
| 1622 |
target_ulong helper_mftc0_epc(CPUMIPSState *env) |
| 1623 |
{
|
| 1624 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1625 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1626 |
|
| 1627 |
return other->CP0_EPC;
|
| 1628 |
} |
| 1629 |
|
| 1630 |
target_ulong helper_mftc0_ebase(CPUMIPSState *env) |
| 1631 |
{
|
| 1632 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1633 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1634 |
|
| 1635 |
return other->CP0_EBase;
|
| 1636 |
} |
| 1637 |
|
| 1638 |
void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
|
| 1639 |
{
|
| 1640 |
/* vectored interrupts not implemented */
|
| 1641 |
env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); |
| 1642 |
} |
| 1643 |
|
| 1644 |
void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
|
| 1645 |
{
|
| 1646 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1647 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1648 |
other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); |
| 1649 |
} |
| 1650 |
|
| 1651 |
target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx) |
| 1652 |
{
|
| 1653 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1654 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1655 |
|
| 1656 |
switch (idx) {
|
| 1657 |
case 0: return other->CP0_Config0; |
| 1658 |
case 1: return other->CP0_Config1; |
| 1659 |
case 2: return other->CP0_Config2; |
| 1660 |
case 3: return other->CP0_Config3; |
| 1661 |
/* 4 and 5 are reserved. */
|
| 1662 |
case 6: return other->CP0_Config6; |
| 1663 |
case 7: return other->CP0_Config7; |
| 1664 |
default:
|
| 1665 |
break;
|
| 1666 |
} |
| 1667 |
return 0; |
| 1668 |
} |
| 1669 |
|
| 1670 |
void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
|
| 1671 |
{
|
| 1672 |
env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); |
| 1673 |
} |
| 1674 |
|
| 1675 |
void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
|
| 1676 |
{
|
| 1677 |
/* tertiary/secondary caches not implemented */
|
| 1678 |
env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
|
| 1679 |
} |
| 1680 |
|
| 1681 |
void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
|
| 1682 |
{
|
| 1683 |
target_long mask = env->CP0_LLAddr_rw_bitmask; |
| 1684 |
arg1 = arg1 << env->CP0_LLAddr_shift; |
| 1685 |
env->lladdr = (env->lladdr & ~mask) | (arg1 & mask); |
| 1686 |
} |
| 1687 |
|
| 1688 |
void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
|
| 1689 |
{
|
| 1690 |
/* Watch exceptions for instructions, data loads, data stores
|
| 1691 |
not implemented. */
|
| 1692 |
env->CP0_WatchLo[sel] = (arg1 & ~0x7);
|
| 1693 |
} |
| 1694 |
|
| 1695 |
void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
|
| 1696 |
{
|
| 1697 |
env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
|
| 1698 |
env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
|
| 1699 |
} |
| 1700 |
|
| 1701 |
void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
|
| 1702 |
{
|
| 1703 |
target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; |
| 1704 |
env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); |
| 1705 |
} |
| 1706 |
|
| 1707 |
void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
|
| 1708 |
{
|
| 1709 |
env->CP0_Framemask = arg1; /* XXX */
|
| 1710 |
} |
| 1711 |
|
| 1712 |
void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
|
| 1713 |
{
|
| 1714 |
env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); |
| 1715 |
if (arg1 & (1 << CP0DB_DM)) |
| 1716 |
env->hflags |= MIPS_HFLAG_DM; |
| 1717 |
else
|
| 1718 |
env->hflags &= ~MIPS_HFLAG_DM; |
| 1719 |
} |
| 1720 |
|
| 1721 |
void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
|
| 1722 |
{
|
| 1723 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1724 |
uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); |
| 1725 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1726 |
|
| 1727 |
/* XXX: Might be wrong, check with EJTAG spec. */
|
| 1728 |
if (other_tc == other->current_tc)
|
| 1729 |
other->active_tc.CP0_Debug_tcstatus = val; |
| 1730 |
else
|
| 1731 |
other->tcs[other_tc].CP0_Debug_tcstatus = val; |
| 1732 |
other->CP0_Debug = (other->CP0_Debug & |
| 1733 |
((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
| 1734 |
(arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
| 1735 |
} |
| 1736 |
|
| 1737 |
void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
|
| 1738 |
{
|
| 1739 |
env->CP0_Performance0 = arg1 & 0x000007ff;
|
| 1740 |
} |
| 1741 |
|
| 1742 |
void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
|
| 1743 |
{
|
| 1744 |
env->CP0_TagLo = arg1 & 0xFFFFFCF6;
|
| 1745 |
} |
| 1746 |
|
| 1747 |
void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
|
| 1748 |
{
|
| 1749 |
env->CP0_DataLo = arg1; /* XXX */
|
| 1750 |
} |
| 1751 |
|
| 1752 |
void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
|
| 1753 |
{
|
| 1754 |
env->CP0_TagHi = arg1; /* XXX */
|
| 1755 |
} |
| 1756 |
|
| 1757 |
void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
|
| 1758 |
{
|
| 1759 |
env->CP0_DataHi = arg1; /* XXX */
|
| 1760 |
} |
| 1761 |
|
| 1762 |
/* MIPS MT functions */
|
| 1763 |
target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel) |
| 1764 |
{
|
| 1765 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1766 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1767 |
|
| 1768 |
if (other_tc == other->current_tc)
|
| 1769 |
return other->active_tc.gpr[sel];
|
| 1770 |
else
|
| 1771 |
return other->tcs[other_tc].gpr[sel];
|
| 1772 |
} |
| 1773 |
|
| 1774 |
target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) |
| 1775 |
{
|
| 1776 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1777 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1778 |
|
| 1779 |
if (other_tc == other->current_tc)
|
| 1780 |
return other->active_tc.LO[sel];
|
| 1781 |
else
|
| 1782 |
return other->tcs[other_tc].LO[sel];
|
| 1783 |
} |
| 1784 |
|
| 1785 |
target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) |
| 1786 |
{
|
| 1787 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1788 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1789 |
|
| 1790 |
if (other_tc == other->current_tc)
|
| 1791 |
return other->active_tc.HI[sel];
|
| 1792 |
else
|
| 1793 |
return other->tcs[other_tc].HI[sel];
|
| 1794 |
} |
| 1795 |
|
| 1796 |
target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) |
| 1797 |
{
|
| 1798 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1799 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1800 |
|
| 1801 |
if (other_tc == other->current_tc)
|
| 1802 |
return other->active_tc.ACX[sel];
|
| 1803 |
else
|
| 1804 |
return other->tcs[other_tc].ACX[sel];
|
| 1805 |
} |
| 1806 |
|
| 1807 |
target_ulong helper_mftdsp(CPUMIPSState *env) |
| 1808 |
{
|
| 1809 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1810 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1811 |
|
| 1812 |
if (other_tc == other->current_tc)
|
| 1813 |
return other->active_tc.DSPControl;
|
| 1814 |
else
|
| 1815 |
return other->tcs[other_tc].DSPControl;
|
| 1816 |
} |
| 1817 |
|
| 1818 |
void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
|
| 1819 |
{
|
| 1820 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1821 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1822 |
|
| 1823 |
if (other_tc == other->current_tc)
|
| 1824 |
other->active_tc.gpr[sel] = arg1; |
| 1825 |
else
|
| 1826 |
other->tcs[other_tc].gpr[sel] = arg1; |
| 1827 |
} |
| 1828 |
|
| 1829 |
void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
|
| 1830 |
{
|
| 1831 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1832 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1833 |
|
| 1834 |
if (other_tc == other->current_tc)
|
| 1835 |
other->active_tc.LO[sel] = arg1; |
| 1836 |
else
|
| 1837 |
other->tcs[other_tc].LO[sel] = arg1; |
| 1838 |
} |
| 1839 |
|
| 1840 |
void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
|
| 1841 |
{
|
| 1842 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1843 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1844 |
|
| 1845 |
if (other_tc == other->current_tc)
|
| 1846 |
other->active_tc.HI[sel] = arg1; |
| 1847 |
else
|
| 1848 |
other->tcs[other_tc].HI[sel] = arg1; |
| 1849 |
} |
| 1850 |
|
| 1851 |
void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
|
| 1852 |
{
|
| 1853 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1854 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1855 |
|
| 1856 |
if (other_tc == other->current_tc)
|
| 1857 |
other->active_tc.ACX[sel] = arg1; |
| 1858 |
else
|
| 1859 |
other->tcs[other_tc].ACX[sel] = arg1; |
| 1860 |
} |
| 1861 |
|
| 1862 |
void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
|
| 1863 |
{
|
| 1864 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1865 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
| 1866 |
|
| 1867 |
if (other_tc == other->current_tc)
|
| 1868 |
other->active_tc.DSPControl = arg1; |
| 1869 |
else
|
| 1870 |
other->tcs[other_tc].DSPControl = arg1; |
| 1871 |
} |
| 1872 |
|
| 1873 |
/* MIPS MT functions */
|
| 1874 |
target_ulong helper_dmt(void)
|
| 1875 |
{
|
| 1876 |
// TODO
|
| 1877 |
return 0; |
| 1878 |
} |
| 1879 |
|
| 1880 |
target_ulong helper_emt(void)
|
| 1881 |
{
|
| 1882 |
// TODO
|
| 1883 |
return 0; |
| 1884 |
} |
| 1885 |
|
| 1886 |
target_ulong helper_dvpe(CPUMIPSState *env) |
| 1887 |
{
|
| 1888 |
CPUMIPSState *other_cpu_env = first_cpu; |
| 1889 |
target_ulong prev = env->mvp->CP0_MVPControl; |
| 1890 |
|
| 1891 |
do {
|
| 1892 |
/* Turn off all VPEs except the one executing the dvpe. */
|
| 1893 |
if (other_cpu_env != env) {
|
| 1894 |
MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env); |
| 1895 |
|
| 1896 |
other_cpu_env->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
|
| 1897 |
mips_vpe_sleep(other_cpu); |
| 1898 |
} |
| 1899 |
other_cpu_env = other_cpu_env->next_cpu; |
| 1900 |
} while (other_cpu_env);
|
| 1901 |
return prev;
|
| 1902 |
} |
| 1903 |
|
| 1904 |
target_ulong helper_evpe(CPUMIPSState *env) |
| 1905 |
{
|
| 1906 |
CPUMIPSState *other_cpu_env = first_cpu; |
| 1907 |
target_ulong prev = env->mvp->CP0_MVPControl; |
| 1908 |
|
| 1909 |
do {
|
| 1910 |
MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env); |
| 1911 |
|
| 1912 |
if (other_cpu_env != env
|
| 1913 |
/* If the VPE is WFI, don't disturb its sleep. */
|
| 1914 |
&& !mips_vpe_is_wfi(other_cpu)) {
|
| 1915 |
/* Enable the VPE. */
|
| 1916 |
other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
|
| 1917 |
mips_vpe_wake(other_cpu_env); /* And wake it up. */
|
| 1918 |
} |
| 1919 |
other_cpu_env = other_cpu_env->next_cpu; |
| 1920 |
} while (other_cpu_env);
|
| 1921 |
return prev;
|
| 1922 |
} |
| 1923 |
#endif /* !CONFIG_USER_ONLY */ |
| 1924 |
|
| 1925 |
void helper_fork(target_ulong arg1, target_ulong arg2)
|
| 1926 |
{
|
| 1927 |
// arg1 = rt, arg2 = rs
|
| 1928 |
arg1 = 0;
|
| 1929 |
// TODO: store to TC register
|
| 1930 |
} |
| 1931 |
|
| 1932 |
target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) |
| 1933 |
{
|
| 1934 |
target_long arg1 = arg; |
| 1935 |
|
| 1936 |
if (arg1 < 0) { |
| 1937 |
/* No scheduling policy implemented. */
|
| 1938 |
if (arg1 != -2) { |
| 1939 |
if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && |
| 1940 |
env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
|
| 1941 |
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
| 1942 |
env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
|
| 1943 |
helper_raise_exception(env, EXCP_THREAD); |
| 1944 |
} |
| 1945 |
} |
| 1946 |
} else if (arg1 == 0) { |
| 1947 |
if (0 /* TODO: TC underflow */) { |
| 1948 |
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
| 1949 |
helper_raise_exception(env, EXCP_THREAD); |
| 1950 |
} else {
|
| 1951 |
// TODO: Deallocate TC
|
| 1952 |
} |
| 1953 |
} else if (arg1 > 0) { |
| 1954 |
/* Yield qualifier inputs not implemented. */
|
| 1955 |
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
| 1956 |
env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
|
| 1957 |
helper_raise_exception(env, EXCP_THREAD); |
| 1958 |
} |
| 1959 |
return env->CP0_YQMask;
|
| 1960 |
} |
| 1961 |
|
| 1962 |
#ifndef CONFIG_USER_ONLY
|
| 1963 |
/* TLB management */
|
| 1964 |
static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global) |
| 1965 |
{
|
| 1966 |
/* Flush qemu's TLB and discard all shadowed entries. */
|
| 1967 |
tlb_flush (env, flush_global); |
| 1968 |
env->tlb->tlb_in_use = env->tlb->nb_tlb; |
| 1969 |
} |
| 1970 |
|
| 1971 |
static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first) |
| 1972 |
{
|
| 1973 |
/* Discard entries from env->tlb[first] onwards. */
|
| 1974 |
while (env->tlb->tlb_in_use > first) {
|
| 1975 |
r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
|
| 1976 |
} |
| 1977 |
} |
| 1978 |
|
| 1979 |
static void r4k_fill_tlb(CPUMIPSState *env, int idx) |
| 1980 |
{
|
| 1981 |
r4k_tlb_t *tlb; |
| 1982 |
|
| 1983 |
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
| 1984 |
tlb = &env->tlb->mmu.r4k.tlb[idx]; |
| 1985 |
tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
|
| 1986 |
#if defined(TARGET_MIPS64)
|
| 1987 |
tlb->VPN &= env->SEGMask; |
| 1988 |
#endif
|
| 1989 |
tlb->ASID = env->CP0_EntryHi & 0xFF;
|
| 1990 |
tlb->PageMask = env->CP0_PageMask; |
| 1991 |
tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
| 1992 |
tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
| 1993 |
tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
| 1994 |
tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
| 1995 |
tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
| 1996 |
tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
| 1997 |
tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
| 1998 |
tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
| 1999 |
tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
| 2000 |
} |
| 2001 |
|
| 2002 |
void r4k_helper_tlbwi(CPUMIPSState *env)
|
| 2003 |
{
|
| 2004 |
int idx;
|
| 2005 |
|
| 2006 |
idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
|
| 2007 |
|
| 2008 |
/* Discard cached TLB entries. We could avoid doing this if the
|
| 2009 |
tlbwi is just upgrading access permissions on the current entry;
|
| 2010 |
that might be a further win. */
|
| 2011 |
r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); |
| 2012 |
|
| 2013 |
r4k_invalidate_tlb(env, idx, 0);
|
| 2014 |
r4k_fill_tlb(env, idx); |
| 2015 |
} |
| 2016 |
|
| 2017 |
void r4k_helper_tlbwr(CPUMIPSState *env)
|
| 2018 |
{
|
| 2019 |
int r = cpu_mips_get_random(env);
|
| 2020 |
|
| 2021 |
r4k_invalidate_tlb(env, r, 1);
|
| 2022 |
r4k_fill_tlb(env, r); |
| 2023 |
} |
| 2024 |
|
| 2025 |
void r4k_helper_tlbp(CPUMIPSState *env)
|
| 2026 |
{
|
| 2027 |
r4k_tlb_t *tlb; |
| 2028 |
target_ulong mask; |
| 2029 |
target_ulong tag; |
| 2030 |
target_ulong VPN; |
| 2031 |
uint8_t ASID; |
| 2032 |
int i;
|
| 2033 |
|
| 2034 |
ASID = env->CP0_EntryHi & 0xFF;
|
| 2035 |
for (i = 0; i < env->tlb->nb_tlb; i++) { |
| 2036 |
tlb = &env->tlb->mmu.r4k.tlb[i]; |
| 2037 |
/* 1k pages are not supported. */
|
| 2038 |
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
| 2039 |
tag = env->CP0_EntryHi & ~mask; |
| 2040 |
VPN = tlb->VPN & ~mask; |
| 2041 |
/* Check ASID, virtual page number & size */
|
| 2042 |
if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
| 2043 |
/* TLB match */
|
| 2044 |
env->CP0_Index = i; |
| 2045 |
break;
|
| 2046 |
} |
| 2047 |
} |
| 2048 |
if (i == env->tlb->nb_tlb) {
|
| 2049 |
/* No match. Discard any shadow entries, if any of them match. */
|
| 2050 |
for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
|
| 2051 |
tlb = &env->tlb->mmu.r4k.tlb[i]; |
| 2052 |
/* 1k pages are not supported. */
|
| 2053 |
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
| 2054 |
tag = env->CP0_EntryHi & ~mask; |
| 2055 |
VPN = tlb->VPN & ~mask; |
| 2056 |
/* Check ASID, virtual page number & size */
|
| 2057 |
if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
| 2058 |
r4k_mips_tlb_flush_extra (env, i); |
| 2059 |
break;
|
| 2060 |
} |
| 2061 |
} |
| 2062 |
|
| 2063 |
env->CP0_Index |= 0x80000000;
|
| 2064 |
} |
| 2065 |
} |
| 2066 |
|
| 2067 |
void r4k_helper_tlbr(CPUMIPSState *env)
|
| 2068 |
{
|
| 2069 |
r4k_tlb_t *tlb; |
| 2070 |
uint8_t ASID; |
| 2071 |
int idx;
|
| 2072 |
|
| 2073 |
ASID = env->CP0_EntryHi & 0xFF;
|
| 2074 |
idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
|
| 2075 |
tlb = &env->tlb->mmu.r4k.tlb[idx]; |
| 2076 |
|
| 2077 |
/* If this will change the current ASID, flush qemu's TLB. */
|
| 2078 |
if (ASID != tlb->ASID)
|
| 2079 |
cpu_mips_tlb_flush (env, 1);
|
| 2080 |
|
| 2081 |
r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
| 2082 |
|
| 2083 |
env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
| 2084 |
env->CP0_PageMask = tlb->PageMask; |
| 2085 |
env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
| 2086 |
(tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
| 2087 |
env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
| 2088 |
(tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
| 2089 |
} |
| 2090 |
|
| 2091 |
void helper_tlbwi(CPUMIPSState *env)
|
| 2092 |
{
|
| 2093 |
env->tlb->helper_tlbwi(env); |
| 2094 |
} |
| 2095 |
|
| 2096 |
void helper_tlbwr(CPUMIPSState *env)
|
| 2097 |
{
|
| 2098 |
env->tlb->helper_tlbwr(env); |
| 2099 |
} |
| 2100 |
|
| 2101 |
void helper_tlbp(CPUMIPSState *env)
|
| 2102 |
{
|
| 2103 |
env->tlb->helper_tlbp(env); |
| 2104 |
} |
| 2105 |
|
| 2106 |
void helper_tlbr(CPUMIPSState *env)
|
| 2107 |
{
|
| 2108 |
env->tlb->helper_tlbr(env); |
| 2109 |
} |
| 2110 |
|
| 2111 |
/* Specials */
|
| 2112 |
target_ulong helper_di(CPUMIPSState *env) |
| 2113 |
{
|
| 2114 |
target_ulong t0 = env->CP0_Status; |
| 2115 |
|
| 2116 |
env->CP0_Status = t0 & ~(1 << CP0St_IE);
|
| 2117 |
return t0;
|
| 2118 |
} |
| 2119 |
|
| 2120 |
target_ulong helper_ei(CPUMIPSState *env) |
| 2121 |
{
|
| 2122 |
target_ulong t0 = env->CP0_Status; |
| 2123 |
|
| 2124 |
env->CP0_Status = t0 | (1 << CP0St_IE);
|
| 2125 |
return t0;
|
| 2126 |
} |
| 2127 |
|
| 2128 |
static void debug_pre_eret(CPUMIPSState *env) |
| 2129 |
{
|
| 2130 |
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
| 2131 |
qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
| 2132 |
env->active_tc.PC, env->CP0_EPC); |
| 2133 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
| 2134 |
qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
| 2135 |
if (env->hflags & MIPS_HFLAG_DM)
|
| 2136 |
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
| 2137 |
qemu_log("\n");
|
| 2138 |
} |
| 2139 |
} |
| 2140 |
|
| 2141 |
static void debug_post_eret(CPUMIPSState *env) |
| 2142 |
{
|
| 2143 |
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
| 2144 |
qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
| 2145 |
env->active_tc.PC, env->CP0_EPC); |
| 2146 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
| 2147 |
qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
| 2148 |
if (env->hflags & MIPS_HFLAG_DM)
|
| 2149 |
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
| 2150 |
switch (env->hflags & MIPS_HFLAG_KSU) {
|
| 2151 |
case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; |
| 2152 |
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; |
| 2153 |
case MIPS_HFLAG_KM: qemu_log("\n"); break; |
| 2154 |
default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
| 2155 |
} |
| 2156 |
} |
| 2157 |
} |
| 2158 |
|
| 2159 |
static void set_pc(CPUMIPSState *env, target_ulong error_pc) |
| 2160 |
{
|
| 2161 |
env->active_tc.PC = error_pc & ~(target_ulong)1;
|
| 2162 |
if (error_pc & 1) { |
| 2163 |
env->hflags |= MIPS_HFLAG_M16; |
| 2164 |
} else {
|
| 2165 |
env->hflags &= ~(MIPS_HFLAG_M16); |
| 2166 |
} |
| 2167 |
} |
| 2168 |
|
| 2169 |
void helper_eret(CPUMIPSState *env)
|
| 2170 |
{
|
| 2171 |
debug_pre_eret(env); |
| 2172 |
if (env->CP0_Status & (1 << CP0St_ERL)) { |
| 2173 |
set_pc(env, env->CP0_ErrorEPC); |
| 2174 |
env->CP0_Status &= ~(1 << CP0St_ERL);
|
| 2175 |
} else {
|
| 2176 |
set_pc(env, env->CP0_EPC); |
| 2177 |
env->CP0_Status &= ~(1 << CP0St_EXL);
|
| 2178 |
} |
| 2179 |
compute_hflags(env); |
| 2180 |
debug_post_eret(env); |
| 2181 |
env->lladdr = 1;
|
| 2182 |
} |
| 2183 |
|
| 2184 |
void helper_deret(CPUMIPSState *env)
|
| 2185 |
{
|
| 2186 |
debug_pre_eret(env); |
| 2187 |
set_pc(env, env->CP0_DEPC); |
| 2188 |
|
| 2189 |
env->hflags &= MIPS_HFLAG_DM; |
| 2190 |
compute_hflags(env); |
| 2191 |
debug_post_eret(env); |
| 2192 |
env->lladdr = 1;
|
| 2193 |
} |
| 2194 |
#endif /* !CONFIG_USER_ONLY */ |
| 2195 |
|
| 2196 |
target_ulong helper_rdhwr_cpunum(CPUMIPSState *env) |
| 2197 |
{
|
| 2198 |
if ((env->hflags & MIPS_HFLAG_CP0) ||
|
| 2199 |
(env->CP0_HWREna & (1 << 0))) |
| 2200 |
return env->CP0_EBase & 0x3ff; |
| 2201 |
else
|
| 2202 |
helper_raise_exception(env, EXCP_RI); |
| 2203 |
|
| 2204 |
return 0; |
| 2205 |
} |
| 2206 |
|
| 2207 |
target_ulong helper_rdhwr_synci_step(CPUMIPSState *env) |
| 2208 |
{
|
| 2209 |
if ((env->hflags & MIPS_HFLAG_CP0) ||
|
| 2210 |
(env->CP0_HWREna & (1 << 1))) |
| 2211 |
return env->SYNCI_Step;
|
| 2212 |
else
|
| 2213 |
helper_raise_exception(env, EXCP_RI); |
| 2214 |
|
| 2215 |
return 0; |
| 2216 |
} |
| 2217 |
|
| 2218 |
target_ulong helper_rdhwr_cc(CPUMIPSState *env) |
| 2219 |
{
|
| 2220 |
if ((env->hflags & MIPS_HFLAG_CP0) ||
|
| 2221 |
(env->CP0_HWREna & (1 << 2))) |
| 2222 |
return env->CP0_Count;
|
| 2223 |
else
|
| 2224 |
helper_raise_exception(env, EXCP_RI); |
| 2225 |
|
| 2226 |
return 0; |
| 2227 |
} |
| 2228 |
|
| 2229 |
target_ulong helper_rdhwr_ccres(CPUMIPSState *env) |
| 2230 |
{
|
| 2231 |
if ((env->hflags & MIPS_HFLAG_CP0) ||
|
| 2232 |
(env->CP0_HWREna & (1 << 3))) |
| 2233 |
return env->CCRes;
|
| 2234 |
else
|
| 2235 |
helper_raise_exception(env, EXCP_RI); |
| 2236 |
|
| 2237 |
return 0; |
| 2238 |
} |
| 2239 |
|
| 2240 |
void helper_pmon(CPUMIPSState *env, int function) |
| 2241 |
{
|
| 2242 |
function /= 2;
|
| 2243 |
switch (function) {
|
| 2244 |
case 2: /* TODO: char inbyte(int waitflag); */ |
| 2245 |
if (env->active_tc.gpr[4] == 0) |
| 2246 |
env->active_tc.gpr[2] = -1; |
| 2247 |
/* Fall through */
|
| 2248 |
case 11: /* TODO: char inbyte (void); */ |
| 2249 |
env->active_tc.gpr[2] = -1; |
| 2250 |
break;
|
| 2251 |
case 3: |
| 2252 |
case 12: |
| 2253 |
printf("%c", (char)(env->active_tc.gpr[4] & 0xFF)); |
| 2254 |
break;
|
| 2255 |
case 17: |
| 2256 |
break;
|
| 2257 |
case 158: |
| 2258 |
{
|
| 2259 |
unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4]; |
| 2260 |
printf("%s", fmt);
|
| 2261 |
} |
| 2262 |
break;
|
| 2263 |
} |
| 2264 |
} |
| 2265 |
|
| 2266 |
void helper_wait(CPUMIPSState *env)
|
| 2267 |
{
|
| 2268 |
env->halted = 1;
|
| 2269 |
cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE); |
| 2270 |
helper_raise_exception(env, EXCP_HLT); |
| 2271 |
} |
| 2272 |
|
| 2273 |
#if !defined(CONFIG_USER_ONLY)
|
| 2274 |
|
| 2275 |
static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env, |
| 2276 |
target_ulong addr, int is_write,
|
| 2277 |
int is_user, uintptr_t retaddr);
|
| 2278 |
|
| 2279 |
#define MMUSUFFIX _mmu
|
| 2280 |
#define ALIGNED_ONLY
|
| 2281 |
|
| 2282 |
#define SHIFT 0 |
| 2283 |
#include "softmmu_template.h" |
| 2284 |
|
| 2285 |
#define SHIFT 1 |
| 2286 |
#include "softmmu_template.h" |
| 2287 |
|
| 2288 |
#define SHIFT 2 |
| 2289 |
#include "softmmu_template.h" |
| 2290 |
|
| 2291 |
#define SHIFT 3 |
| 2292 |
#include "softmmu_template.h" |
| 2293 |
|
| 2294 |
static void do_unaligned_access(CPUMIPSState *env, target_ulong addr, |
| 2295 |
int is_write, int is_user, uintptr_t retaddr) |
| 2296 |
{
|
| 2297 |
env->CP0_BadVAddr = addr; |
| 2298 |
do_restore_state(env, retaddr); |
| 2299 |
helper_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
| 2300 |
} |
| 2301 |
|
| 2302 |
void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx, |
| 2303 |
uintptr_t retaddr) |
| 2304 |
{
|
| 2305 |
TranslationBlock *tb; |
| 2306 |
int ret;
|
| 2307 |
|
| 2308 |
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx); |
| 2309 |
if (ret) {
|
| 2310 |
if (retaddr) {
|
| 2311 |
/* now we have a real cpu fault */
|
| 2312 |
tb = tb_find_pc(retaddr); |
| 2313 |
if (tb) {
|
| 2314 |
/* the PC is inside the translated code. It means that we have
|
| 2315 |
a virtual CPU fault */
|
| 2316 |
cpu_restore_state(tb, env, retaddr); |
| 2317 |
} |
| 2318 |
} |
| 2319 |
helper_raise_exception_err(env, env->exception_index, env->error_code); |
| 2320 |
} |
| 2321 |
} |
| 2322 |
|
| 2323 |
void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
|
| 2324 |
int is_write, int is_exec, int unused, int size) |
| 2325 |
{
|
| 2326 |
if (is_exec)
|
| 2327 |
helper_raise_exception(env, EXCP_IBE); |
| 2328 |
else
|
| 2329 |
helper_raise_exception(env, EXCP_DBE); |
| 2330 |
} |
| 2331 |
#endif /* !CONFIG_USER_ONLY */ |
| 2332 |
|
| 2333 |
/* Complex FPU operations which may need stack space. */
|
| 2334 |
|
| 2335 |
#define FLOAT_ONE32 make_float32(0x3f8 << 20) |
| 2336 |
#define FLOAT_ONE64 make_float64(0x3ffULL << 52) |
| 2337 |
#define FLOAT_TWO32 make_float32(1 << 30) |
| 2338 |
#define FLOAT_TWO64 make_float64(1ULL << 62) |
| 2339 |
#define FLOAT_QNAN32 0x7fbfffff |
| 2340 |
#define FLOAT_QNAN64 0x7ff7ffffffffffffULL |
| 2341 |
#define FLOAT_SNAN32 0x7fffffff |
| 2342 |
#define FLOAT_SNAN64 0x7fffffffffffffffULL |
| 2343 |
|
| 2344 |
/* convert MIPS rounding mode in FCR31 to IEEE library */
|
| 2345 |
static unsigned int ieee_rm[] = { |
| 2346 |
float_round_nearest_even, |
| 2347 |
float_round_to_zero, |
| 2348 |
float_round_up, |
| 2349 |
float_round_down |
| 2350 |
}; |
| 2351 |
|
| 2352 |
#define RESTORE_ROUNDING_MODE \
|
| 2353 |
set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
|
| 2354 |
|
| 2355 |
#define RESTORE_FLUSH_MODE \
|
| 2356 |
set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status); |
| 2357 |
|
| 2358 |
target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) |
| 2359 |
{
|
| 2360 |
target_ulong arg1; |
| 2361 |
|
| 2362 |
switch (reg) {
|
| 2363 |
case 0: |
| 2364 |
arg1 = (int32_t)env->active_fpu.fcr0; |
| 2365 |
break;
|
| 2366 |
case 25: |
| 2367 |
arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1); |
| 2368 |
break;
|
| 2369 |
case 26: |
| 2370 |
arg1 = env->active_fpu.fcr31 & 0x0003f07c;
|
| 2371 |
break;
|
| 2372 |
case 28: |
| 2373 |
arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4); |
| 2374 |
break;
|
| 2375 |
default:
|
| 2376 |
arg1 = (int32_t)env->active_fpu.fcr31; |
| 2377 |
break;
|
| 2378 |
} |
| 2379 |
|
| 2380 |
return arg1;
|
| 2381 |
} |
| 2382 |
|
| 2383 |
void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
|
| 2384 |
{
|
| 2385 |
switch(reg) {
|
| 2386 |
case 25: |
| 2387 |
if (arg1 & 0xffffff00) |
| 2388 |
return;
|
| 2389 |
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) | |
| 2390 |
((arg1 & 0x1) << 23); |
| 2391 |
break;
|
| 2392 |
case 26: |
| 2393 |
if (arg1 & 0x007c0000) |
| 2394 |
return;
|
| 2395 |
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c); |
| 2396 |
break;
|
| 2397 |
case 28: |
| 2398 |
if (arg1 & 0x007c0000) |
| 2399 |
return;
|
| 2400 |
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) | |
| 2401 |
((arg1 & 0x4) << 22); |
| 2402 |
break;
|
| 2403 |
case 31: |
| 2404 |
if (arg1 & 0x007c0000) |
| 2405 |
return;
|
| 2406 |
env->active_fpu.fcr31 = arg1; |
| 2407 |
break;
|
| 2408 |
default:
|
| 2409 |
return;
|
| 2410 |
} |
| 2411 |
/* set rounding mode */
|
| 2412 |
RESTORE_ROUNDING_MODE; |
| 2413 |
/* set flush-to-zero mode */
|
| 2414 |
RESTORE_FLUSH_MODE; |
| 2415 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2416 |
if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) |
| 2417 |
helper_raise_exception(env, EXCP_FPE); |
| 2418 |
} |
| 2419 |
|
| 2420 |
static inline int ieee_ex_to_mips(int xcpt) |
| 2421 |
{
|
| 2422 |
int ret = 0; |
| 2423 |
if (xcpt) {
|
| 2424 |
if (xcpt & float_flag_invalid) {
|
| 2425 |
ret |= FP_INVALID; |
| 2426 |
} |
| 2427 |
if (xcpt & float_flag_overflow) {
|
| 2428 |
ret |= FP_OVERFLOW; |
| 2429 |
} |
| 2430 |
if (xcpt & float_flag_underflow) {
|
| 2431 |
ret |= FP_UNDERFLOW; |
| 2432 |
} |
| 2433 |
if (xcpt & float_flag_divbyzero) {
|
| 2434 |
ret |= FP_DIV0; |
| 2435 |
} |
| 2436 |
if (xcpt & float_flag_inexact) {
|
| 2437 |
ret |= FP_INEXACT; |
| 2438 |
} |
| 2439 |
} |
| 2440 |
return ret;
|
| 2441 |
} |
| 2442 |
|
| 2443 |
static inline void update_fcr31(CPUMIPSState *env) |
| 2444 |
{
|
| 2445 |
int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
|
| 2446 |
|
| 2447 |
SET_FP_CAUSE(env->active_fpu.fcr31, tmp); |
| 2448 |
if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
|
| 2449 |
helper_raise_exception(env, EXCP_FPE); |
| 2450 |
else
|
| 2451 |
UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); |
| 2452 |
} |
| 2453 |
|
| 2454 |
/* Float support.
|
| 2455 |
Single precition routines have a "s" suffix, double precision a
|
| 2456 |
"d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
|
| 2457 |
paired single lower "pl", paired single upper "pu". */
|
| 2458 |
|
| 2459 |
/* unary operations, modifying fp status */
|
| 2460 |
uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) |
| 2461 |
{
|
| 2462 |
return float64_sqrt(fdt0, &env->active_fpu.fp_status);
|
| 2463 |
} |
| 2464 |
|
| 2465 |
uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0) |
| 2466 |
{
|
| 2467 |
return float32_sqrt(fst0, &env->active_fpu.fp_status);
|
| 2468 |
} |
| 2469 |
|
| 2470 |
uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) |
| 2471 |
{
|
| 2472 |
uint64_t fdt2; |
| 2473 |
|
| 2474 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2475 |
fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); |
| 2476 |
update_fcr31(env); |
| 2477 |
return fdt2;
|
| 2478 |
} |
| 2479 |
|
| 2480 |
uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0) |
| 2481 |
{
|
| 2482 |
uint64_t fdt2; |
| 2483 |
|
| 2484 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2485 |
fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); |
| 2486 |
update_fcr31(env); |
| 2487 |
return fdt2;
|
| 2488 |
} |
| 2489 |
|
| 2490 |
uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0) |
| 2491 |
{
|
| 2492 |
uint64_t fdt2; |
| 2493 |
|
| 2494 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2495 |
fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); |
| 2496 |
update_fcr31(env); |
| 2497 |
return fdt2;
|
| 2498 |
} |
| 2499 |
|
| 2500 |
uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0) |
| 2501 |
{
|
| 2502 |
uint64_t dt2; |
| 2503 |
|
| 2504 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2505 |
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
| 2506 |
update_fcr31(env); |
| 2507 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2508 |
dt2 = FLOAT_SNAN64; |
| 2509 |
return dt2;
|
| 2510 |
} |
| 2511 |
|
| 2512 |
uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0) |
| 2513 |
{
|
| 2514 |
uint64_t dt2; |
| 2515 |
|
| 2516 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2517 |
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
| 2518 |
update_fcr31(env); |
| 2519 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2520 |
dt2 = FLOAT_SNAN64; |
| 2521 |
return dt2;
|
| 2522 |
} |
| 2523 |
|
| 2524 |
uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0) |
| 2525 |
{
|
| 2526 |
uint32_t fst2; |
| 2527 |
uint32_t fsth2; |
| 2528 |
|
| 2529 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2530 |
fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
|
| 2531 |
fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
|
| 2532 |
update_fcr31(env); |
| 2533 |
return ((uint64_t)fsth2 << 32) | fst2; |
| 2534 |
} |
| 2535 |
|
| 2536 |
uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) |
| 2537 |
{
|
| 2538 |
uint32_t wt2; |
| 2539 |
uint32_t wth2; |
| 2540 |
|
| 2541 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2542 |
wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
|
| 2543 |
wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
|
| 2544 |
update_fcr31(env); |
| 2545 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
|
| 2546 |
wt2 = FLOAT_SNAN32; |
| 2547 |
wth2 = FLOAT_SNAN32; |
| 2548 |
} |
| 2549 |
return ((uint64_t)wth2 << 32) | wt2; |
| 2550 |
} |
| 2551 |
|
| 2552 |
uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) |
| 2553 |
{
|
| 2554 |
uint32_t fst2; |
| 2555 |
|
| 2556 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2557 |
fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); |
| 2558 |
update_fcr31(env); |
| 2559 |
return fst2;
|
| 2560 |
} |
| 2561 |
|
| 2562 |
uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0) |
| 2563 |
{
|
| 2564 |
uint32_t fst2; |
| 2565 |
|
| 2566 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2567 |
fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); |
| 2568 |
update_fcr31(env); |
| 2569 |
return fst2;
|
| 2570 |
} |
| 2571 |
|
| 2572 |
uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0) |
| 2573 |
{
|
| 2574 |
uint32_t fst2; |
| 2575 |
|
| 2576 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2577 |
fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); |
| 2578 |
update_fcr31(env); |
| 2579 |
return fst2;
|
| 2580 |
} |
| 2581 |
|
| 2582 |
uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0) |
| 2583 |
{
|
| 2584 |
uint32_t wt2; |
| 2585 |
|
| 2586 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2587 |
wt2 = wt0; |
| 2588 |
update_fcr31(env); |
| 2589 |
return wt2;
|
| 2590 |
} |
| 2591 |
|
| 2592 |
uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0) |
| 2593 |
{
|
| 2594 |
uint32_t wt2; |
| 2595 |
|
| 2596 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2597 |
wt2 = wth0; |
| 2598 |
update_fcr31(env); |
| 2599 |
return wt2;
|
| 2600 |
} |
| 2601 |
|
| 2602 |
uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0) |
| 2603 |
{
|
| 2604 |
uint32_t wt2; |
| 2605 |
|
| 2606 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2607 |
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
| 2608 |
update_fcr31(env); |
| 2609 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2610 |
wt2 = FLOAT_SNAN32; |
| 2611 |
return wt2;
|
| 2612 |
} |
| 2613 |
|
| 2614 |
uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0) |
| 2615 |
{
|
| 2616 |
uint32_t wt2; |
| 2617 |
|
| 2618 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2619 |
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
| 2620 |
update_fcr31(env); |
| 2621 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2622 |
wt2 = FLOAT_SNAN32; |
| 2623 |
return wt2;
|
| 2624 |
} |
| 2625 |
|
| 2626 |
uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0) |
| 2627 |
{
|
| 2628 |
uint64_t dt2; |
| 2629 |
|
| 2630 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2631 |
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
| 2632 |
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
| 2633 |
RESTORE_ROUNDING_MODE; |
| 2634 |
update_fcr31(env); |
| 2635 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2636 |
dt2 = FLOAT_SNAN64; |
| 2637 |
return dt2;
|
| 2638 |
} |
| 2639 |
|
| 2640 |
uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0) |
| 2641 |
{
|
| 2642 |
uint64_t dt2; |
| 2643 |
|
| 2644 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2645 |
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
| 2646 |
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
| 2647 |
RESTORE_ROUNDING_MODE; |
| 2648 |
update_fcr31(env); |
| 2649 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2650 |
dt2 = FLOAT_SNAN64; |
| 2651 |
return dt2;
|
| 2652 |
} |
| 2653 |
|
| 2654 |
uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0) |
| 2655 |
{
|
| 2656 |
uint32_t wt2; |
| 2657 |
|
| 2658 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2659 |
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
| 2660 |
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
| 2661 |
RESTORE_ROUNDING_MODE; |
| 2662 |
update_fcr31(env); |
| 2663 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2664 |
wt2 = FLOAT_SNAN32; |
| 2665 |
return wt2;
|
| 2666 |
} |
| 2667 |
|
| 2668 |
uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0) |
| 2669 |
{
|
| 2670 |
uint32_t wt2; |
| 2671 |
|
| 2672 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2673 |
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
| 2674 |
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
| 2675 |
RESTORE_ROUNDING_MODE; |
| 2676 |
update_fcr31(env); |
| 2677 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2678 |
wt2 = FLOAT_SNAN32; |
| 2679 |
return wt2;
|
| 2680 |
} |
| 2681 |
|
| 2682 |
uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0) |
| 2683 |
{
|
| 2684 |
uint64_t dt2; |
| 2685 |
|
| 2686 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2687 |
dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); |
| 2688 |
update_fcr31(env); |
| 2689 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2690 |
dt2 = FLOAT_SNAN64; |
| 2691 |
return dt2;
|
| 2692 |
} |
| 2693 |
|
| 2694 |
uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0) |
| 2695 |
{
|
| 2696 |
uint64_t dt2; |
| 2697 |
|
| 2698 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2699 |
dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); |
| 2700 |
update_fcr31(env); |
| 2701 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2702 |
dt2 = FLOAT_SNAN64; |
| 2703 |
return dt2;
|
| 2704 |
} |
| 2705 |
|
| 2706 |
uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0) |
| 2707 |
{
|
| 2708 |
uint32_t wt2; |
| 2709 |
|
| 2710 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2711 |
wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); |
| 2712 |
update_fcr31(env); |
| 2713 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2714 |
wt2 = FLOAT_SNAN32; |
| 2715 |
return wt2;
|
| 2716 |
} |
| 2717 |
|
| 2718 |
uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0) |
| 2719 |
{
|
| 2720 |
uint32_t wt2; |
| 2721 |
|
| 2722 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2723 |
wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); |
| 2724 |
update_fcr31(env); |
| 2725 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2726 |
wt2 = FLOAT_SNAN32; |
| 2727 |
return wt2;
|
| 2728 |
} |
| 2729 |
|
| 2730 |
uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0) |
| 2731 |
{
|
| 2732 |
uint64_t dt2; |
| 2733 |
|
| 2734 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2735 |
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
| 2736 |
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
| 2737 |
RESTORE_ROUNDING_MODE; |
| 2738 |
update_fcr31(env); |
| 2739 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2740 |
dt2 = FLOAT_SNAN64; |
| 2741 |
return dt2;
|
| 2742 |
} |
| 2743 |
|
| 2744 |
uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0) |
| 2745 |
{
|
| 2746 |
uint64_t dt2; |
| 2747 |
|
| 2748 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2749 |
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
| 2750 |
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
| 2751 |
RESTORE_ROUNDING_MODE; |
| 2752 |
update_fcr31(env); |
| 2753 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2754 |
dt2 = FLOAT_SNAN64; |
| 2755 |
return dt2;
|
| 2756 |
} |
| 2757 |
|
| 2758 |
uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0) |
| 2759 |
{
|
| 2760 |
uint32_t wt2; |
| 2761 |
|
| 2762 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2763 |
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
| 2764 |
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
| 2765 |
RESTORE_ROUNDING_MODE; |
| 2766 |
update_fcr31(env); |
| 2767 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2768 |
wt2 = FLOAT_SNAN32; |
| 2769 |
return wt2;
|
| 2770 |
} |
| 2771 |
|
| 2772 |
uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0) |
| 2773 |
{
|
| 2774 |
uint32_t wt2; |
| 2775 |
|
| 2776 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2777 |
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
| 2778 |
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
| 2779 |
RESTORE_ROUNDING_MODE; |
| 2780 |
update_fcr31(env); |
| 2781 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2782 |
wt2 = FLOAT_SNAN32; |
| 2783 |
return wt2;
|
| 2784 |
} |
| 2785 |
|
| 2786 |
uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0) |
| 2787 |
{
|
| 2788 |
uint64_t dt2; |
| 2789 |
|
| 2790 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2791 |
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
| 2792 |
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
| 2793 |
RESTORE_ROUNDING_MODE; |
| 2794 |
update_fcr31(env); |
| 2795 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2796 |
dt2 = FLOAT_SNAN64; |
| 2797 |
return dt2;
|
| 2798 |
} |
| 2799 |
|
| 2800 |
uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0) |
| 2801 |
{
|
| 2802 |
uint64_t dt2; |
| 2803 |
|
| 2804 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2805 |
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
| 2806 |
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
| 2807 |
RESTORE_ROUNDING_MODE; |
| 2808 |
update_fcr31(env); |
| 2809 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2810 |
dt2 = FLOAT_SNAN64; |
| 2811 |
return dt2;
|
| 2812 |
} |
| 2813 |
|
| 2814 |
uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0) |
| 2815 |
{
|
| 2816 |
uint32_t wt2; |
| 2817 |
|
| 2818 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2819 |
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
| 2820 |
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
| 2821 |
RESTORE_ROUNDING_MODE; |
| 2822 |
update_fcr31(env); |
| 2823 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2824 |
wt2 = FLOAT_SNAN32; |
| 2825 |
return wt2;
|
| 2826 |
} |
| 2827 |
|
| 2828 |
uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0) |
| 2829 |
{
|
| 2830 |
uint32_t wt2; |
| 2831 |
|
| 2832 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2833 |
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
| 2834 |
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
| 2835 |
RESTORE_ROUNDING_MODE; |
| 2836 |
update_fcr31(env); |
| 2837 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
| 2838 |
wt2 = FLOAT_SNAN32; |
| 2839 |
return wt2;
|
| 2840 |
} |
| 2841 |
|
| 2842 |
/* unary operations, not modifying fp status */
|
| 2843 |
#define FLOAT_UNOP(name) \
|
| 2844 |
uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \ |
| 2845 |
{ \
|
| 2846 |
return float64_ ## name(fdt0); \ |
| 2847 |
} \ |
| 2848 |
uint32_t helper_float_ ## name ## _s(uint32_t fst0) \ |
| 2849 |
{ \
|
| 2850 |
return float32_ ## name(fst0); \ |
| 2851 |
} \ |
| 2852 |
uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \ |
| 2853 |
{ \
|
| 2854 |
uint32_t wt0; \ |
| 2855 |
uint32_t wth0; \ |
| 2856 |
\ |
| 2857 |
wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \ |
| 2858 |
wth0 = float32_ ## name(fdt0 >> 32); \ |
| 2859 |
return ((uint64_t)wth0 << 32) | wt0; \ |
| 2860 |
} |
| 2861 |
FLOAT_UNOP(abs) |
| 2862 |
FLOAT_UNOP(chs) |
| 2863 |
#undef FLOAT_UNOP
|
| 2864 |
|
| 2865 |
/* MIPS specific unary operations */
|
| 2866 |
uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) |
| 2867 |
{
|
| 2868 |
uint64_t fdt2; |
| 2869 |
|
| 2870 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2871 |
fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); |
| 2872 |
update_fcr31(env); |
| 2873 |
return fdt2;
|
| 2874 |
} |
| 2875 |
|
| 2876 |
uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0) |
| 2877 |
{
|
| 2878 |
uint32_t fst2; |
| 2879 |
|
| 2880 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2881 |
fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); |
| 2882 |
update_fcr31(env); |
| 2883 |
return fst2;
|
| 2884 |
} |
| 2885 |
|
| 2886 |
uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0) |
| 2887 |
{
|
| 2888 |
uint64_t fdt2; |
| 2889 |
|
| 2890 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2891 |
fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
| 2892 |
fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); |
| 2893 |
update_fcr31(env); |
| 2894 |
return fdt2;
|
| 2895 |
} |
| 2896 |
|
| 2897 |
uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0) |
| 2898 |
{
|
| 2899 |
uint32_t fst2; |
| 2900 |
|
| 2901 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2902 |
fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
| 2903 |
fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); |
| 2904 |
update_fcr31(env); |
| 2905 |
return fst2;
|
| 2906 |
} |
| 2907 |
|
| 2908 |
uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0) |
| 2909 |
{
|
| 2910 |
uint64_t fdt2; |
| 2911 |
|
| 2912 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2913 |
fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); |
| 2914 |
update_fcr31(env); |
| 2915 |
return fdt2;
|
| 2916 |
} |
| 2917 |
|
| 2918 |
uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) |
| 2919 |
{
|
| 2920 |
uint32_t fst2; |
| 2921 |
|
| 2922 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2923 |
fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); |
| 2924 |
update_fcr31(env); |
| 2925 |
return fst2;
|
| 2926 |
} |
| 2927 |
|
| 2928 |
uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) |
| 2929 |
{
|
| 2930 |
uint32_t fst2; |
| 2931 |
uint32_t fsth2; |
| 2932 |
|
| 2933 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2934 |
fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
|
| 2935 |
fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
|
| 2936 |
update_fcr31(env); |
| 2937 |
return ((uint64_t)fsth2 << 32) | fst2; |
| 2938 |
} |
| 2939 |
|
| 2940 |
uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) |
| 2941 |
{
|
| 2942 |
uint64_t fdt2; |
| 2943 |
|
| 2944 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2945 |
fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
| 2946 |
fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); |
| 2947 |
update_fcr31(env); |
| 2948 |
return fdt2;
|
| 2949 |
} |
| 2950 |
|
| 2951 |
uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) |
| 2952 |
{
|
| 2953 |
uint32_t fst2; |
| 2954 |
|
| 2955 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2956 |
fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
| 2957 |
fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); |
| 2958 |
update_fcr31(env); |
| 2959 |
return fst2;
|
| 2960 |
} |
| 2961 |
|
| 2962 |
uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) |
| 2963 |
{
|
| 2964 |
uint32_t fst2; |
| 2965 |
uint32_t fsth2; |
| 2966 |
|
| 2967 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 2968 |
fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
|
| 2969 |
fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
|
| 2970 |
fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); |
| 2971 |
fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status); |
| 2972 |
update_fcr31(env); |
| 2973 |
return ((uint64_t)fsth2 << 32) | fst2; |
| 2974 |
} |
| 2975 |
|
| 2976 |
#define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env) |
| 2977 |
|
| 2978 |
/* binary operations */
|
| 2979 |
#define FLOAT_BINOP(name) \
|
| 2980 |
uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ |
| 2981 |
uint64_t fdt0, uint64_t fdt1) \ |
| 2982 |
{ \
|
| 2983 |
uint64_t dt2; \ |
| 2984 |
\ |
| 2985 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
| 2986 |
dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ |
| 2987 |
update_fcr31(env); \ |
| 2988 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
|
| 2989 |
dt2 = FLOAT_QNAN64; \ |
| 2990 |
return dt2; \
|
| 2991 |
} \ |
| 2992 |
\ |
| 2993 |
uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ |
| 2994 |
uint32_t fst0, uint32_t fst1) \ |
| 2995 |
{ \
|
| 2996 |
uint32_t wt2; \ |
| 2997 |
\ |
| 2998 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
| 2999 |
wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
| 3000 |
update_fcr31(env); \ |
| 3001 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
|
| 3002 |
wt2 = FLOAT_QNAN32; \ |
| 3003 |
return wt2; \
|
| 3004 |
} \ |
| 3005 |
\ |
| 3006 |
uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ |
| 3007 |
uint64_t fdt0, \ |
| 3008 |
uint64_t fdt1) \ |
| 3009 |
{ \
|
| 3010 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
|
| 3011 |
uint32_t fsth0 = fdt0 >> 32; \
|
| 3012 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
|
| 3013 |
uint32_t fsth1 = fdt1 >> 32; \
|
| 3014 |
uint32_t wt2; \ |
| 3015 |
uint32_t wth2; \ |
| 3016 |
\ |
| 3017 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
| 3018 |
wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
| 3019 |
wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ |
| 3020 |
update_fcr31(env); \ |
| 3021 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
|
| 3022 |
wt2 = FLOAT_QNAN32; \ |
| 3023 |
wth2 = FLOAT_QNAN32; \ |
| 3024 |
} \ |
| 3025 |
return ((uint64_t)wth2 << 32) | wt2; \ |
| 3026 |
} |
| 3027 |
|
| 3028 |
FLOAT_BINOP(add) |
| 3029 |
FLOAT_BINOP(sub) |
| 3030 |
FLOAT_BINOP(mul) |
| 3031 |
FLOAT_BINOP(div) |
| 3032 |
#undef FLOAT_BINOP
|
| 3033 |
|
| 3034 |
/* ternary operations */
|
| 3035 |
#define FLOAT_TERNOP(name1, name2) \
|
| 3036 |
uint64_t helper_float_ ## name1 ## name2 ## _d(CPUMIPSState *env, \ |
| 3037 |
uint64_t fdt0, \ |
| 3038 |
uint64_t fdt1, \ |
| 3039 |
uint64_t fdt2) \ |
| 3040 |
{ \
|
| 3041 |
fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ |
| 3042 |
return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ |
| 3043 |
} \ |
| 3044 |
\ |
| 3045 |
uint32_t helper_float_ ## name1 ## name2 ## _s(CPUMIPSState *env, \ |
| 3046 |
uint32_t fst0, \ |
| 3047 |
uint32_t fst1, \ |
| 3048 |
uint32_t fst2) \ |
| 3049 |
{ \
|
| 3050 |
fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
| 3051 |
return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ |
| 3052 |
} \ |
| 3053 |
\ |
| 3054 |
uint64_t helper_float_ ## name1 ## name2 ## _ps(CPUMIPSState *env, \ |
| 3055 |
uint64_t fdt0, \ |
| 3056 |
uint64_t fdt1, \ |
| 3057 |
uint64_t fdt2) \ |
| 3058 |
{ \
|
| 3059 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
|
| 3060 |
uint32_t fsth0 = fdt0 >> 32; \
|
| 3061 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
|
| 3062 |
uint32_t fsth1 = fdt1 >> 32; \
|
| 3063 |
uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
|
| 3064 |
uint32_t fsth2 = fdt2 >> 32; \
|
| 3065 |
\ |
| 3066 |
fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
| 3067 |
fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ |
| 3068 |
fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ |
| 3069 |
fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ |
| 3070 |
return ((uint64_t)fsth2 << 32) | fst2; \ |
| 3071 |
} |
| 3072 |
|
| 3073 |
FLOAT_TERNOP(mul, add) |
| 3074 |
FLOAT_TERNOP(mul, sub) |
| 3075 |
#undef FLOAT_TERNOP
|
| 3076 |
|
| 3077 |
/* negated ternary operations */
|
| 3078 |
#define FLOAT_NTERNOP(name1, name2) \
|
| 3079 |
uint64_t helper_float_n ## name1 ## name2 ## _d(CPUMIPSState *env, \ |
| 3080 |
uint64_t fdt0, \ |
| 3081 |
uint64_t fdt1, \ |
| 3082 |
uint64_t fdt2) \ |
| 3083 |
{ \
|
| 3084 |
fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ |
| 3085 |
fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ |
| 3086 |
return float64_chs(fdt2); \
|
| 3087 |
} \ |
| 3088 |
\ |
| 3089 |
uint32_t helper_float_n ## name1 ## name2 ## _s(CPUMIPSState *env, \ |
| 3090 |
uint32_t fst0, \ |
| 3091 |
uint32_t fst1, \ |
| 3092 |
uint32_t fst2) \ |
| 3093 |
{ \
|
| 3094 |
fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
| 3095 |
fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ |
| 3096 |
return float32_chs(fst2); \
|
| 3097 |
} \ |
| 3098 |
\ |
| 3099 |
uint64_t helper_float_n ## name1 ## name2 ## _ps(CPUMIPSState *env, \ |
| 3100 |
uint64_t fdt0, \ |
| 3101 |
uint64_t fdt1, \ |
| 3102 |
uint64_t fdt2) \ |
| 3103 |
{ \
|
| 3104 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
|
| 3105 |
uint32_t fsth0 = fdt0 >> 32; \
|
| 3106 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
|
| 3107 |
uint32_t fsth1 = fdt1 >> 32; \
|
| 3108 |
uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
|
| 3109 |
uint32_t fsth2 = fdt2 >> 32; \
|
| 3110 |
\ |
| 3111 |
fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
| 3112 |
fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ |
| 3113 |
fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ |
| 3114 |
fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ |
| 3115 |
fst2 = float32_chs(fst2); \ |
| 3116 |
fsth2 = float32_chs(fsth2); \ |
| 3117 |
return ((uint64_t)fsth2 << 32) | fst2; \ |
| 3118 |
} |
| 3119 |
|
| 3120 |
FLOAT_NTERNOP(mul, add) |
| 3121 |
FLOAT_NTERNOP(mul, sub) |
| 3122 |
#undef FLOAT_NTERNOP
|
| 3123 |
|
| 3124 |
/* MIPS specific binary operations */
|
| 3125 |
uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
| 3126 |
{
|
| 3127 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 3128 |
fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
| 3129 |
fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status)); |
| 3130 |
update_fcr31(env); |
| 3131 |
return fdt2;
|
| 3132 |
} |
| 3133 |
|
| 3134 |
uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) |
| 3135 |
{
|
| 3136 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 3137 |
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
| 3138 |
fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); |
| 3139 |
update_fcr31(env); |
| 3140 |
return fst2;
|
| 3141 |
} |
| 3142 |
|
| 3143 |
uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
| 3144 |
{
|
| 3145 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
|
| 3146 |
uint32_t fsth0 = fdt0 >> 32;
|
| 3147 |
uint32_t fst2 = fdt2 & 0XFFFFFFFF;
|
| 3148 |
uint32_t fsth2 = fdt2 >> 32;
|
| 3149 |
|
| 3150 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 3151 |
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
| 3152 |
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); |
| 3153 |
fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); |
| 3154 |
fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status)); |
| 3155 |
update_fcr31(env); |
| 3156 |
return ((uint64_t)fsth2 << 32) | fst2; |
| 3157 |
} |
| 3158 |
|
| 3159 |
uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
| 3160 |
{
|
| 3161 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 3162 |
fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
| 3163 |
fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status); |
| 3164 |
fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); |
| 3165 |
update_fcr31(env); |
| 3166 |
return fdt2;
|
| 3167 |
} |
| 3168 |
|
| 3169 |
uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) |
| 3170 |
{
|
| 3171 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 3172 |
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
| 3173 |
fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); |
| 3174 |
fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
| 3175 |
update_fcr31(env); |
| 3176 |
return fst2;
|
| 3177 |
} |
| 3178 |
|
| 3179 |
uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
| 3180 |
{
|
| 3181 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
|
| 3182 |
uint32_t fsth0 = fdt0 >> 32;
|
| 3183 |
uint32_t fst2 = fdt2 & 0XFFFFFFFF;
|
| 3184 |
uint32_t fsth2 = fdt2 >> 32;
|
| 3185 |
|
| 3186 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 3187 |
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
| 3188 |
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); |
| 3189 |
fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); |
| 3190 |
fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status); |
| 3191 |
fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
| 3192 |
fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
| 3193 |
update_fcr31(env); |
| 3194 |
return ((uint64_t)fsth2 << 32) | fst2; |
| 3195 |
} |
| 3196 |
|
| 3197 |
uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) |
| 3198 |
{
|
| 3199 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
|
| 3200 |
uint32_t fsth0 = fdt0 >> 32;
|
| 3201 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF;
|
| 3202 |
uint32_t fsth1 = fdt1 >> 32;
|
| 3203 |
uint32_t fst2; |
| 3204 |
uint32_t fsth2; |
| 3205 |
|
| 3206 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 3207 |
fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); |
| 3208 |
fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); |
| 3209 |
update_fcr31(env); |
| 3210 |
return ((uint64_t)fsth2 << 32) | fst2; |
| 3211 |
} |
| 3212 |
|
| 3213 |
uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) |
| 3214 |
{
|
| 3215 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
|
| 3216 |
uint32_t fsth0 = fdt0 >> 32;
|
| 3217 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF;
|
| 3218 |
uint32_t fsth1 = fdt1 >> 32;
|
| 3219 |
uint32_t fst2; |
| 3220 |
uint32_t fsth2; |
| 3221 |
|
| 3222 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
| 3223 |
fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); |
| 3224 |
fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); |
| 3225 |
update_fcr31(env); |
| 3226 |
return ((uint64_t)fsth2 << 32) | fst2; |
| 3227 |
} |
| 3228 |
|
| 3229 |
/* compare operations */
|
| 3230 |
#define FOP_COND_D(op, cond) \
|
| 3231 |
void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
| 3232 |
uint64_t fdt1, int cc) \
|
| 3233 |
{ \
|
| 3234 |
int c; \
|
| 3235 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
| 3236 |
c = cond; \ |
| 3237 |
update_fcr31(env); \ |
| 3238 |
if (c) \
|
| 3239 |
SET_FP_COND(cc, env->active_fpu); \ |
| 3240 |
else \
|
| 3241 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
| 3242 |
} \ |
| 3243 |
void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
| 3244 |
uint64_t fdt1, int cc) \
|
| 3245 |
{ \
|
| 3246 |
int c; \
|
| 3247 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
| 3248 |
fdt0 = float64_abs(fdt0); \ |
| 3249 |
fdt1 = float64_abs(fdt1); \ |
| 3250 |
c = cond; \ |
| 3251 |
update_fcr31(env); \ |
| 3252 |
if (c) \
|
| 3253 |
SET_FP_COND(cc, env->active_fpu); \ |
| 3254 |
else \
|
| 3255 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
| 3256 |
} |
| 3257 |
|
| 3258 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
| 3259 |
* but float64_unordered_quiet() is still called. */
|
| 3260 |
FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
|
| 3261 |
FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)) |
| 3262 |
FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3263 |
FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3264 |
FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3265 |
FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3266 |
FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3267 |
FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3268 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
| 3269 |
* but float64_unordered() is still called. */
|
| 3270 |
FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
|
| 3271 |
FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)) |
| 3272 |
FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3273 |
FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3274 |
FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3275 |
FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3276 |
FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3277 |
FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3278 |
|
| 3279 |
#define FOP_COND_S(op, cond) \
|
| 3280 |
void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ |
| 3281 |
uint32_t fst1, int cc) \
|
| 3282 |
{ \
|
| 3283 |
int c; \
|
| 3284 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
| 3285 |
c = cond; \ |
| 3286 |
update_fcr31(env); \ |
| 3287 |
if (c) \
|
| 3288 |
SET_FP_COND(cc, env->active_fpu); \ |
| 3289 |
else \
|
| 3290 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
| 3291 |
} \ |
| 3292 |
void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ |
| 3293 |
uint32_t fst1, int cc) \
|
| 3294 |
{ \
|
| 3295 |
int c; \
|
| 3296 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
| 3297 |
fst0 = float32_abs(fst0); \ |
| 3298 |
fst1 = float32_abs(fst1); \ |
| 3299 |
c = cond; \ |
| 3300 |
update_fcr31(env); \ |
| 3301 |
if (c) \
|
| 3302 |
SET_FP_COND(cc, env->active_fpu); \ |
| 3303 |
else \
|
| 3304 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
| 3305 |
} |
| 3306 |
|
| 3307 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
| 3308 |
* but float32_unordered_quiet() is still called. */
|
| 3309 |
FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
|
| 3310 |
FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)) |
| 3311 |
FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
| 3312 |
FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
| 3313 |
FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
| 3314 |
FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
| 3315 |
FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
| 3316 |
FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
| 3317 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
| 3318 |
* but float32_unordered() is still called. */
|
| 3319 |
FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
|
| 3320 |
FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status)) |
| 3321 |
FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
| 3322 |
FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
| 3323 |
FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
| 3324 |
FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
| 3325 |
FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
| 3326 |
FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
| 3327 |
|
| 3328 |
#define FOP_COND_PS(op, condl, condh) \
|
| 3329 |
void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
| 3330 |
uint64_t fdt1, int cc) \
|
| 3331 |
{ \
|
| 3332 |
uint32_t fst0, fsth0, fst1, fsth1; \ |
| 3333 |
int ch, cl; \
|
| 3334 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
| 3335 |
fst0 = fdt0 & 0XFFFFFFFF; \
|
| 3336 |
fsth0 = fdt0 >> 32; \
|
| 3337 |
fst1 = fdt1 & 0XFFFFFFFF; \
|
| 3338 |
fsth1 = fdt1 >> 32; \
|
| 3339 |
cl = condl; \ |
| 3340 |
ch = condh; \ |
| 3341 |
update_fcr31(env); \ |
| 3342 |
if (cl) \
|
| 3343 |
SET_FP_COND(cc, env->active_fpu); \ |
| 3344 |
else \
|
| 3345 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
| 3346 |
if (ch) \
|
| 3347 |
SET_FP_COND(cc + 1, env->active_fpu); \
|
| 3348 |
else \
|
| 3349 |
CLEAR_FP_COND(cc + 1, env->active_fpu); \
|
| 3350 |
} \ |
| 3351 |
void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
| 3352 |
uint64_t fdt1, int cc) \
|
| 3353 |
{ \
|
| 3354 |
uint32_t fst0, fsth0, fst1, fsth1; \ |
| 3355 |
int ch, cl; \
|
| 3356 |
fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
|
| 3357 |
fsth0 = float32_abs(fdt0 >> 32); \
|
| 3358 |
fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
|
| 3359 |
fsth1 = float32_abs(fdt1 >> 32); \
|
| 3360 |
cl = condl; \ |
| 3361 |
ch = condh; \ |
| 3362 |
update_fcr31(env); \ |
| 3363 |
if (cl) \
|
| 3364 |
SET_FP_COND(cc, env->active_fpu); \ |
| 3365 |
else \
|
| 3366 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
| 3367 |
if (ch) \
|
| 3368 |
SET_FP_COND(cc + 1, env->active_fpu); \
|
| 3369 |
else \
|
| 3370 |
CLEAR_FP_COND(cc + 1, env->active_fpu); \
|
| 3371 |
} |
| 3372 |
|
| 3373 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
| 3374 |
* but float32_unordered_quiet() is still called. */
|
| 3375 |
FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
|
| 3376 |
(float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
|
| 3377 |
FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), |
| 3378 |
float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)) |
| 3379 |
FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), |
| 3380 |
float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3381 |
FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), |
| 3382 |
float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3383 |
FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), |
| 3384 |
float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3385 |
FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), |
| 3386 |
float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3387 |
FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), |
| 3388 |
float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3389 |
FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), |
| 3390 |
float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3391 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
| 3392 |
* but float32_unordered() is still called. */
|
| 3393 |
FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
|
| 3394 |
(float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
|
| 3395 |
FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status), |
| 3396 |
float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)) |
| 3397 |
FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
| 3398 |
float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3399 |
FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
| 3400 |
float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3401 |
FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
| 3402 |
float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3403 |
FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
| 3404 |
float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3405 |
FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status), |
| 3406 |
float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3407 |
FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), |
| 3408 |
float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |