root / target-arm / helper.c @ a88790a1
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1 | b5ff1b31 | bellard | #include <stdio.h> |
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2 | b5ff1b31 | bellard | #include <stdlib.h> |
3 | b5ff1b31 | bellard | #include <string.h> |
4 | b5ff1b31 | bellard | |
5 | b5ff1b31 | bellard | #include "cpu.h" |
6 | b5ff1b31 | bellard | #include "exec-all.h" |
7 | 9ee6e8bb | pbrook | #include "gdbstub.h" |
8 | b26eefb6 | pbrook | #include "helpers.h" |
9 | ca10f867 | aurel32 | #include "qemu-common.h" |
10 | 7bbcb0af | Aurelien Jarno | #include "host-utils.h" |
11 | 4f78c9ad | Paul Brook | #if !defined(CONFIG_USER_ONLY)
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12 | 983fe826 | Paul Brook | #include "hw/loader.h" |
13 | 4f78c9ad | Paul Brook | #endif
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14 | 9ee6e8bb | pbrook | |
15 | 10055562 | Paul Brook | static uint32_t cortexa9_cp15_c0_c1[8] = |
16 | 10055562 | Paul Brook | { 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 }; |
17 | 10055562 | Paul Brook | |
18 | 10055562 | Paul Brook | static uint32_t cortexa9_cp15_c0_c2[8] = |
19 | 10055562 | Paul Brook | { 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 }; |
20 | 10055562 | Paul Brook | |
21 | 9ee6e8bb | pbrook | static uint32_t cortexa8_cp15_c0_c1[8] = |
22 | 9ee6e8bb | pbrook | { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 }; |
23 | 9ee6e8bb | pbrook | |
24 | 9ee6e8bb | pbrook | static uint32_t cortexa8_cp15_c0_c2[8] = |
25 | 9ee6e8bb | pbrook | { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 }; |
26 | 9ee6e8bb | pbrook | |
27 | 9ee6e8bb | pbrook | static uint32_t mpcore_cp15_c0_c1[8] = |
28 | 9ee6e8bb | pbrook | { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 }; |
29 | 9ee6e8bb | pbrook | |
30 | 9ee6e8bb | pbrook | static uint32_t mpcore_cp15_c0_c2[8] = |
31 | 9ee6e8bb | pbrook | { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 }; |
32 | 9ee6e8bb | pbrook | |
33 | 9ee6e8bb | pbrook | static uint32_t arm1136_cp15_c0_c1[8] = |
34 | 9ee6e8bb | pbrook | { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 }; |
35 | 9ee6e8bb | pbrook | |
36 | 9ee6e8bb | pbrook | static uint32_t arm1136_cp15_c0_c2[8] = |
37 | 9ee6e8bb | pbrook | { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 }; |
38 | b5ff1b31 | bellard | |
39 | aaed909a | bellard | static uint32_t cpu_arm_find_by_name(const char *name); |
40 | aaed909a | bellard | |
41 | f3d6b95e | pbrook | static inline void set_feature(CPUARMState *env, int feature) |
42 | f3d6b95e | pbrook | { |
43 | f3d6b95e | pbrook | env->features |= 1u << feature;
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44 | f3d6b95e | pbrook | } |
45 | f3d6b95e | pbrook | |
46 | f3d6b95e | pbrook | static void cpu_reset_model_id(CPUARMState *env, uint32_t id) |
47 | f3d6b95e | pbrook | { |
48 | f3d6b95e | pbrook | env->cp15.c0_cpuid = id; |
49 | f3d6b95e | pbrook | switch (id) {
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50 | f3d6b95e | pbrook | case ARM_CPUID_ARM926:
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51 | f3d6b95e | pbrook | set_feature(env, ARM_FEATURE_VFP); |
52 | f3d6b95e | pbrook | env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
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53 | c1713132 | balrog | env->cp15.c0_cachetype = 0x1dd20d2;
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54 | 610c3c8a | balrog | env->cp15.c1_sys = 0x00090078;
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55 | f3d6b95e | pbrook | break;
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56 | ce819861 | pbrook | case ARM_CPUID_ARM946:
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57 | ce819861 | pbrook | set_feature(env, ARM_FEATURE_MPU); |
58 | ce819861 | pbrook | env->cp15.c0_cachetype = 0x0f004006;
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59 | 610c3c8a | balrog | env->cp15.c1_sys = 0x00000078;
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60 | ce819861 | pbrook | break;
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61 | f3d6b95e | pbrook | case ARM_CPUID_ARM1026:
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62 | f3d6b95e | pbrook | set_feature(env, ARM_FEATURE_VFP); |
63 | f3d6b95e | pbrook | set_feature(env, ARM_FEATURE_AUXCR); |
64 | f3d6b95e | pbrook | env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
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65 | c1713132 | balrog | env->cp15.c0_cachetype = 0x1dd20d2;
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66 | 610c3c8a | balrog | env->cp15.c1_sys = 0x00090078;
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67 | c1713132 | balrog | break;
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68 | 827df9f3 | balrog | case ARM_CPUID_ARM1136_R2:
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69 | 9ee6e8bb | pbrook | case ARM_CPUID_ARM1136:
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70 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_V6); |
71 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_VFP); |
72 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_AUXCR); |
73 | 9ee6e8bb | pbrook | env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
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74 | 9ee6e8bb | pbrook | env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
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75 | 9ee6e8bb | pbrook | env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
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76 | 9ee6e8bb | pbrook | memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); |
77 | 22478e79 | balrog | memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)); |
78 | 9ee6e8bb | pbrook | env->cp15.c0_cachetype = 0x1dd20d2;
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79 | 9ee6e8bb | pbrook | break;
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80 | 9ee6e8bb | pbrook | case ARM_CPUID_ARM11MPCORE:
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81 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_V6); |
82 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_V6K); |
83 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_VFP); |
84 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_AUXCR); |
85 | 9ee6e8bb | pbrook | env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
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86 | 9ee6e8bb | pbrook | env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
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87 | 9ee6e8bb | pbrook | env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
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88 | 9ee6e8bb | pbrook | memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); |
89 | 22478e79 | balrog | memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t)); |
90 | 9ee6e8bb | pbrook | env->cp15.c0_cachetype = 0x1dd20d2;
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91 | 9ee6e8bb | pbrook | break;
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92 | 9ee6e8bb | pbrook | case ARM_CPUID_CORTEXA8:
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93 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_V6); |
94 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_V6K); |
95 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_V7); |
96 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_AUXCR); |
97 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_THUMB2); |
98 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_VFP); |
99 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_VFP3); |
100 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_NEON); |
101 | fe1479c3 | pbrook | set_feature(env, ARM_FEATURE_THUMB2EE); |
102 | 9ee6e8bb | pbrook | env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
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103 | 9ee6e8bb | pbrook | env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
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104 | 9ee6e8bb | pbrook | env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
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105 | 9ee6e8bb | pbrook | memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); |
106 | 22478e79 | balrog | memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t)); |
107 | a49ea279 | pbrook | env->cp15.c0_cachetype = 0x82048004;
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108 | a49ea279 | pbrook | env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3; |
109 | a49ea279 | pbrook | env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ |
110 | a49ea279 | pbrook | env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ |
111 | a49ea279 | pbrook | env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */ |
112 | 9ee6e8bb | pbrook | break;
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113 | 10055562 | Paul Brook | case ARM_CPUID_CORTEXA9:
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114 | 10055562 | Paul Brook | set_feature(env, ARM_FEATURE_V6); |
115 | 10055562 | Paul Brook | set_feature(env, ARM_FEATURE_V6K); |
116 | 10055562 | Paul Brook | set_feature(env, ARM_FEATURE_V7); |
117 | 10055562 | Paul Brook | set_feature(env, ARM_FEATURE_AUXCR); |
118 | 10055562 | Paul Brook | set_feature(env, ARM_FEATURE_THUMB2); |
119 | 10055562 | Paul Brook | set_feature(env, ARM_FEATURE_VFP); |
120 | 10055562 | Paul Brook | set_feature(env, ARM_FEATURE_VFP3); |
121 | 10055562 | Paul Brook | set_feature(env, ARM_FEATURE_VFP_FP16); |
122 | 10055562 | Paul Brook | set_feature(env, ARM_FEATURE_NEON); |
123 | 10055562 | Paul Brook | set_feature(env, ARM_FEATURE_THUMB2EE); |
124 | 10055562 | Paul Brook | env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */ |
125 | 10055562 | Paul Brook | env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
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126 | 10055562 | Paul Brook | env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
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127 | 10055562 | Paul Brook | memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); |
128 | 10055562 | Paul Brook | memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t)); |
129 | 10055562 | Paul Brook | env->cp15.c0_cachetype = 0x80038003;
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130 | 10055562 | Paul Brook | env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; |
131 | 10055562 | Paul Brook | env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ |
132 | 10055562 | Paul Brook | env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ |
133 | 10055562 | Paul Brook | break;
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134 | 9ee6e8bb | pbrook | case ARM_CPUID_CORTEXM3:
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135 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_V6); |
136 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_THUMB2); |
137 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_V7); |
138 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_M); |
139 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_DIV); |
140 | 9ee6e8bb | pbrook | break;
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141 | 9ee6e8bb | pbrook | case ARM_CPUID_ANY: /* For userspace emulation. */ |
142 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_V6); |
143 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_V6K); |
144 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_V7); |
145 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_THUMB2); |
146 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_VFP); |
147 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_VFP3); |
148 | 60011498 | Paul Brook | set_feature(env, ARM_FEATURE_VFP_FP16); |
149 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_NEON); |
150 | fe1479c3 | pbrook | set_feature(env, ARM_FEATURE_THUMB2EE); |
151 | 9ee6e8bb | pbrook | set_feature(env, ARM_FEATURE_DIV); |
152 | 9ee6e8bb | pbrook | break;
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153 | c3d2689d | balrog | case ARM_CPUID_TI915T:
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154 | c3d2689d | balrog | case ARM_CPUID_TI925T:
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155 | c3d2689d | balrog | set_feature(env, ARM_FEATURE_OMAPCP); |
156 | c3d2689d | balrog | env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
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157 | c3d2689d | balrog | env->cp15.c0_cachetype = 0x5109149;
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158 | c3d2689d | balrog | env->cp15.c1_sys = 0x00000070;
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159 | c3d2689d | balrog | env->cp15.c15_i_max = 0x000;
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160 | c3d2689d | balrog | env->cp15.c15_i_min = 0xff0;
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161 | c3d2689d | balrog | break;
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162 | c1713132 | balrog | case ARM_CPUID_PXA250:
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163 | c1713132 | balrog | case ARM_CPUID_PXA255:
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164 | c1713132 | balrog | case ARM_CPUID_PXA260:
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165 | c1713132 | balrog | case ARM_CPUID_PXA261:
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166 | c1713132 | balrog | case ARM_CPUID_PXA262:
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167 | c1713132 | balrog | set_feature(env, ARM_FEATURE_XSCALE); |
168 | c1713132 | balrog | /* JTAG_ID is ((id << 28) | 0x09265013) */
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169 | c1713132 | balrog | env->cp15.c0_cachetype = 0xd172172;
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170 | 610c3c8a | balrog | env->cp15.c1_sys = 0x00000078;
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171 | c1713132 | balrog | break;
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172 | c1713132 | balrog | case ARM_CPUID_PXA270_A0:
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173 | c1713132 | balrog | case ARM_CPUID_PXA270_A1:
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174 | c1713132 | balrog | case ARM_CPUID_PXA270_B0:
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175 | c1713132 | balrog | case ARM_CPUID_PXA270_B1:
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176 | c1713132 | balrog | case ARM_CPUID_PXA270_C0:
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177 | c1713132 | balrog | case ARM_CPUID_PXA270_C5:
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178 | c1713132 | balrog | set_feature(env, ARM_FEATURE_XSCALE); |
179 | c1713132 | balrog | /* JTAG_ID is ((id << 28) | 0x09265013) */
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180 | 18c9b560 | balrog | set_feature(env, ARM_FEATURE_IWMMXT); |
181 | 18c9b560 | balrog | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; |
182 | c1713132 | balrog | env->cp15.c0_cachetype = 0xd172172;
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183 | 610c3c8a | balrog | env->cp15.c1_sys = 0x00000078;
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184 | f3d6b95e | pbrook | break;
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185 | f3d6b95e | pbrook | default:
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186 | f3d6b95e | pbrook | cpu_abort(env, "Bad CPU ID: %x\n", id);
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187 | f3d6b95e | pbrook | break;
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188 | f3d6b95e | pbrook | } |
189 | f3d6b95e | pbrook | } |
190 | f3d6b95e | pbrook | |
191 | 40f137e1 | pbrook | void cpu_reset(CPUARMState *env)
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192 | 40f137e1 | pbrook | { |
193 | f3d6b95e | pbrook | uint32_t id; |
194 | eca1bdf4 | aliguori | |
195 | eca1bdf4 | aliguori | if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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196 | eca1bdf4 | aliguori | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
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197 | eca1bdf4 | aliguori | log_cpu_state(env, 0);
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198 | eca1bdf4 | aliguori | } |
199 | eca1bdf4 | aliguori | |
200 | f3d6b95e | pbrook | id = env->cp15.c0_cpuid; |
201 | f3d6b95e | pbrook | memset(env, 0, offsetof(CPUARMState, breakpoints));
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202 | f3d6b95e | pbrook | if (id)
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203 | f3d6b95e | pbrook | cpu_reset_model_id(env, id); |
204 | 40f137e1 | pbrook | #if defined (CONFIG_USER_ONLY)
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205 | 40f137e1 | pbrook | env->uncached_cpsr = ARM_CPU_MODE_USR; |
206 | 40f137e1 | pbrook | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; |
207 | 40f137e1 | pbrook | #else
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208 | 40f137e1 | pbrook | /* SVC mode with interrupts disabled. */
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209 | 40f137e1 | pbrook | env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
210 | 9ee6e8bb | pbrook | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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211 | 983fe826 | Paul Brook | clear at reset. Initial SP and PC are loaded from ROM. */
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212 | 983fe826 | Paul Brook | if (IS_M(env)) {
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213 | 983fe826 | Paul Brook | uint32_t pc; |
214 | 983fe826 | Paul Brook | uint8_t *rom; |
215 | 9ee6e8bb | pbrook | env->uncached_cpsr &= ~CPSR_I; |
216 | 983fe826 | Paul Brook | rom = rom_ptr(0);
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217 | 983fe826 | Paul Brook | if (rom) {
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218 | 983fe826 | Paul Brook | /* We should really use ldl_phys here, in case the guest
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219 | 983fe826 | Paul Brook | modified flash and reset itself. However images
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220 | 983fe826 | Paul Brook | loaded via -kenrel have not been copied yet, so load the
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221 | 983fe826 | Paul Brook | values directly from there. */
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222 | 983fe826 | Paul Brook | env->regs[13] = ldl_p(rom);
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223 | 983fe826 | Paul Brook | pc = ldl_p(rom + 4);
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224 | 983fe826 | Paul Brook | env->thumb = pc & 1;
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225 | 983fe826 | Paul Brook | env->regs[15] = pc & ~1; |
226 | 983fe826 | Paul Brook | } |
227 | 983fe826 | Paul Brook | } |
228 | 40f137e1 | pbrook | env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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229 | b2fa1797 | pbrook | env->cp15.c2_base_mask = 0xffffc000u;
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230 | 40f137e1 | pbrook | #endif
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231 | f3d6b95e | pbrook | tlb_flush(env, 1);
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232 | 40f137e1 | pbrook | } |
233 | 40f137e1 | pbrook | |
234 | 56aebc89 | pbrook | static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg) |
235 | 56aebc89 | pbrook | { |
236 | 56aebc89 | pbrook | int nregs;
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237 | 56aebc89 | pbrook | |
238 | 56aebc89 | pbrook | /* VFP data registers are always little-endian. */
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239 | 56aebc89 | pbrook | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; |
240 | 56aebc89 | pbrook | if (reg < nregs) {
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241 | 56aebc89 | pbrook | stfq_le_p(buf, env->vfp.regs[reg]); |
242 | 56aebc89 | pbrook | return 8; |
243 | 56aebc89 | pbrook | } |
244 | 56aebc89 | pbrook | if (arm_feature(env, ARM_FEATURE_NEON)) {
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245 | 56aebc89 | pbrook | /* Aliases for Q regs. */
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246 | 56aebc89 | pbrook | nregs += 16;
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247 | 56aebc89 | pbrook | if (reg < nregs) {
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248 | 56aebc89 | pbrook | stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); |
249 | 56aebc89 | pbrook | stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); |
250 | 56aebc89 | pbrook | return 16; |
251 | 56aebc89 | pbrook | } |
252 | 56aebc89 | pbrook | } |
253 | 56aebc89 | pbrook | switch (reg - nregs) {
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254 | 56aebc89 | pbrook | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; |
255 | 56aebc89 | pbrook | case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; |
256 | 56aebc89 | pbrook | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; |
257 | 56aebc89 | pbrook | } |
258 | 56aebc89 | pbrook | return 0; |
259 | 56aebc89 | pbrook | } |
260 | 56aebc89 | pbrook | |
261 | 56aebc89 | pbrook | static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg) |
262 | 56aebc89 | pbrook | { |
263 | 56aebc89 | pbrook | int nregs;
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264 | 56aebc89 | pbrook | |
265 | 56aebc89 | pbrook | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; |
266 | 56aebc89 | pbrook | if (reg < nregs) {
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267 | 56aebc89 | pbrook | env->vfp.regs[reg] = ldfq_le_p(buf); |
268 | 56aebc89 | pbrook | return 8; |
269 | 56aebc89 | pbrook | } |
270 | 56aebc89 | pbrook | if (arm_feature(env, ARM_FEATURE_NEON)) {
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271 | 56aebc89 | pbrook | nregs += 16;
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272 | 56aebc89 | pbrook | if (reg < nregs) {
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273 | 56aebc89 | pbrook | env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); |
274 | 56aebc89 | pbrook | env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); |
275 | 56aebc89 | pbrook | return 16; |
276 | 56aebc89 | pbrook | } |
277 | 56aebc89 | pbrook | } |
278 | 56aebc89 | pbrook | switch (reg - nregs) {
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279 | 56aebc89 | pbrook | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; |
280 | 56aebc89 | pbrook | case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; |
281 | 71b3c3de | Juha Riihimรคki | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
282 | 56aebc89 | pbrook | } |
283 | 56aebc89 | pbrook | return 0; |
284 | 56aebc89 | pbrook | } |
285 | 56aebc89 | pbrook | |
286 | aaed909a | bellard | CPUARMState *cpu_arm_init(const char *cpu_model) |
287 | 40f137e1 | pbrook | { |
288 | 40f137e1 | pbrook | CPUARMState *env; |
289 | aaed909a | bellard | uint32_t id; |
290 | b26eefb6 | pbrook | static int inited = 0; |
291 | 40f137e1 | pbrook | |
292 | aaed909a | bellard | id = cpu_arm_find_by_name(cpu_model); |
293 | aaed909a | bellard | if (id == 0) |
294 | aaed909a | bellard | return NULL; |
295 | 40f137e1 | pbrook | env = qemu_mallocz(sizeof(CPUARMState));
|
296 | 40f137e1 | pbrook | cpu_exec_init(env); |
297 | b26eefb6 | pbrook | if (!inited) {
|
298 | b26eefb6 | pbrook | inited = 1;
|
299 | b26eefb6 | pbrook | arm_translate_init(); |
300 | b26eefb6 | pbrook | } |
301 | b26eefb6 | pbrook | |
302 | 01ba9816 | ths | env->cpu_model_str = cpu_model; |
303 | aaed909a | bellard | env->cp15.c0_cpuid = id; |
304 | 40f137e1 | pbrook | cpu_reset(env); |
305 | 56aebc89 | pbrook | if (arm_feature(env, ARM_FEATURE_NEON)) {
|
306 | 56aebc89 | pbrook | gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
307 | 56aebc89 | pbrook | 51, "arm-neon.xml", 0); |
308 | 56aebc89 | pbrook | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { |
309 | 56aebc89 | pbrook | gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
310 | 56aebc89 | pbrook | 35, "arm-vfp3.xml", 0); |
311 | 56aebc89 | pbrook | } else if (arm_feature(env, ARM_FEATURE_VFP)) { |
312 | 56aebc89 | pbrook | gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
313 | 56aebc89 | pbrook | 19, "arm-vfp.xml", 0); |
314 | 56aebc89 | pbrook | } |
315 | 0bf46a40 | aliguori | qemu_init_vcpu(env); |
316 | 40f137e1 | pbrook | return env;
|
317 | 40f137e1 | pbrook | } |
318 | 40f137e1 | pbrook | |
319 | 3371d272 | pbrook | struct arm_cpu_t {
|
320 | 3371d272 | pbrook | uint32_t id; |
321 | 3371d272 | pbrook | const char *name; |
322 | 3371d272 | pbrook | }; |
323 | 3371d272 | pbrook | |
324 | 3371d272 | pbrook | static const struct arm_cpu_t arm_cpu_names[] = { |
325 | 3371d272 | pbrook | { ARM_CPUID_ARM926, "arm926"},
|
326 | ce819861 | pbrook | { ARM_CPUID_ARM946, "arm946"},
|
327 | 3371d272 | pbrook | { ARM_CPUID_ARM1026, "arm1026"},
|
328 | 9ee6e8bb | pbrook | { ARM_CPUID_ARM1136, "arm1136"},
|
329 | 827df9f3 | balrog | { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
|
330 | 9ee6e8bb | pbrook | { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
|
331 | 9ee6e8bb | pbrook | { ARM_CPUID_CORTEXM3, "cortex-m3"},
|
332 | 9ee6e8bb | pbrook | { ARM_CPUID_CORTEXA8, "cortex-a8"},
|
333 | 10055562 | Paul Brook | { ARM_CPUID_CORTEXA9, "cortex-a9"},
|
334 | c3d2689d | balrog | { ARM_CPUID_TI925T, "ti925t" },
|
335 | c1713132 | balrog | { ARM_CPUID_PXA250, "pxa250" },
|
336 | c1713132 | balrog | { ARM_CPUID_PXA255, "pxa255" },
|
337 | c1713132 | balrog | { ARM_CPUID_PXA260, "pxa260" },
|
338 | c1713132 | balrog | { ARM_CPUID_PXA261, "pxa261" },
|
339 | c1713132 | balrog | { ARM_CPUID_PXA262, "pxa262" },
|
340 | c1713132 | balrog | { ARM_CPUID_PXA270, "pxa270" },
|
341 | c1713132 | balrog | { ARM_CPUID_PXA270_A0, "pxa270-a0" },
|
342 | c1713132 | balrog | { ARM_CPUID_PXA270_A1, "pxa270-a1" },
|
343 | c1713132 | balrog | { ARM_CPUID_PXA270_B0, "pxa270-b0" },
|
344 | c1713132 | balrog | { ARM_CPUID_PXA270_B1, "pxa270-b1" },
|
345 | c1713132 | balrog | { ARM_CPUID_PXA270_C0, "pxa270-c0" },
|
346 | c1713132 | balrog | { ARM_CPUID_PXA270_C5, "pxa270-c5" },
|
347 | 9ee6e8bb | pbrook | { ARM_CPUID_ANY, "any"},
|
348 | 3371d272 | pbrook | { 0, NULL} |
349 | 3371d272 | pbrook | }; |
350 | 3371d272 | pbrook | |
351 | c732abe2 | j_mayer | void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
352 | 5adb4839 | pbrook | { |
353 | 5adb4839 | pbrook | int i;
|
354 | 5adb4839 | pbrook | |
355 | c732abe2 | j_mayer | (*cpu_fprintf)(f, "Available CPUs:\n");
|
356 | 5adb4839 | pbrook | for (i = 0; arm_cpu_names[i].name; i++) { |
357 | c732abe2 | j_mayer | (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
|
358 | 5adb4839 | pbrook | } |
359 | 5adb4839 | pbrook | } |
360 | 5adb4839 | pbrook | |
361 | aaed909a | bellard | /* return 0 if not found */
|
362 | aaed909a | bellard | static uint32_t cpu_arm_find_by_name(const char *name) |
363 | 40f137e1 | pbrook | { |
364 | 3371d272 | pbrook | int i;
|
365 | 3371d272 | pbrook | uint32_t id; |
366 | 3371d272 | pbrook | |
367 | 3371d272 | pbrook | id = 0;
|
368 | 3371d272 | pbrook | for (i = 0; arm_cpu_names[i].name; i++) { |
369 | 3371d272 | pbrook | if (strcmp(name, arm_cpu_names[i].name) == 0) { |
370 | 3371d272 | pbrook | id = arm_cpu_names[i].id; |
371 | 3371d272 | pbrook | break;
|
372 | 3371d272 | pbrook | } |
373 | 3371d272 | pbrook | } |
374 | aaed909a | bellard | return id;
|
375 | 40f137e1 | pbrook | } |
376 | 40f137e1 | pbrook | |
377 | 40f137e1 | pbrook | void cpu_arm_close(CPUARMState *env)
|
378 | 40f137e1 | pbrook | { |
379 | 40f137e1 | pbrook | free(env); |
380 | 40f137e1 | pbrook | } |
381 | 40f137e1 | pbrook | |
382 | 2f4a40e5 | balrog | uint32_t cpsr_read(CPUARMState *env) |
383 | 2f4a40e5 | balrog | { |
384 | 2f4a40e5 | balrog | int ZF;
|
385 | 6fbe23d5 | pbrook | ZF = (env->ZF == 0);
|
386 | 6fbe23d5 | pbrook | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | |
387 | 2f4a40e5 | balrog | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
388 | 2f4a40e5 | balrog | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) |
389 | 2f4a40e5 | balrog | | ((env->condexec_bits & 0xfc) << 8) |
390 | 2f4a40e5 | balrog | | (env->GE << 16);
|
391 | 2f4a40e5 | balrog | } |
392 | 2f4a40e5 | balrog | |
393 | 2f4a40e5 | balrog | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
|
394 | 2f4a40e5 | balrog | { |
395 | 2f4a40e5 | balrog | if (mask & CPSR_NZCV) {
|
396 | 6fbe23d5 | pbrook | env->ZF = (~val) & CPSR_Z; |
397 | 6fbe23d5 | pbrook | env->NF = val; |
398 | 2f4a40e5 | balrog | env->CF = (val >> 29) & 1; |
399 | 2f4a40e5 | balrog | env->VF = (val << 3) & 0x80000000; |
400 | 2f4a40e5 | balrog | } |
401 | 2f4a40e5 | balrog | if (mask & CPSR_Q)
|
402 | 2f4a40e5 | balrog | env->QF = ((val & CPSR_Q) != 0);
|
403 | 2f4a40e5 | balrog | if (mask & CPSR_T)
|
404 | 2f4a40e5 | balrog | env->thumb = ((val & CPSR_T) != 0);
|
405 | 2f4a40e5 | balrog | if (mask & CPSR_IT_0_1) {
|
406 | 2f4a40e5 | balrog | env->condexec_bits &= ~3;
|
407 | 2f4a40e5 | balrog | env->condexec_bits |= (val >> 25) & 3; |
408 | 2f4a40e5 | balrog | } |
409 | 2f4a40e5 | balrog | if (mask & CPSR_IT_2_7) {
|
410 | 2f4a40e5 | balrog | env->condexec_bits &= 3;
|
411 | 2f4a40e5 | balrog | env->condexec_bits |= (val >> 8) & 0xfc; |
412 | 2f4a40e5 | balrog | } |
413 | 2f4a40e5 | balrog | if (mask & CPSR_GE) {
|
414 | 2f4a40e5 | balrog | env->GE = (val >> 16) & 0xf; |
415 | 2f4a40e5 | balrog | } |
416 | 2f4a40e5 | balrog | |
417 | 2f4a40e5 | balrog | if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
|
418 | 2f4a40e5 | balrog | switch_mode(env, val & CPSR_M); |
419 | 2f4a40e5 | balrog | } |
420 | 2f4a40e5 | balrog | mask &= ~CACHED_CPSR_BITS; |
421 | 2f4a40e5 | balrog | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); |
422 | 2f4a40e5 | balrog | } |
423 | 2f4a40e5 | balrog | |
424 | b26eefb6 | pbrook | /* Sign/zero extend */
|
425 | b26eefb6 | pbrook | uint32_t HELPER(sxtb16)(uint32_t x) |
426 | b26eefb6 | pbrook | { |
427 | b26eefb6 | pbrook | uint32_t res; |
428 | b26eefb6 | pbrook | res = (uint16_t)(int8_t)x; |
429 | b26eefb6 | pbrook | res |= (uint32_t)(int8_t)(x >> 16) << 16; |
430 | b26eefb6 | pbrook | return res;
|
431 | b26eefb6 | pbrook | } |
432 | b26eefb6 | pbrook | |
433 | b26eefb6 | pbrook | uint32_t HELPER(uxtb16)(uint32_t x) |
434 | b26eefb6 | pbrook | { |
435 | b26eefb6 | pbrook | uint32_t res; |
436 | b26eefb6 | pbrook | res = (uint16_t)(uint8_t)x; |
437 | b26eefb6 | pbrook | res |= (uint32_t)(uint8_t)(x >> 16) << 16; |
438 | b26eefb6 | pbrook | return res;
|
439 | b26eefb6 | pbrook | } |
440 | b26eefb6 | pbrook | |
441 | f51bbbfe | pbrook | uint32_t HELPER(clz)(uint32_t x) |
442 | f51bbbfe | pbrook | { |
443 | 7bbcb0af | Aurelien Jarno | return clz32(x);
|
444 | f51bbbfe | pbrook | } |
445 | f51bbbfe | pbrook | |
446 | 3670669c | pbrook | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
447 | 3670669c | pbrook | { |
448 | 3670669c | pbrook | if (den == 0) |
449 | 3670669c | pbrook | return 0; |
450 | 686eeb93 | Aurelien Jarno | if (num == INT_MIN && den == -1) |
451 | 686eeb93 | Aurelien Jarno | return INT_MIN;
|
452 | 3670669c | pbrook | return num / den;
|
453 | 3670669c | pbrook | } |
454 | 3670669c | pbrook | |
455 | 3670669c | pbrook | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) |
456 | 3670669c | pbrook | { |
457 | 3670669c | pbrook | if (den == 0) |
458 | 3670669c | pbrook | return 0; |
459 | 3670669c | pbrook | return num / den;
|
460 | 3670669c | pbrook | } |
461 | 3670669c | pbrook | |
462 | 3670669c | pbrook | uint32_t HELPER(rbit)(uint32_t x) |
463 | 3670669c | pbrook | { |
464 | 3670669c | pbrook | x = ((x & 0xff000000) >> 24) |
465 | 3670669c | pbrook | | ((x & 0x00ff0000) >> 8) |
466 | 3670669c | pbrook | | ((x & 0x0000ff00) << 8) |
467 | 3670669c | pbrook | | ((x & 0x000000ff) << 24); |
468 | 3670669c | pbrook | x = ((x & 0xf0f0f0f0) >> 4) |
469 | 3670669c | pbrook | | ((x & 0x0f0f0f0f) << 4); |
470 | 3670669c | pbrook | x = ((x & 0x88888888) >> 3) |
471 | 3670669c | pbrook | | ((x & 0x44444444) >> 1) |
472 | 3670669c | pbrook | | ((x & 0x22222222) << 1) |
473 | 3670669c | pbrook | | ((x & 0x11111111) << 3); |
474 | 3670669c | pbrook | return x;
|
475 | 3670669c | pbrook | } |
476 | 3670669c | pbrook | |
477 | ad69471c | pbrook | uint32_t HELPER(abs)(uint32_t x) |
478 | ad69471c | pbrook | { |
479 | ad69471c | pbrook | return ((int32_t)x < 0) ? -x : x; |
480 | ad69471c | pbrook | } |
481 | ad69471c | pbrook | |
482 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
|
483 | b5ff1b31 | bellard | |
484 | b5ff1b31 | bellard | void do_interrupt (CPUState *env)
|
485 | b5ff1b31 | bellard | { |
486 | b5ff1b31 | bellard | env->exception_index = -1;
|
487 | b5ff1b31 | bellard | } |
488 | b5ff1b31 | bellard | |
489 | b5ff1b31 | bellard | int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
490 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
491 | b5ff1b31 | bellard | { |
492 | b5ff1b31 | bellard | if (rw == 2) { |
493 | b5ff1b31 | bellard | env->exception_index = EXCP_PREFETCH_ABORT; |
494 | b5ff1b31 | bellard | env->cp15.c6_insn = address; |
495 | b5ff1b31 | bellard | } else {
|
496 | b5ff1b31 | bellard | env->exception_index = EXCP_DATA_ABORT; |
497 | b5ff1b31 | bellard | env->cp15.c6_data = address; |
498 | b5ff1b31 | bellard | } |
499 | b5ff1b31 | bellard | return 1; |
500 | b5ff1b31 | bellard | } |
501 | b5ff1b31 | bellard | |
502 | b5ff1b31 | bellard | /* These should probably raise undefined insn exceptions. */
|
503 | 8984bd2e | pbrook | void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
|
504 | c1713132 | balrog | { |
505 | c1713132 | balrog | int op1 = (insn >> 8) & 0xf; |
506 | c1713132 | balrog | cpu_abort(env, "cp%i insn %08x\n", op1, insn);
|
507 | c1713132 | balrog | return;
|
508 | c1713132 | balrog | } |
509 | c1713132 | balrog | |
510 | 8984bd2e | pbrook | uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn) |
511 | c1713132 | balrog | { |
512 | c1713132 | balrog | int op1 = (insn >> 8) & 0xf; |
513 | c1713132 | balrog | cpu_abort(env, "cp%i insn %08x\n", op1, insn);
|
514 | c1713132 | balrog | return 0; |
515 | c1713132 | balrog | } |
516 | c1713132 | balrog | |
517 | 8984bd2e | pbrook | void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
|
518 | b5ff1b31 | bellard | { |
519 | b5ff1b31 | bellard | cpu_abort(env, "cp15 insn %08x\n", insn);
|
520 | b5ff1b31 | bellard | } |
521 | b5ff1b31 | bellard | |
522 | 8984bd2e | pbrook | uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) |
523 | b5ff1b31 | bellard | { |
524 | b5ff1b31 | bellard | cpu_abort(env, "cp15 insn %08x\n", insn);
|
525 | b5ff1b31 | bellard | } |
526 | b5ff1b31 | bellard | |
527 | 9ee6e8bb | pbrook | /* These should probably raise undefined insn exceptions. */
|
528 | 8984bd2e | pbrook | void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
|
529 | 9ee6e8bb | pbrook | { |
530 | 9ee6e8bb | pbrook | cpu_abort(env, "v7m_mrs %d\n", reg);
|
531 | 9ee6e8bb | pbrook | } |
532 | 9ee6e8bb | pbrook | |
533 | 8984bd2e | pbrook | uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) |
534 | 9ee6e8bb | pbrook | { |
535 | 9ee6e8bb | pbrook | cpu_abort(env, "v7m_mrs %d\n", reg);
|
536 | 9ee6e8bb | pbrook | return 0; |
537 | 9ee6e8bb | pbrook | } |
538 | 9ee6e8bb | pbrook | |
539 | b5ff1b31 | bellard | void switch_mode(CPUState *env, int mode) |
540 | b5ff1b31 | bellard | { |
541 | b5ff1b31 | bellard | if (mode != ARM_CPU_MODE_USR)
|
542 | b5ff1b31 | bellard | cpu_abort(env, "Tried to switch out of user mode\n");
|
543 | b5ff1b31 | bellard | } |
544 | b5ff1b31 | bellard | |
545 | b0109805 | pbrook | void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
|
546 | 9ee6e8bb | pbrook | { |
547 | 9ee6e8bb | pbrook | cpu_abort(env, "banked r13 write\n");
|
548 | 9ee6e8bb | pbrook | } |
549 | 9ee6e8bb | pbrook | |
550 | b0109805 | pbrook | uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode) |
551 | 9ee6e8bb | pbrook | { |
552 | 9ee6e8bb | pbrook | cpu_abort(env, "banked r13 read\n");
|
553 | 9ee6e8bb | pbrook | return 0; |
554 | 9ee6e8bb | pbrook | } |
555 | 9ee6e8bb | pbrook | |
556 | b5ff1b31 | bellard | #else
|
557 | b5ff1b31 | bellard | |
558 | 8e71621f | pbrook | extern int semihosting_enabled; |
559 | 8e71621f | pbrook | |
560 | b5ff1b31 | bellard | /* Map CPU modes onto saved register banks. */
|
561 | b5ff1b31 | bellard | static inline int bank_number (int mode) |
562 | b5ff1b31 | bellard | { |
563 | b5ff1b31 | bellard | switch (mode) {
|
564 | b5ff1b31 | bellard | case ARM_CPU_MODE_USR:
|
565 | b5ff1b31 | bellard | case ARM_CPU_MODE_SYS:
|
566 | b5ff1b31 | bellard | return 0; |
567 | b5ff1b31 | bellard | case ARM_CPU_MODE_SVC:
|
568 | b5ff1b31 | bellard | return 1; |
569 | b5ff1b31 | bellard | case ARM_CPU_MODE_ABT:
|
570 | b5ff1b31 | bellard | return 2; |
571 | b5ff1b31 | bellard | case ARM_CPU_MODE_UND:
|
572 | b5ff1b31 | bellard | return 3; |
573 | b5ff1b31 | bellard | case ARM_CPU_MODE_IRQ:
|
574 | b5ff1b31 | bellard | return 4; |
575 | b5ff1b31 | bellard | case ARM_CPU_MODE_FIQ:
|
576 | b5ff1b31 | bellard | return 5; |
577 | b5ff1b31 | bellard | } |
578 | b5ff1b31 | bellard | cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
|
579 | b5ff1b31 | bellard | return -1; |
580 | b5ff1b31 | bellard | } |
581 | b5ff1b31 | bellard | |
582 | b5ff1b31 | bellard | void switch_mode(CPUState *env, int mode) |
583 | b5ff1b31 | bellard | { |
584 | b5ff1b31 | bellard | int old_mode;
|
585 | b5ff1b31 | bellard | int i;
|
586 | b5ff1b31 | bellard | |
587 | b5ff1b31 | bellard | old_mode = env->uncached_cpsr & CPSR_M; |
588 | b5ff1b31 | bellard | if (mode == old_mode)
|
589 | b5ff1b31 | bellard | return;
|
590 | b5ff1b31 | bellard | |
591 | b5ff1b31 | bellard | if (old_mode == ARM_CPU_MODE_FIQ) {
|
592 | b5ff1b31 | bellard | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
593 | 8637c67f | pbrook | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
594 | b5ff1b31 | bellard | } else if (mode == ARM_CPU_MODE_FIQ) { |
595 | b5ff1b31 | bellard | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
596 | 8637c67f | pbrook | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
597 | b5ff1b31 | bellard | } |
598 | b5ff1b31 | bellard | |
599 | b5ff1b31 | bellard | i = bank_number(old_mode); |
600 | b5ff1b31 | bellard | env->banked_r13[i] = env->regs[13];
|
601 | b5ff1b31 | bellard | env->banked_r14[i] = env->regs[14];
|
602 | b5ff1b31 | bellard | env->banked_spsr[i] = env->spsr; |
603 | b5ff1b31 | bellard | |
604 | b5ff1b31 | bellard | i = bank_number(mode); |
605 | b5ff1b31 | bellard | env->regs[13] = env->banked_r13[i];
|
606 | b5ff1b31 | bellard | env->regs[14] = env->banked_r14[i];
|
607 | b5ff1b31 | bellard | env->spsr = env->banked_spsr[i]; |
608 | b5ff1b31 | bellard | } |
609 | b5ff1b31 | bellard | |
610 | 9ee6e8bb | pbrook | static void v7m_push(CPUARMState *env, uint32_t val) |
611 | 9ee6e8bb | pbrook | { |
612 | 9ee6e8bb | pbrook | env->regs[13] -= 4; |
613 | 9ee6e8bb | pbrook | stl_phys(env->regs[13], val);
|
614 | 9ee6e8bb | pbrook | } |
615 | 9ee6e8bb | pbrook | |
616 | 9ee6e8bb | pbrook | static uint32_t v7m_pop(CPUARMState *env)
|
617 | 9ee6e8bb | pbrook | { |
618 | 9ee6e8bb | pbrook | uint32_t val; |
619 | 9ee6e8bb | pbrook | val = ldl_phys(env->regs[13]);
|
620 | 9ee6e8bb | pbrook | env->regs[13] += 4; |
621 | 9ee6e8bb | pbrook | return val;
|
622 | 9ee6e8bb | pbrook | } |
623 | 9ee6e8bb | pbrook | |
624 | 9ee6e8bb | pbrook | /* Switch to V7M main or process stack pointer. */
|
625 | 9ee6e8bb | pbrook | static void switch_v7m_sp(CPUARMState *env, int process) |
626 | 9ee6e8bb | pbrook | { |
627 | 9ee6e8bb | pbrook | uint32_t tmp; |
628 | 9ee6e8bb | pbrook | if (env->v7m.current_sp != process) {
|
629 | 9ee6e8bb | pbrook | tmp = env->v7m.other_sp; |
630 | 9ee6e8bb | pbrook | env->v7m.other_sp = env->regs[13];
|
631 | 9ee6e8bb | pbrook | env->regs[13] = tmp;
|
632 | 9ee6e8bb | pbrook | env->v7m.current_sp = process; |
633 | 9ee6e8bb | pbrook | } |
634 | 9ee6e8bb | pbrook | } |
635 | 9ee6e8bb | pbrook | |
636 | 9ee6e8bb | pbrook | static void do_v7m_exception_exit(CPUARMState *env) |
637 | 9ee6e8bb | pbrook | { |
638 | 9ee6e8bb | pbrook | uint32_t type; |
639 | 9ee6e8bb | pbrook | uint32_t xpsr; |
640 | 9ee6e8bb | pbrook | |
641 | 9ee6e8bb | pbrook | type = env->regs[15];
|
642 | 9ee6e8bb | pbrook | if (env->v7m.exception != 0) |
643 | 983fe826 | Paul Brook | armv7m_nvic_complete_irq(env->nvic, env->v7m.exception); |
644 | 9ee6e8bb | pbrook | |
645 | 9ee6e8bb | pbrook | /* Switch to the target stack. */
|
646 | 9ee6e8bb | pbrook | switch_v7m_sp(env, (type & 4) != 0); |
647 | 9ee6e8bb | pbrook | /* Pop registers. */
|
648 | 9ee6e8bb | pbrook | env->regs[0] = v7m_pop(env);
|
649 | 9ee6e8bb | pbrook | env->regs[1] = v7m_pop(env);
|
650 | 9ee6e8bb | pbrook | env->regs[2] = v7m_pop(env);
|
651 | 9ee6e8bb | pbrook | env->regs[3] = v7m_pop(env);
|
652 | 9ee6e8bb | pbrook | env->regs[12] = v7m_pop(env);
|
653 | 9ee6e8bb | pbrook | env->regs[14] = v7m_pop(env);
|
654 | 9ee6e8bb | pbrook | env->regs[15] = v7m_pop(env);
|
655 | 9ee6e8bb | pbrook | xpsr = v7m_pop(env); |
656 | 9ee6e8bb | pbrook | xpsr_write(env, xpsr, 0xfffffdff);
|
657 | 9ee6e8bb | pbrook | /* Undo stack alignment. */
|
658 | 9ee6e8bb | pbrook | if (xpsr & 0x200) |
659 | 9ee6e8bb | pbrook | env->regs[13] |= 4; |
660 | 9ee6e8bb | pbrook | /* ??? The exception return type specifies Thread/Handler mode. However
|
661 | 9ee6e8bb | pbrook | this is also implied by the xPSR value. Not sure what to do
|
662 | 9ee6e8bb | pbrook | if there is a mismatch. */
|
663 | 9ee6e8bb | pbrook | /* ??? Likewise for mismatches between the CONTROL register and the stack
|
664 | 9ee6e8bb | pbrook | pointer. */
|
665 | 9ee6e8bb | pbrook | } |
666 | 9ee6e8bb | pbrook | |
667 | 2b3ea315 | aurel32 | static void do_interrupt_v7m(CPUARMState *env) |
668 | 9ee6e8bb | pbrook | { |
669 | 9ee6e8bb | pbrook | uint32_t xpsr = xpsr_read(env); |
670 | 9ee6e8bb | pbrook | uint32_t lr; |
671 | 9ee6e8bb | pbrook | uint32_t addr; |
672 | 9ee6e8bb | pbrook | |
673 | 9ee6e8bb | pbrook | lr = 0xfffffff1;
|
674 | 9ee6e8bb | pbrook | if (env->v7m.current_sp)
|
675 | 9ee6e8bb | pbrook | lr |= 4;
|
676 | 9ee6e8bb | pbrook | if (env->v7m.exception == 0) |
677 | 9ee6e8bb | pbrook | lr |= 8;
|
678 | 9ee6e8bb | pbrook | |
679 | 9ee6e8bb | pbrook | /* For exceptions we just mark as pending on the NVIC, and let that
|
680 | 9ee6e8bb | pbrook | handle it. */
|
681 | 9ee6e8bb | pbrook | /* TODO: Need to escalate if the current priority is higher than the
|
682 | 9ee6e8bb | pbrook | one we're raising. */
|
683 | 9ee6e8bb | pbrook | switch (env->exception_index) {
|
684 | 9ee6e8bb | pbrook | case EXCP_UDEF:
|
685 | 983fe826 | Paul Brook | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); |
686 | 9ee6e8bb | pbrook | return;
|
687 | 9ee6e8bb | pbrook | case EXCP_SWI:
|
688 | 9ee6e8bb | pbrook | env->regs[15] += 2; |
689 | 983fe826 | Paul Brook | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); |
690 | 9ee6e8bb | pbrook | return;
|
691 | 9ee6e8bb | pbrook | case EXCP_PREFETCH_ABORT:
|
692 | 9ee6e8bb | pbrook | case EXCP_DATA_ABORT:
|
693 | 983fe826 | Paul Brook | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); |
694 | 9ee6e8bb | pbrook | return;
|
695 | 9ee6e8bb | pbrook | case EXCP_BKPT:
|
696 | 2ad207d4 | pbrook | if (semihosting_enabled) {
|
697 | 2ad207d4 | pbrook | int nr;
|
698 | 2ad207d4 | pbrook | nr = lduw_code(env->regs[15]) & 0xff; |
699 | 2ad207d4 | pbrook | if (nr == 0xab) { |
700 | 2ad207d4 | pbrook | env->regs[15] += 2; |
701 | 2ad207d4 | pbrook | env->regs[0] = do_arm_semihosting(env);
|
702 | 2ad207d4 | pbrook | return;
|
703 | 2ad207d4 | pbrook | } |
704 | 2ad207d4 | pbrook | } |
705 | 983fe826 | Paul Brook | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); |
706 | 9ee6e8bb | pbrook | return;
|
707 | 9ee6e8bb | pbrook | case EXCP_IRQ:
|
708 | 983fe826 | Paul Brook | env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); |
709 | 9ee6e8bb | pbrook | break;
|
710 | 9ee6e8bb | pbrook | case EXCP_EXCEPTION_EXIT:
|
711 | 9ee6e8bb | pbrook | do_v7m_exception_exit(env); |
712 | 9ee6e8bb | pbrook | return;
|
713 | 9ee6e8bb | pbrook | default:
|
714 | 9ee6e8bb | pbrook | cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
|
715 | 9ee6e8bb | pbrook | return; /* Never happens. Keep compiler happy. */ |
716 | 9ee6e8bb | pbrook | } |
717 | 9ee6e8bb | pbrook | |
718 | 9ee6e8bb | pbrook | /* Align stack pointer. */
|
719 | 9ee6e8bb | pbrook | /* ??? Should only do this if Configuration Control Register
|
720 | 9ee6e8bb | pbrook | STACKALIGN bit is set. */
|
721 | 9ee6e8bb | pbrook | if (env->regs[13] & 4) { |
722 | ab19b0ec | pbrook | env->regs[13] -= 4; |
723 | 9ee6e8bb | pbrook | xpsr |= 0x200;
|
724 | 9ee6e8bb | pbrook | } |
725 | 6c95676b | balrog | /* Switch to the handler mode. */
|
726 | 9ee6e8bb | pbrook | v7m_push(env, xpsr); |
727 | 9ee6e8bb | pbrook | v7m_push(env, env->regs[15]);
|
728 | 9ee6e8bb | pbrook | v7m_push(env, env->regs[14]);
|
729 | 9ee6e8bb | pbrook | v7m_push(env, env->regs[12]);
|
730 | 9ee6e8bb | pbrook | v7m_push(env, env->regs[3]);
|
731 | 9ee6e8bb | pbrook | v7m_push(env, env->regs[2]);
|
732 | 9ee6e8bb | pbrook | v7m_push(env, env->regs[1]);
|
733 | 9ee6e8bb | pbrook | v7m_push(env, env->regs[0]);
|
734 | 9ee6e8bb | pbrook | switch_v7m_sp(env, 0);
|
735 | 9ee6e8bb | pbrook | env->uncached_cpsr &= ~CPSR_IT; |
736 | 9ee6e8bb | pbrook | env->regs[14] = lr;
|
737 | 9ee6e8bb | pbrook | addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
|
738 | 9ee6e8bb | pbrook | env->regs[15] = addr & 0xfffffffe; |
739 | 9ee6e8bb | pbrook | env->thumb = addr & 1;
|
740 | 9ee6e8bb | pbrook | } |
741 | 9ee6e8bb | pbrook | |
742 | b5ff1b31 | bellard | /* Handle a CPU exception. */
|
743 | b5ff1b31 | bellard | void do_interrupt(CPUARMState *env)
|
744 | b5ff1b31 | bellard | { |
745 | b5ff1b31 | bellard | uint32_t addr; |
746 | b5ff1b31 | bellard | uint32_t mask; |
747 | b5ff1b31 | bellard | int new_mode;
|
748 | b5ff1b31 | bellard | uint32_t offset; |
749 | b5ff1b31 | bellard | |
750 | 9ee6e8bb | pbrook | if (IS_M(env)) {
|
751 | 9ee6e8bb | pbrook | do_interrupt_v7m(env); |
752 | 9ee6e8bb | pbrook | return;
|
753 | 9ee6e8bb | pbrook | } |
754 | b5ff1b31 | bellard | /* TODO: Vectored interrupt controller. */
|
755 | b5ff1b31 | bellard | switch (env->exception_index) {
|
756 | b5ff1b31 | bellard | case EXCP_UDEF:
|
757 | b5ff1b31 | bellard | new_mode = ARM_CPU_MODE_UND; |
758 | b5ff1b31 | bellard | addr = 0x04;
|
759 | b5ff1b31 | bellard | mask = CPSR_I; |
760 | b5ff1b31 | bellard | if (env->thumb)
|
761 | b5ff1b31 | bellard | offset = 2;
|
762 | b5ff1b31 | bellard | else
|
763 | b5ff1b31 | bellard | offset = 4;
|
764 | b5ff1b31 | bellard | break;
|
765 | b5ff1b31 | bellard | case EXCP_SWI:
|
766 | 8e71621f | pbrook | if (semihosting_enabled) {
|
767 | 8e71621f | pbrook | /* Check for semihosting interrupt. */
|
768 | 8e71621f | pbrook | if (env->thumb) {
|
769 | 8e71621f | pbrook | mask = lduw_code(env->regs[15] - 2) & 0xff; |
770 | 8e71621f | pbrook | } else {
|
771 | 8e71621f | pbrook | mask = ldl_code(env->regs[15] - 4) & 0xffffff; |
772 | 8e71621f | pbrook | } |
773 | 8e71621f | pbrook | /* Only intercept calls from privileged modes, to provide some
|
774 | 8e71621f | pbrook | semblance of security. */
|
775 | 8e71621f | pbrook | if (((mask == 0x123456 && !env->thumb) |
776 | 8e71621f | pbrook | || (mask == 0xab && env->thumb))
|
777 | 8e71621f | pbrook | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { |
778 | 8e71621f | pbrook | env->regs[0] = do_arm_semihosting(env);
|
779 | 8e71621f | pbrook | return;
|
780 | 8e71621f | pbrook | } |
781 | 8e71621f | pbrook | } |
782 | b5ff1b31 | bellard | new_mode = ARM_CPU_MODE_SVC; |
783 | b5ff1b31 | bellard | addr = 0x08;
|
784 | b5ff1b31 | bellard | mask = CPSR_I; |
785 | 601d70b9 | balrog | /* The PC already points to the next instruction. */
|
786 | b5ff1b31 | bellard | offset = 0;
|
787 | b5ff1b31 | bellard | break;
|
788 | 06c949e6 | pbrook | case EXCP_BKPT:
|
789 | 9ee6e8bb | pbrook | /* See if this is a semihosting syscall. */
|
790 | 2ad207d4 | pbrook | if (env->thumb && semihosting_enabled) {
|
791 | 9ee6e8bb | pbrook | mask = lduw_code(env->regs[15]) & 0xff; |
792 | 9ee6e8bb | pbrook | if (mask == 0xab |
793 | 9ee6e8bb | pbrook | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { |
794 | 9ee6e8bb | pbrook | env->regs[15] += 2; |
795 | 9ee6e8bb | pbrook | env->regs[0] = do_arm_semihosting(env);
|
796 | 9ee6e8bb | pbrook | return;
|
797 | 9ee6e8bb | pbrook | } |
798 | 9ee6e8bb | pbrook | } |
799 | 9ee6e8bb | pbrook | /* Fall through to prefetch abort. */
|
800 | 9ee6e8bb | pbrook | case EXCP_PREFETCH_ABORT:
|
801 | b5ff1b31 | bellard | new_mode = ARM_CPU_MODE_ABT; |
802 | b5ff1b31 | bellard | addr = 0x0c;
|
803 | b5ff1b31 | bellard | mask = CPSR_A | CPSR_I; |
804 | b5ff1b31 | bellard | offset = 4;
|
805 | b5ff1b31 | bellard | break;
|
806 | b5ff1b31 | bellard | case EXCP_DATA_ABORT:
|
807 | b5ff1b31 | bellard | new_mode = ARM_CPU_MODE_ABT; |
808 | b5ff1b31 | bellard | addr = 0x10;
|
809 | b5ff1b31 | bellard | mask = CPSR_A | CPSR_I; |
810 | b5ff1b31 | bellard | offset = 8;
|
811 | b5ff1b31 | bellard | break;
|
812 | b5ff1b31 | bellard | case EXCP_IRQ:
|
813 | b5ff1b31 | bellard | new_mode = ARM_CPU_MODE_IRQ; |
814 | b5ff1b31 | bellard | addr = 0x18;
|
815 | b5ff1b31 | bellard | /* Disable IRQ and imprecise data aborts. */
|
816 | b5ff1b31 | bellard | mask = CPSR_A | CPSR_I; |
817 | b5ff1b31 | bellard | offset = 4;
|
818 | b5ff1b31 | bellard | break;
|
819 | b5ff1b31 | bellard | case EXCP_FIQ:
|
820 | b5ff1b31 | bellard | new_mode = ARM_CPU_MODE_FIQ; |
821 | b5ff1b31 | bellard | addr = 0x1c;
|
822 | b5ff1b31 | bellard | /* Disable FIQ, IRQ and imprecise data aborts. */
|
823 | b5ff1b31 | bellard | mask = CPSR_A | CPSR_I | CPSR_F; |
824 | b5ff1b31 | bellard | offset = 4;
|
825 | b5ff1b31 | bellard | break;
|
826 | b5ff1b31 | bellard | default:
|
827 | b5ff1b31 | bellard | cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
|
828 | b5ff1b31 | bellard | return; /* Never happens. Keep compiler happy. */ |
829 | b5ff1b31 | bellard | } |
830 | b5ff1b31 | bellard | /* High vectors. */
|
831 | b5ff1b31 | bellard | if (env->cp15.c1_sys & (1 << 13)) { |
832 | b5ff1b31 | bellard | addr += 0xffff0000;
|
833 | b5ff1b31 | bellard | } |
834 | b5ff1b31 | bellard | switch_mode (env, new_mode); |
835 | b5ff1b31 | bellard | env->spsr = cpsr_read(env); |
836 | 9ee6e8bb | pbrook | /* Clear IT bits. */
|
837 | 9ee6e8bb | pbrook | env->condexec_bits = 0;
|
838 | 30a8cac1 | Rabin Vincent | /* Switch to the new mode, and to the correct instruction set. */
|
839 | 6d7e6326 | bellard | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
840 | b5ff1b31 | bellard | env->uncached_cpsr |= mask; |
841 | 30a8cac1 | Rabin Vincent | env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0; |
842 | b5ff1b31 | bellard | env->regs[14] = env->regs[15] + offset; |
843 | b5ff1b31 | bellard | env->regs[15] = addr;
|
844 | b5ff1b31 | bellard | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
845 | b5ff1b31 | bellard | } |
846 | b5ff1b31 | bellard | |
847 | b5ff1b31 | bellard | /* Check section/page access permissions.
|
848 | b5ff1b31 | bellard | Returns the page protection flags, or zero if the access is not
|
849 | b5ff1b31 | bellard | permitted. */
|
850 | b5ff1b31 | bellard | static inline int check_ap(CPUState *env, int ap, int domain, int access_type, |
851 | b5ff1b31 | bellard | int is_user)
|
852 | b5ff1b31 | bellard | { |
853 | 9ee6e8bb | pbrook | int prot_ro;
|
854 | 9ee6e8bb | pbrook | |
855 | b5ff1b31 | bellard | if (domain == 3) |
856 | b5ff1b31 | bellard | return PAGE_READ | PAGE_WRITE;
|
857 | b5ff1b31 | bellard | |
858 | 9ee6e8bb | pbrook | if (access_type == 1) |
859 | 9ee6e8bb | pbrook | prot_ro = 0;
|
860 | 9ee6e8bb | pbrook | else
|
861 | 9ee6e8bb | pbrook | prot_ro = PAGE_READ; |
862 | 9ee6e8bb | pbrook | |
863 | b5ff1b31 | bellard | switch (ap) {
|
864 | b5ff1b31 | bellard | case 0: |
865 | 78600320 | pbrook | if (access_type == 1) |
866 | b5ff1b31 | bellard | return 0; |
867 | b5ff1b31 | bellard | switch ((env->cp15.c1_sys >> 8) & 3) { |
868 | b5ff1b31 | bellard | case 1: |
869 | b5ff1b31 | bellard | return is_user ? 0 : PAGE_READ; |
870 | b5ff1b31 | bellard | case 2: |
871 | b5ff1b31 | bellard | return PAGE_READ;
|
872 | b5ff1b31 | bellard | default:
|
873 | b5ff1b31 | bellard | return 0; |
874 | b5ff1b31 | bellard | } |
875 | b5ff1b31 | bellard | case 1: |
876 | b5ff1b31 | bellard | return is_user ? 0 : PAGE_READ | PAGE_WRITE; |
877 | b5ff1b31 | bellard | case 2: |
878 | b5ff1b31 | bellard | if (is_user)
|
879 | 9ee6e8bb | pbrook | return prot_ro;
|
880 | b5ff1b31 | bellard | else
|
881 | b5ff1b31 | bellard | return PAGE_READ | PAGE_WRITE;
|
882 | b5ff1b31 | bellard | case 3: |
883 | b5ff1b31 | bellard | return PAGE_READ | PAGE_WRITE;
|
884 | d4934d18 | pbrook | case 4: /* Reserved. */ |
885 | 9ee6e8bb | pbrook | return 0; |
886 | 9ee6e8bb | pbrook | case 5: |
887 | 9ee6e8bb | pbrook | return is_user ? 0 : prot_ro; |
888 | 9ee6e8bb | pbrook | case 6: |
889 | 9ee6e8bb | pbrook | return prot_ro;
|
890 | d4934d18 | pbrook | case 7: |
891 | d4934d18 | pbrook | if (!arm_feature (env, ARM_FEATURE_V7))
|
892 | d4934d18 | pbrook | return 0; |
893 | d4934d18 | pbrook | return prot_ro;
|
894 | b5ff1b31 | bellard | default:
|
895 | b5ff1b31 | bellard | abort(); |
896 | b5ff1b31 | bellard | } |
897 | b5ff1b31 | bellard | } |
898 | b5ff1b31 | bellard | |
899 | b2fa1797 | pbrook | static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
|
900 | b2fa1797 | pbrook | { |
901 | b2fa1797 | pbrook | uint32_t table; |
902 | b2fa1797 | pbrook | |
903 | b2fa1797 | pbrook | if (address & env->cp15.c2_mask)
|
904 | b2fa1797 | pbrook | table = env->cp15.c2_base1 & 0xffffc000;
|
905 | b2fa1797 | pbrook | else
|
906 | b2fa1797 | pbrook | table = env->cp15.c2_base0 & env->cp15.c2_base_mask; |
907 | b2fa1797 | pbrook | |
908 | b2fa1797 | pbrook | table |= (address >> 18) & 0x3ffc; |
909 | b2fa1797 | pbrook | return table;
|
910 | b2fa1797 | pbrook | } |
911 | b2fa1797 | pbrook | |
912 | 9ee6e8bb | pbrook | static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type, |
913 | d4c430a8 | Paul Brook | int is_user, uint32_t *phys_ptr, int *prot, |
914 | d4c430a8 | Paul Brook | target_ulong *page_size) |
915 | b5ff1b31 | bellard | { |
916 | b5ff1b31 | bellard | int code;
|
917 | b5ff1b31 | bellard | uint32_t table; |
918 | b5ff1b31 | bellard | uint32_t desc; |
919 | b5ff1b31 | bellard | int type;
|
920 | b5ff1b31 | bellard | int ap;
|
921 | b5ff1b31 | bellard | int domain;
|
922 | b5ff1b31 | bellard | uint32_t phys_addr; |
923 | b5ff1b31 | bellard | |
924 | 9ee6e8bb | pbrook | /* Pagetable walk. */
|
925 | 9ee6e8bb | pbrook | /* Lookup l1 descriptor. */
|
926 | b2fa1797 | pbrook | table = get_level1_table_address(env, address); |
927 | 9ee6e8bb | pbrook | desc = ldl_phys(table); |
928 | 9ee6e8bb | pbrook | type = (desc & 3);
|
929 | 9ee6e8bb | pbrook | domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3; |
930 | 9ee6e8bb | pbrook | if (type == 0) { |
931 | 601d70b9 | balrog | /* Section translation fault. */
|
932 | 9ee6e8bb | pbrook | code = 5;
|
933 | 9ee6e8bb | pbrook | goto do_fault;
|
934 | 9ee6e8bb | pbrook | } |
935 | 9ee6e8bb | pbrook | if (domain == 0 || domain == 2) { |
936 | 9ee6e8bb | pbrook | if (type == 2) |
937 | 9ee6e8bb | pbrook | code = 9; /* Section domain fault. */ |
938 | 9ee6e8bb | pbrook | else
|
939 | 9ee6e8bb | pbrook | code = 11; /* Page domain fault. */ |
940 | 9ee6e8bb | pbrook | goto do_fault;
|
941 | 9ee6e8bb | pbrook | } |
942 | 9ee6e8bb | pbrook | if (type == 2) { |
943 | 9ee6e8bb | pbrook | /* 1Mb section. */
|
944 | 9ee6e8bb | pbrook | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); |
945 | 9ee6e8bb | pbrook | ap = (desc >> 10) & 3; |
946 | 9ee6e8bb | pbrook | code = 13;
|
947 | d4c430a8 | Paul Brook | *page_size = 1024 * 1024; |
948 | 9ee6e8bb | pbrook | } else {
|
949 | 9ee6e8bb | pbrook | /* Lookup l2 entry. */
|
950 | 9ee6e8bb | pbrook | if (type == 1) { |
951 | 9ee6e8bb | pbrook | /* Coarse pagetable. */
|
952 | 9ee6e8bb | pbrook | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); |
953 | 9ee6e8bb | pbrook | } else {
|
954 | 9ee6e8bb | pbrook | /* Fine pagetable. */
|
955 | 9ee6e8bb | pbrook | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); |
956 | 9ee6e8bb | pbrook | } |
957 | 9ee6e8bb | pbrook | desc = ldl_phys(table); |
958 | 9ee6e8bb | pbrook | switch (desc & 3) { |
959 | 9ee6e8bb | pbrook | case 0: /* Page translation fault. */ |
960 | 9ee6e8bb | pbrook | code = 7;
|
961 | 9ee6e8bb | pbrook | goto do_fault;
|
962 | 9ee6e8bb | pbrook | case 1: /* 64k page. */ |
963 | 9ee6e8bb | pbrook | phys_addr = (desc & 0xffff0000) | (address & 0xffff); |
964 | 9ee6e8bb | pbrook | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; |
965 | d4c430a8 | Paul Brook | *page_size = 0x10000;
|
966 | ce819861 | pbrook | break;
|
967 | 9ee6e8bb | pbrook | case 2: /* 4k page. */ |
968 | 9ee6e8bb | pbrook | phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
969 | 9ee6e8bb | pbrook | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; |
970 | d4c430a8 | Paul Brook | *page_size = 0x1000;
|
971 | ce819861 | pbrook | break;
|
972 | 9ee6e8bb | pbrook | case 3: /* 1k page. */ |
973 | 9ee6e8bb | pbrook | if (type == 1) { |
974 | 9ee6e8bb | pbrook | if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
975 | 9ee6e8bb | pbrook | phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
976 | 9ee6e8bb | pbrook | } else {
|
977 | 9ee6e8bb | pbrook | /* Page translation fault. */
|
978 | 9ee6e8bb | pbrook | code = 7;
|
979 | 9ee6e8bb | pbrook | goto do_fault;
|
980 | 9ee6e8bb | pbrook | } |
981 | 9ee6e8bb | pbrook | } else {
|
982 | 9ee6e8bb | pbrook | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); |
983 | 9ee6e8bb | pbrook | } |
984 | 9ee6e8bb | pbrook | ap = (desc >> 4) & 3; |
985 | d4c430a8 | Paul Brook | *page_size = 0x400;
|
986 | ce819861 | pbrook | break;
|
987 | ce819861 | pbrook | default:
|
988 | 9ee6e8bb | pbrook | /* Never happens, but compiler isn't smart enough to tell. */
|
989 | 9ee6e8bb | pbrook | abort(); |
990 | ce819861 | pbrook | } |
991 | 9ee6e8bb | pbrook | code = 15;
|
992 | 9ee6e8bb | pbrook | } |
993 | 9ee6e8bb | pbrook | *prot = check_ap(env, ap, domain, access_type, is_user); |
994 | 9ee6e8bb | pbrook | if (!*prot) {
|
995 | 9ee6e8bb | pbrook | /* Access permission fault. */
|
996 | 9ee6e8bb | pbrook | goto do_fault;
|
997 | 9ee6e8bb | pbrook | } |
998 | 3ad493fc | Rabin Vincent | *prot |= PAGE_EXEC; |
999 | 9ee6e8bb | pbrook | *phys_ptr = phys_addr; |
1000 | 9ee6e8bb | pbrook | return 0; |
1001 | 9ee6e8bb | pbrook | do_fault:
|
1002 | 9ee6e8bb | pbrook | return code | (domain << 4); |
1003 | 9ee6e8bb | pbrook | } |
1004 | 9ee6e8bb | pbrook | |
1005 | 9ee6e8bb | pbrook | static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type, |
1006 | d4c430a8 | Paul Brook | int is_user, uint32_t *phys_ptr, int *prot, |
1007 | d4c430a8 | Paul Brook | target_ulong *page_size) |
1008 | 9ee6e8bb | pbrook | { |
1009 | 9ee6e8bb | pbrook | int code;
|
1010 | 9ee6e8bb | pbrook | uint32_t table; |
1011 | 9ee6e8bb | pbrook | uint32_t desc; |
1012 | 9ee6e8bb | pbrook | uint32_t xn; |
1013 | 9ee6e8bb | pbrook | int type;
|
1014 | 9ee6e8bb | pbrook | int ap;
|
1015 | 9ee6e8bb | pbrook | int domain;
|
1016 | 9ee6e8bb | pbrook | uint32_t phys_addr; |
1017 | 9ee6e8bb | pbrook | |
1018 | 9ee6e8bb | pbrook | /* Pagetable walk. */
|
1019 | 9ee6e8bb | pbrook | /* Lookup l1 descriptor. */
|
1020 | b2fa1797 | pbrook | table = get_level1_table_address(env, address); |
1021 | 9ee6e8bb | pbrook | desc = ldl_phys(table); |
1022 | 9ee6e8bb | pbrook | type = (desc & 3);
|
1023 | 9ee6e8bb | pbrook | if (type == 0) { |
1024 | 601d70b9 | balrog | /* Section translation fault. */
|
1025 | 9ee6e8bb | pbrook | code = 5;
|
1026 | 9ee6e8bb | pbrook | domain = 0;
|
1027 | 9ee6e8bb | pbrook | goto do_fault;
|
1028 | 9ee6e8bb | pbrook | } else if (type == 2 && (desc & (1 << 18))) { |
1029 | 9ee6e8bb | pbrook | /* Supersection. */
|
1030 | 9ee6e8bb | pbrook | domain = 0;
|
1031 | b5ff1b31 | bellard | } else {
|
1032 | 9ee6e8bb | pbrook | /* Section or page. */
|
1033 | 9ee6e8bb | pbrook | domain = (desc >> 4) & 0x1e; |
1034 | 9ee6e8bb | pbrook | } |
1035 | 9ee6e8bb | pbrook | domain = (env->cp15.c3 >> domain) & 3;
|
1036 | 9ee6e8bb | pbrook | if (domain == 0 || domain == 2) { |
1037 | 9ee6e8bb | pbrook | if (type == 2) |
1038 | 9ee6e8bb | pbrook | code = 9; /* Section domain fault. */ |
1039 | 9ee6e8bb | pbrook | else
|
1040 | 9ee6e8bb | pbrook | code = 11; /* Page domain fault. */ |
1041 | 9ee6e8bb | pbrook | goto do_fault;
|
1042 | 9ee6e8bb | pbrook | } |
1043 | 9ee6e8bb | pbrook | if (type == 2) { |
1044 | 9ee6e8bb | pbrook | if (desc & (1 << 18)) { |
1045 | 9ee6e8bb | pbrook | /* Supersection. */
|
1046 | 9ee6e8bb | pbrook | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); |
1047 | d4c430a8 | Paul Brook | *page_size = 0x1000000;
|
1048 | b5ff1b31 | bellard | } else {
|
1049 | 9ee6e8bb | pbrook | /* Section. */
|
1050 | 9ee6e8bb | pbrook | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); |
1051 | d4c430a8 | Paul Brook | *page_size = 0x100000;
|
1052 | b5ff1b31 | bellard | } |
1053 | 9ee6e8bb | pbrook | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
1054 | 9ee6e8bb | pbrook | xn = desc & (1 << 4); |
1055 | 9ee6e8bb | pbrook | code = 13;
|
1056 | 9ee6e8bb | pbrook | } else {
|
1057 | 9ee6e8bb | pbrook | /* Lookup l2 entry. */
|
1058 | 9ee6e8bb | pbrook | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); |
1059 | 9ee6e8bb | pbrook | desc = ldl_phys(table); |
1060 | 9ee6e8bb | pbrook | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
1061 | 9ee6e8bb | pbrook | switch (desc & 3) { |
1062 | 9ee6e8bb | pbrook | case 0: /* Page translation fault. */ |
1063 | 9ee6e8bb | pbrook | code = 7;
|
1064 | b5ff1b31 | bellard | goto do_fault;
|
1065 | 9ee6e8bb | pbrook | case 1: /* 64k page. */ |
1066 | 9ee6e8bb | pbrook | phys_addr = (desc & 0xffff0000) | (address & 0xffff); |
1067 | 9ee6e8bb | pbrook | xn = desc & (1 << 15); |
1068 | d4c430a8 | Paul Brook | *page_size = 0x10000;
|
1069 | 9ee6e8bb | pbrook | break;
|
1070 | 9ee6e8bb | pbrook | case 2: case 3: /* 4k page. */ |
1071 | 9ee6e8bb | pbrook | phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
1072 | 9ee6e8bb | pbrook | xn = desc & 1;
|
1073 | d4c430a8 | Paul Brook | *page_size = 0x1000;
|
1074 | 9ee6e8bb | pbrook | break;
|
1075 | 9ee6e8bb | pbrook | default:
|
1076 | 9ee6e8bb | pbrook | /* Never happens, but compiler isn't smart enough to tell. */
|
1077 | 9ee6e8bb | pbrook | abort(); |
1078 | b5ff1b31 | bellard | } |
1079 | 9ee6e8bb | pbrook | code = 15;
|
1080 | 9ee6e8bb | pbrook | } |
1081 | 9ee6e8bb | pbrook | if (xn && access_type == 2) |
1082 | 9ee6e8bb | pbrook | goto do_fault;
|
1083 | 9ee6e8bb | pbrook | |
1084 | d4934d18 | pbrook | /* The simplified model uses AP[0] as an access control bit. */
|
1085 | d4934d18 | pbrook | if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) { |
1086 | d4934d18 | pbrook | /* Access flag fault. */
|
1087 | d4934d18 | pbrook | code = (code == 15) ? 6 : 3; |
1088 | d4934d18 | pbrook | goto do_fault;
|
1089 | d4934d18 | pbrook | } |
1090 | 9ee6e8bb | pbrook | *prot = check_ap(env, ap, domain, access_type, is_user); |
1091 | 9ee6e8bb | pbrook | if (!*prot) {
|
1092 | 9ee6e8bb | pbrook | /* Access permission fault. */
|
1093 | 9ee6e8bb | pbrook | goto do_fault;
|
1094 | b5ff1b31 | bellard | } |
1095 | 3ad493fc | Rabin Vincent | if (!xn) {
|
1096 | 3ad493fc | Rabin Vincent | *prot |= PAGE_EXEC; |
1097 | 3ad493fc | Rabin Vincent | } |
1098 | 9ee6e8bb | pbrook | *phys_ptr = phys_addr; |
1099 | b5ff1b31 | bellard | return 0; |
1100 | b5ff1b31 | bellard | do_fault:
|
1101 | b5ff1b31 | bellard | return code | (domain << 4); |
1102 | b5ff1b31 | bellard | } |
1103 | b5ff1b31 | bellard | |
1104 | 9ee6e8bb | pbrook | static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type, |
1105 | 9ee6e8bb | pbrook | int is_user, uint32_t *phys_ptr, int *prot) |
1106 | 9ee6e8bb | pbrook | { |
1107 | 9ee6e8bb | pbrook | int n;
|
1108 | 9ee6e8bb | pbrook | uint32_t mask; |
1109 | 9ee6e8bb | pbrook | uint32_t base; |
1110 | 9ee6e8bb | pbrook | |
1111 | 9ee6e8bb | pbrook | *phys_ptr = address; |
1112 | 9ee6e8bb | pbrook | for (n = 7; n >= 0; n--) { |
1113 | 9ee6e8bb | pbrook | base = env->cp15.c6_region[n]; |
1114 | 9ee6e8bb | pbrook | if ((base & 1) == 0) |
1115 | 9ee6e8bb | pbrook | continue;
|
1116 | 9ee6e8bb | pbrook | mask = 1 << ((base >> 1) & 0x1f); |
1117 | 9ee6e8bb | pbrook | /* Keep this shift separate from the above to avoid an
|
1118 | 9ee6e8bb | pbrook | (undefined) << 32. */
|
1119 | 9ee6e8bb | pbrook | mask = (mask << 1) - 1; |
1120 | 9ee6e8bb | pbrook | if (((base ^ address) & ~mask) == 0) |
1121 | 9ee6e8bb | pbrook | break;
|
1122 | 9ee6e8bb | pbrook | } |
1123 | 9ee6e8bb | pbrook | if (n < 0) |
1124 | 9ee6e8bb | pbrook | return 2; |
1125 | 9ee6e8bb | pbrook | |
1126 | 9ee6e8bb | pbrook | if (access_type == 2) { |
1127 | 9ee6e8bb | pbrook | mask = env->cp15.c5_insn; |
1128 | 9ee6e8bb | pbrook | } else {
|
1129 | 9ee6e8bb | pbrook | mask = env->cp15.c5_data; |
1130 | 9ee6e8bb | pbrook | } |
1131 | 9ee6e8bb | pbrook | mask = (mask >> (n * 4)) & 0xf; |
1132 | 9ee6e8bb | pbrook | switch (mask) {
|
1133 | 9ee6e8bb | pbrook | case 0: |
1134 | 9ee6e8bb | pbrook | return 1; |
1135 | 9ee6e8bb | pbrook | case 1: |
1136 | 9ee6e8bb | pbrook | if (is_user)
|
1137 | 9ee6e8bb | pbrook | return 1; |
1138 | 9ee6e8bb | pbrook | *prot = PAGE_READ | PAGE_WRITE; |
1139 | 9ee6e8bb | pbrook | break;
|
1140 | 9ee6e8bb | pbrook | case 2: |
1141 | 9ee6e8bb | pbrook | *prot = PAGE_READ; |
1142 | 9ee6e8bb | pbrook | if (!is_user)
|
1143 | 9ee6e8bb | pbrook | *prot |= PAGE_WRITE; |
1144 | 9ee6e8bb | pbrook | break;
|
1145 | 9ee6e8bb | pbrook | case 3: |
1146 | 9ee6e8bb | pbrook | *prot = PAGE_READ | PAGE_WRITE; |
1147 | 9ee6e8bb | pbrook | break;
|
1148 | 9ee6e8bb | pbrook | case 5: |
1149 | 9ee6e8bb | pbrook | if (is_user)
|
1150 | 9ee6e8bb | pbrook | return 1; |
1151 | 9ee6e8bb | pbrook | *prot = PAGE_READ; |
1152 | 9ee6e8bb | pbrook | break;
|
1153 | 9ee6e8bb | pbrook | case 6: |
1154 | 9ee6e8bb | pbrook | *prot = PAGE_READ; |
1155 | 9ee6e8bb | pbrook | break;
|
1156 | 9ee6e8bb | pbrook | default:
|
1157 | 9ee6e8bb | pbrook | /* Bad permission. */
|
1158 | 9ee6e8bb | pbrook | return 1; |
1159 | 9ee6e8bb | pbrook | } |
1160 | 3ad493fc | Rabin Vincent | *prot |= PAGE_EXEC; |
1161 | 9ee6e8bb | pbrook | return 0; |
1162 | 9ee6e8bb | pbrook | } |
1163 | 9ee6e8bb | pbrook | |
1164 | 9ee6e8bb | pbrook | static inline int get_phys_addr(CPUState *env, uint32_t address, |
1165 | 9ee6e8bb | pbrook | int access_type, int is_user, |
1166 | d4c430a8 | Paul Brook | uint32_t *phys_ptr, int *prot,
|
1167 | d4c430a8 | Paul Brook | target_ulong *page_size) |
1168 | 9ee6e8bb | pbrook | { |
1169 | 9ee6e8bb | pbrook | /* Fast Context Switch Extension. */
|
1170 | 9ee6e8bb | pbrook | if (address < 0x02000000) |
1171 | 9ee6e8bb | pbrook | address += env->cp15.c13_fcse; |
1172 | 9ee6e8bb | pbrook | |
1173 | 9ee6e8bb | pbrook | if ((env->cp15.c1_sys & 1) == 0) { |
1174 | 9ee6e8bb | pbrook | /* MMU/MPU disabled. */
|
1175 | 9ee6e8bb | pbrook | *phys_ptr = address; |
1176 | 3ad493fc | Rabin Vincent | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
1177 | d4c430a8 | Paul Brook | *page_size = TARGET_PAGE_SIZE; |
1178 | 9ee6e8bb | pbrook | return 0; |
1179 | 9ee6e8bb | pbrook | } else if (arm_feature(env, ARM_FEATURE_MPU)) { |
1180 | d4c430a8 | Paul Brook | *page_size = TARGET_PAGE_SIZE; |
1181 | 9ee6e8bb | pbrook | return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
|
1182 | 9ee6e8bb | pbrook | prot); |
1183 | 9ee6e8bb | pbrook | } else if (env->cp15.c1_sys & (1 << 23)) { |
1184 | 9ee6e8bb | pbrook | return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
|
1185 | d4c430a8 | Paul Brook | prot, page_size); |
1186 | 9ee6e8bb | pbrook | } else {
|
1187 | 9ee6e8bb | pbrook | return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
|
1188 | d4c430a8 | Paul Brook | prot, page_size); |
1189 | 9ee6e8bb | pbrook | } |
1190 | 9ee6e8bb | pbrook | } |
1191 | 9ee6e8bb | pbrook | |
1192 | b5ff1b31 | bellard | int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
|
1193 | 6ebbf390 | j_mayer | int access_type, int mmu_idx, int is_softmmu) |
1194 | b5ff1b31 | bellard | { |
1195 | b5ff1b31 | bellard | uint32_t phys_addr; |
1196 | d4c430a8 | Paul Brook | target_ulong page_size; |
1197 | b5ff1b31 | bellard | int prot;
|
1198 | 6ebbf390 | j_mayer | int ret, is_user;
|
1199 | b5ff1b31 | bellard | |
1200 | 6ebbf390 | j_mayer | is_user = mmu_idx == MMU_USER_IDX; |
1201 | d4c430a8 | Paul Brook | ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot, |
1202 | d4c430a8 | Paul Brook | &page_size); |
1203 | b5ff1b31 | bellard | if (ret == 0) { |
1204 | b5ff1b31 | bellard | /* Map a single [sub]page. */
|
1205 | b5ff1b31 | bellard | phys_addr &= ~(uint32_t)0x3ff;
|
1206 | b5ff1b31 | bellard | address &= ~(uint32_t)0x3ff;
|
1207 | 3ad493fc | Rabin Vincent | tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size); |
1208 | d4c430a8 | Paul Brook | return 0; |
1209 | b5ff1b31 | bellard | } |
1210 | b5ff1b31 | bellard | |
1211 | b5ff1b31 | bellard | if (access_type == 2) { |
1212 | b5ff1b31 | bellard | env->cp15.c5_insn = ret; |
1213 | b5ff1b31 | bellard | env->cp15.c6_insn = address; |
1214 | b5ff1b31 | bellard | env->exception_index = EXCP_PREFETCH_ABORT; |
1215 | b5ff1b31 | bellard | } else {
|
1216 | b5ff1b31 | bellard | env->cp15.c5_data = ret; |
1217 | 9ee6e8bb | pbrook | if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) |
1218 | 9ee6e8bb | pbrook | env->cp15.c5_data |= (1 << 11); |
1219 | b5ff1b31 | bellard | env->cp15.c6_data = address; |
1220 | b5ff1b31 | bellard | env->exception_index = EXCP_DATA_ABORT; |
1221 | b5ff1b31 | bellard | } |
1222 | b5ff1b31 | bellard | return 1; |
1223 | b5ff1b31 | bellard | } |
1224 | b5ff1b31 | bellard | |
1225 | c227f099 | Anthony Liguori | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
1226 | b5ff1b31 | bellard | { |
1227 | b5ff1b31 | bellard | uint32_t phys_addr; |
1228 | d4c430a8 | Paul Brook | target_ulong page_size; |
1229 | b5ff1b31 | bellard | int prot;
|
1230 | b5ff1b31 | bellard | int ret;
|
1231 | b5ff1b31 | bellard | |
1232 | d4c430a8 | Paul Brook | ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size); |
1233 | b5ff1b31 | bellard | |
1234 | b5ff1b31 | bellard | if (ret != 0) |
1235 | b5ff1b31 | bellard | return -1; |
1236 | b5ff1b31 | bellard | |
1237 | b5ff1b31 | bellard | return phys_addr;
|
1238 | b5ff1b31 | bellard | } |
1239 | b5ff1b31 | bellard | |
1240 | 8984bd2e | pbrook | void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
|
1241 | c1713132 | balrog | { |
1242 | c1713132 | balrog | int cp_num = (insn >> 8) & 0xf; |
1243 | c1713132 | balrog | int cp_info = (insn >> 5) & 7; |
1244 | c1713132 | balrog | int src = (insn >> 16) & 0xf; |
1245 | c1713132 | balrog | int operand = insn & 0xf; |
1246 | c1713132 | balrog | |
1247 | c1713132 | balrog | if (env->cp[cp_num].cp_write)
|
1248 | c1713132 | balrog | env->cp[cp_num].cp_write(env->cp[cp_num].opaque, |
1249 | c1713132 | balrog | cp_info, src, operand, val); |
1250 | c1713132 | balrog | } |
1251 | c1713132 | balrog | |
1252 | 8984bd2e | pbrook | uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn) |
1253 | c1713132 | balrog | { |
1254 | c1713132 | balrog | int cp_num = (insn >> 8) & 0xf; |
1255 | c1713132 | balrog | int cp_info = (insn >> 5) & 7; |
1256 | c1713132 | balrog | int dest = (insn >> 16) & 0xf; |
1257 | c1713132 | balrog | int operand = insn & 0xf; |
1258 | c1713132 | balrog | |
1259 | c1713132 | balrog | if (env->cp[cp_num].cp_read)
|
1260 | c1713132 | balrog | return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
|
1261 | c1713132 | balrog | cp_info, dest, operand); |
1262 | c1713132 | balrog | return 0; |
1263 | c1713132 | balrog | } |
1264 | c1713132 | balrog | |
1265 | ce819861 | pbrook | /* Return basic MPU access permission bits. */
|
1266 | ce819861 | pbrook | static uint32_t simple_mpu_ap_bits(uint32_t val)
|
1267 | ce819861 | pbrook | { |
1268 | ce819861 | pbrook | uint32_t ret; |
1269 | ce819861 | pbrook | uint32_t mask; |
1270 | ce819861 | pbrook | int i;
|
1271 | ce819861 | pbrook | ret = 0;
|
1272 | ce819861 | pbrook | mask = 3;
|
1273 | ce819861 | pbrook | for (i = 0; i < 16; i += 2) { |
1274 | ce819861 | pbrook | ret |= (val >> i) & mask; |
1275 | ce819861 | pbrook | mask <<= 2;
|
1276 | ce819861 | pbrook | } |
1277 | ce819861 | pbrook | return ret;
|
1278 | ce819861 | pbrook | } |
1279 | ce819861 | pbrook | |
1280 | ce819861 | pbrook | /* Pad basic MPU access permission bits to extended format. */
|
1281 | ce819861 | pbrook | static uint32_t extended_mpu_ap_bits(uint32_t val)
|
1282 | ce819861 | pbrook | { |
1283 | ce819861 | pbrook | uint32_t ret; |
1284 | ce819861 | pbrook | uint32_t mask; |
1285 | ce819861 | pbrook | int i;
|
1286 | ce819861 | pbrook | ret = 0;
|
1287 | ce819861 | pbrook | mask = 3;
|
1288 | ce819861 | pbrook | for (i = 0; i < 16; i += 2) { |
1289 | ce819861 | pbrook | ret |= (val & mask) << i; |
1290 | ce819861 | pbrook | mask <<= 2;
|
1291 | ce819861 | pbrook | } |
1292 | ce819861 | pbrook | return ret;
|
1293 | ce819861 | pbrook | } |
1294 | ce819861 | pbrook | |
1295 | 8984bd2e | pbrook | void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
|
1296 | b5ff1b31 | bellard | { |
1297 | 9ee6e8bb | pbrook | int op1;
|
1298 | 9ee6e8bb | pbrook | int op2;
|
1299 | 9ee6e8bb | pbrook | int crm;
|
1300 | b5ff1b31 | bellard | |
1301 | 9ee6e8bb | pbrook | op1 = (insn >> 21) & 7; |
1302 | b5ff1b31 | bellard | op2 = (insn >> 5) & 7; |
1303 | ce819861 | pbrook | crm = insn & 0xf;
|
1304 | b5ff1b31 | bellard | switch ((insn >> 16) & 0xf) { |
1305 | 9ee6e8bb | pbrook | case 0: |
1306 | 9ee6e8bb | pbrook | /* ID codes. */
|
1307 | 610c3c8a | balrog | if (arm_feature(env, ARM_FEATURE_XSCALE))
|
1308 | 610c3c8a | balrog | break;
|
1309 | c3d2689d | balrog | if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1310 | c3d2689d | balrog | break;
|
1311 | a49ea279 | pbrook | if (arm_feature(env, ARM_FEATURE_V7)
|
1312 | a49ea279 | pbrook | && op1 == 2 && crm == 0 && op2 == 0) { |
1313 | a49ea279 | pbrook | env->cp15.c0_cssel = val & 0xf;
|
1314 | a49ea279 | pbrook | break;
|
1315 | a49ea279 | pbrook | } |
1316 | b5ff1b31 | bellard | goto bad_reg;
|
1317 | b5ff1b31 | bellard | case 1: /* System configuration. */ |
1318 | c3d2689d | balrog | if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1319 | c3d2689d | balrog | op2 = 0;
|
1320 | b5ff1b31 | bellard | switch (op2) {
|
1321 | b5ff1b31 | bellard | case 0: |
1322 | ce819861 | pbrook | if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0) |
1323 | c1713132 | balrog | env->cp15.c1_sys = val; |
1324 | b5ff1b31 | bellard | /* ??? Lots of these bits are not implemented. */
|
1325 | b5ff1b31 | bellard | /* This may enable/disable the MMU, so do a TLB flush. */
|
1326 | b5ff1b31 | bellard | tlb_flush(env, 1);
|
1327 | b5ff1b31 | bellard | break;
|
1328 | 9ee6e8bb | pbrook | case 1: /* Auxiliary cotrol register. */ |
1329 | 610c3c8a | balrog | if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
1330 | 610c3c8a | balrog | env->cp15.c1_xscaleauxcr = val; |
1331 | c1713132 | balrog | break;
|
1332 | 610c3c8a | balrog | } |
1333 | 9ee6e8bb | pbrook | /* Not implemented. */
|
1334 | 9ee6e8bb | pbrook | break;
|
1335 | b5ff1b31 | bellard | case 2: |
1336 | 610c3c8a | balrog | if (arm_feature(env, ARM_FEATURE_XSCALE))
|
1337 | 610c3c8a | balrog | goto bad_reg;
|
1338 | 4be27dbb | pbrook | if (env->cp15.c1_coproc != val) {
|
1339 | 4be27dbb | pbrook | env->cp15.c1_coproc = val; |
1340 | 4be27dbb | pbrook | /* ??? Is this safe when called from within a TB? */
|
1341 | 4be27dbb | pbrook | tb_flush(env); |
1342 | 4be27dbb | pbrook | } |
1343 | c1713132 | balrog | break;
|
1344 | b5ff1b31 | bellard | default:
|
1345 | b5ff1b31 | bellard | goto bad_reg;
|
1346 | b5ff1b31 | bellard | } |
1347 | b5ff1b31 | bellard | break;
|
1348 | ce819861 | pbrook | case 2: /* MMU Page table control / MPU cache control. */ |
1349 | ce819861 | pbrook | if (arm_feature(env, ARM_FEATURE_MPU)) {
|
1350 | ce819861 | pbrook | switch (op2) {
|
1351 | ce819861 | pbrook | case 0: |
1352 | ce819861 | pbrook | env->cp15.c2_data = val; |
1353 | ce819861 | pbrook | break;
|
1354 | ce819861 | pbrook | case 1: |
1355 | ce819861 | pbrook | env->cp15.c2_insn = val; |
1356 | ce819861 | pbrook | break;
|
1357 | ce819861 | pbrook | default:
|
1358 | ce819861 | pbrook | goto bad_reg;
|
1359 | ce819861 | pbrook | } |
1360 | ce819861 | pbrook | } else {
|
1361 | 9ee6e8bb | pbrook | switch (op2) {
|
1362 | 9ee6e8bb | pbrook | case 0: |
1363 | 9ee6e8bb | pbrook | env->cp15.c2_base0 = val; |
1364 | 9ee6e8bb | pbrook | break;
|
1365 | 9ee6e8bb | pbrook | case 1: |
1366 | 9ee6e8bb | pbrook | env->cp15.c2_base1 = val; |
1367 | 9ee6e8bb | pbrook | break;
|
1368 | 9ee6e8bb | pbrook | case 2: |
1369 | b2fa1797 | pbrook | val &= 7;
|
1370 | b2fa1797 | pbrook | env->cp15.c2_control = val; |
1371 | 9ee6e8bb | pbrook | env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
|
1372 | b2fa1797 | pbrook | env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
|
1373 | 9ee6e8bb | pbrook | break;
|
1374 | 9ee6e8bb | pbrook | default:
|
1375 | 9ee6e8bb | pbrook | goto bad_reg;
|
1376 | 9ee6e8bb | pbrook | } |
1377 | ce819861 | pbrook | } |
1378 | b5ff1b31 | bellard | break;
|
1379 | ce819861 | pbrook | case 3: /* MMU Domain access control / MPU write buffer control. */ |
1380 | b5ff1b31 | bellard | env->cp15.c3 = val; |
1381 | 405ee3ad | balrog | tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ |
1382 | b5ff1b31 | bellard | break;
|
1383 | b5ff1b31 | bellard | case 4: /* Reserved. */ |
1384 | b5ff1b31 | bellard | goto bad_reg;
|
1385 | ce819861 | pbrook | case 5: /* MMU Fault status / MPU access permission. */ |
1386 | c3d2689d | balrog | if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1387 | c3d2689d | balrog | op2 = 0;
|
1388 | b5ff1b31 | bellard | switch (op2) {
|
1389 | b5ff1b31 | bellard | case 0: |
1390 | ce819861 | pbrook | if (arm_feature(env, ARM_FEATURE_MPU))
|
1391 | ce819861 | pbrook | val = extended_mpu_ap_bits(val); |
1392 | b5ff1b31 | bellard | env->cp15.c5_data = val; |
1393 | b5ff1b31 | bellard | break;
|
1394 | b5ff1b31 | bellard | case 1: |
1395 | ce819861 | pbrook | if (arm_feature(env, ARM_FEATURE_MPU))
|
1396 | ce819861 | pbrook | val = extended_mpu_ap_bits(val); |
1397 | b5ff1b31 | bellard | env->cp15.c5_insn = val; |
1398 | b5ff1b31 | bellard | break;
|
1399 | ce819861 | pbrook | case 2: |
1400 | ce819861 | pbrook | if (!arm_feature(env, ARM_FEATURE_MPU))
|
1401 | ce819861 | pbrook | goto bad_reg;
|
1402 | ce819861 | pbrook | env->cp15.c5_data = val; |
1403 | b5ff1b31 | bellard | break;
|
1404 | ce819861 | pbrook | case 3: |
1405 | ce819861 | pbrook | if (!arm_feature(env, ARM_FEATURE_MPU))
|
1406 | ce819861 | pbrook | goto bad_reg;
|
1407 | ce819861 | pbrook | env->cp15.c5_insn = val; |
1408 | b5ff1b31 | bellard | break;
|
1409 | b5ff1b31 | bellard | default:
|
1410 | b5ff1b31 | bellard | goto bad_reg;
|
1411 | b5ff1b31 | bellard | } |
1412 | b5ff1b31 | bellard | break;
|
1413 | ce819861 | pbrook | case 6: /* MMU Fault address / MPU base/size. */ |
1414 | ce819861 | pbrook | if (arm_feature(env, ARM_FEATURE_MPU)) {
|
1415 | ce819861 | pbrook | if (crm >= 8) |
1416 | ce819861 | pbrook | goto bad_reg;
|
1417 | ce819861 | pbrook | env->cp15.c6_region[crm] = val; |
1418 | ce819861 | pbrook | } else {
|
1419 | c3d2689d | balrog | if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1420 | c3d2689d | balrog | op2 = 0;
|
1421 | ce819861 | pbrook | switch (op2) {
|
1422 | ce819861 | pbrook | case 0: |
1423 | ce819861 | pbrook | env->cp15.c6_data = val; |
1424 | ce819861 | pbrook | break;
|
1425 | 9ee6e8bb | pbrook | case 1: /* ??? This is WFAR on armv6 */ |
1426 | 9ee6e8bb | pbrook | case 2: |
1427 | ce819861 | pbrook | env->cp15.c6_insn = val; |
1428 | ce819861 | pbrook | break;
|
1429 | ce819861 | pbrook | default:
|
1430 | ce819861 | pbrook | goto bad_reg;
|
1431 | ce819861 | pbrook | } |
1432 | ce819861 | pbrook | } |
1433 | ce819861 | pbrook | break;
|
1434 | b5ff1b31 | bellard | case 7: /* Cache control. */ |
1435 | c3d2689d | balrog | env->cp15.c15_i_max = 0x000;
|
1436 | c3d2689d | balrog | env->cp15.c15_i_min = 0xff0;
|
1437 | b5ff1b31 | bellard | /* No cache, so nothing to do. */
|
1438 | 9ee6e8bb | pbrook | /* ??? MPCore has VA to PA translation functions. */
|
1439 | b5ff1b31 | bellard | break;
|
1440 | b5ff1b31 | bellard | case 8: /* MMU TLB control. */ |
1441 | b5ff1b31 | bellard | switch (op2) {
|
1442 | b5ff1b31 | bellard | case 0: /* Invalidate all. */ |
1443 | b5ff1b31 | bellard | tlb_flush(env, 0);
|
1444 | b5ff1b31 | bellard | break;
|
1445 | b5ff1b31 | bellard | case 1: /* Invalidate single TLB entry. */ |
1446 | d4c430a8 | Paul Brook | tlb_flush_page(env, val & TARGET_PAGE_MASK); |
1447 | b5ff1b31 | bellard | break;
|
1448 | 9ee6e8bb | pbrook | case 2: /* Invalidate on ASID. */ |
1449 | 9ee6e8bb | pbrook | tlb_flush(env, val == 0);
|
1450 | 9ee6e8bb | pbrook | break;
|
1451 | 9ee6e8bb | pbrook | case 3: /* Invalidate single entry on MVA. */ |
1452 | 9ee6e8bb | pbrook | /* ??? This is like case 1, but ignores ASID. */
|
1453 | 9ee6e8bb | pbrook | tlb_flush(env, 1);
|
1454 | 9ee6e8bb | pbrook | break;
|
1455 | b5ff1b31 | bellard | default:
|
1456 | b5ff1b31 | bellard | goto bad_reg;
|
1457 | b5ff1b31 | bellard | } |
1458 | b5ff1b31 | bellard | break;
|
1459 | ce819861 | pbrook | case 9: |
1460 | c3d2689d | balrog | if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1461 | c3d2689d | balrog | break;
|
1462 | ce819861 | pbrook | switch (crm) {
|
1463 | ce819861 | pbrook | case 0: /* Cache lockdown. */ |
1464 | 9ee6e8bb | pbrook | switch (op1) {
|
1465 | 9ee6e8bb | pbrook | case 0: /* L1 cache. */ |
1466 | 9ee6e8bb | pbrook | switch (op2) {
|
1467 | 9ee6e8bb | pbrook | case 0: |
1468 | 9ee6e8bb | pbrook | env->cp15.c9_data = val; |
1469 | 9ee6e8bb | pbrook | break;
|
1470 | 9ee6e8bb | pbrook | case 1: |
1471 | 9ee6e8bb | pbrook | env->cp15.c9_insn = val; |
1472 | 9ee6e8bb | pbrook | break;
|
1473 | 9ee6e8bb | pbrook | default:
|
1474 | 9ee6e8bb | pbrook | goto bad_reg;
|
1475 | 9ee6e8bb | pbrook | } |
1476 | 9ee6e8bb | pbrook | break;
|
1477 | 9ee6e8bb | pbrook | case 1: /* L2 cache. */ |
1478 | 9ee6e8bb | pbrook | /* Ignore writes to L2 lockdown/auxiliary registers. */
|
1479 | 9ee6e8bb | pbrook | break;
|
1480 | 9ee6e8bb | pbrook | default:
|
1481 | 9ee6e8bb | pbrook | goto bad_reg;
|
1482 | 9ee6e8bb | pbrook | } |
1483 | 9ee6e8bb | pbrook | break;
|
1484 | ce819861 | pbrook | case 1: /* TCM memory region registers. */ |
1485 | ce819861 | pbrook | /* Not implemented. */
|
1486 | ce819861 | pbrook | goto bad_reg;
|
1487 | b5ff1b31 | bellard | default:
|
1488 | b5ff1b31 | bellard | goto bad_reg;
|
1489 | b5ff1b31 | bellard | } |
1490 | b5ff1b31 | bellard | break;
|
1491 | b5ff1b31 | bellard | case 10: /* MMU TLB lockdown. */ |
1492 | b5ff1b31 | bellard | /* ??? TLB lockdown not implemented. */
|
1493 | b5ff1b31 | bellard | break;
|
1494 | b5ff1b31 | bellard | case 12: /* Reserved. */ |
1495 | b5ff1b31 | bellard | goto bad_reg;
|
1496 | b5ff1b31 | bellard | case 13: /* Process ID. */ |
1497 | b5ff1b31 | bellard | switch (op2) {
|
1498 | b5ff1b31 | bellard | case 0: |
1499 | d07edbfa | pbrook | /* Unlike real hardware the qemu TLB uses virtual addresses,
|
1500 | d07edbfa | pbrook | not modified virtual addresses, so this causes a TLB flush.
|
1501 | d07edbfa | pbrook | */
|
1502 | d07edbfa | pbrook | if (env->cp15.c13_fcse != val)
|
1503 | d07edbfa | pbrook | tlb_flush(env, 1);
|
1504 | d07edbfa | pbrook | env->cp15.c13_fcse = val; |
1505 | b5ff1b31 | bellard | break;
|
1506 | b5ff1b31 | bellard | case 1: |
1507 | d07edbfa | pbrook | /* This changes the ASID, so do a TLB flush. */
|
1508 | ce819861 | pbrook | if (env->cp15.c13_context != val
|
1509 | ce819861 | pbrook | && !arm_feature(env, ARM_FEATURE_MPU)) |
1510 | d07edbfa | pbrook | tlb_flush(env, 0);
|
1511 | d07edbfa | pbrook | env->cp15.c13_context = val; |
1512 | b5ff1b31 | bellard | break;
|
1513 | b5ff1b31 | bellard | default:
|
1514 | b5ff1b31 | bellard | goto bad_reg;
|
1515 | b5ff1b31 | bellard | } |
1516 | b5ff1b31 | bellard | break;
|
1517 | b5ff1b31 | bellard | case 14: /* Reserved. */ |
1518 | b5ff1b31 | bellard | goto bad_reg;
|
1519 | b5ff1b31 | bellard | case 15: /* Implementation specific. */ |
1520 | c1713132 | balrog | if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
1521 | ce819861 | pbrook | if (op2 == 0 && crm == 1) { |
1522 | 2e23213f | balrog | if (env->cp15.c15_cpar != (val & 0x3fff)) { |
1523 | 2e23213f | balrog | /* Changes cp0 to cp13 behavior, so needs a TB flush. */
|
1524 | 2e23213f | balrog | tb_flush(env); |
1525 | 2e23213f | balrog | env->cp15.c15_cpar = val & 0x3fff;
|
1526 | 2e23213f | balrog | } |
1527 | c1713132 | balrog | break;
|
1528 | c1713132 | balrog | } |
1529 | c1713132 | balrog | goto bad_reg;
|
1530 | c1713132 | balrog | } |
1531 | c3d2689d | balrog | if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
|
1532 | c3d2689d | balrog | switch (crm) {
|
1533 | c3d2689d | balrog | case 0: |
1534 | c3d2689d | balrog | break;
|
1535 | c3d2689d | balrog | case 1: /* Set TI925T configuration. */ |
1536 | c3d2689d | balrog | env->cp15.c15_ticonfig = val & 0xe7;
|
1537 | c3d2689d | balrog | env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */ |
1538 | c3d2689d | balrog | ARM_CPUID_TI915T : ARM_CPUID_TI925T; |
1539 | c3d2689d | balrog | break;
|
1540 | c3d2689d | balrog | case 2: /* Set I_max. */ |
1541 | c3d2689d | balrog | env->cp15.c15_i_max = val; |
1542 | c3d2689d | balrog | break;
|
1543 | c3d2689d | balrog | case 3: /* Set I_min. */ |
1544 | c3d2689d | balrog | env->cp15.c15_i_min = val; |
1545 | c3d2689d | balrog | break;
|
1546 | c3d2689d | balrog | case 4: /* Set thread-ID. */ |
1547 | c3d2689d | balrog | env->cp15.c15_threadid = val & 0xffff;
|
1548 | c3d2689d | balrog | break;
|
1549 | c3d2689d | balrog | case 8: /* Wait-for-interrupt (deprecated). */ |
1550 | c3d2689d | balrog | cpu_interrupt(env, CPU_INTERRUPT_HALT); |
1551 | c3d2689d | balrog | break;
|
1552 | c3d2689d | balrog | default:
|
1553 | c3d2689d | balrog | goto bad_reg;
|
1554 | c3d2689d | balrog | } |
1555 | c3d2689d | balrog | } |
1556 | b5ff1b31 | bellard | break;
|
1557 | b5ff1b31 | bellard | } |
1558 | b5ff1b31 | bellard | return;
|
1559 | b5ff1b31 | bellard | bad_reg:
|
1560 | b5ff1b31 | bellard | /* ??? For debugging only. Should raise illegal instruction exception. */
|
1561 | 9ee6e8bb | pbrook | cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
|
1562 | 9ee6e8bb | pbrook | (insn >> 16) & 0xf, crm, op1, op2); |
1563 | b5ff1b31 | bellard | } |
1564 | b5ff1b31 | bellard | |
1565 | 8984bd2e | pbrook | uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) |
1566 | b5ff1b31 | bellard | { |
1567 | 9ee6e8bb | pbrook | int op1;
|
1568 | 9ee6e8bb | pbrook | int op2;
|
1569 | 9ee6e8bb | pbrook | int crm;
|
1570 | b5ff1b31 | bellard | |
1571 | 9ee6e8bb | pbrook | op1 = (insn >> 21) & 7; |
1572 | b5ff1b31 | bellard | op2 = (insn >> 5) & 7; |
1573 | c3d2689d | balrog | crm = insn & 0xf;
|
1574 | b5ff1b31 | bellard | switch ((insn >> 16) & 0xf) { |
1575 | b5ff1b31 | bellard | case 0: /* ID codes. */ |
1576 | 9ee6e8bb | pbrook | switch (op1) {
|
1577 | 9ee6e8bb | pbrook | case 0: |
1578 | 9ee6e8bb | pbrook | switch (crm) {
|
1579 | 9ee6e8bb | pbrook | case 0: |
1580 | 9ee6e8bb | pbrook | switch (op2) {
|
1581 | 9ee6e8bb | pbrook | case 0: /* Device ID. */ |
1582 | 9ee6e8bb | pbrook | return env->cp15.c0_cpuid;
|
1583 | 9ee6e8bb | pbrook | case 1: /* Cache Type. */ |
1584 | 9ee6e8bb | pbrook | return env->cp15.c0_cachetype;
|
1585 | 9ee6e8bb | pbrook | case 2: /* TCM status. */ |
1586 | 9ee6e8bb | pbrook | return 0; |
1587 | 9ee6e8bb | pbrook | case 3: /* TLB type register. */ |
1588 | 9ee6e8bb | pbrook | return 0; /* No lockable TLB entries. */ |
1589 | 9ee6e8bb | pbrook | case 5: /* CPU ID */ |
1590 | 10055562 | Paul Brook | if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
|
1591 | 10055562 | Paul Brook | return env->cpu_index | 0x80000900; |
1592 | 10055562 | Paul Brook | } else {
|
1593 | 10055562 | Paul Brook | return env->cpu_index;
|
1594 | 10055562 | Paul Brook | } |
1595 | 9ee6e8bb | pbrook | default:
|
1596 | 9ee6e8bb | pbrook | goto bad_reg;
|
1597 | 9ee6e8bb | pbrook | } |
1598 | 9ee6e8bb | pbrook | case 1: |
1599 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_V6))
|
1600 | 9ee6e8bb | pbrook | goto bad_reg;
|
1601 | 9ee6e8bb | pbrook | return env->cp15.c0_c1[op2];
|
1602 | 9ee6e8bb | pbrook | case 2: |
1603 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_V6))
|
1604 | 9ee6e8bb | pbrook | goto bad_reg;
|
1605 | 9ee6e8bb | pbrook | return env->cp15.c0_c2[op2];
|
1606 | 9ee6e8bb | pbrook | case 3: case 4: case 5: case 6: case 7: |
1607 | 9ee6e8bb | pbrook | return 0; |
1608 | 9ee6e8bb | pbrook | default:
|
1609 | 9ee6e8bb | pbrook | goto bad_reg;
|
1610 | 9ee6e8bb | pbrook | } |
1611 | 9ee6e8bb | pbrook | case 1: |
1612 | 9ee6e8bb | pbrook | /* These registers aren't documented on arm11 cores. However
|
1613 | 9ee6e8bb | pbrook | Linux looks at them anyway. */
|
1614 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_V6))
|
1615 | 9ee6e8bb | pbrook | goto bad_reg;
|
1616 | 9ee6e8bb | pbrook | if (crm != 0) |
1617 | 9ee6e8bb | pbrook | goto bad_reg;
|
1618 | a49ea279 | pbrook | if (!arm_feature(env, ARM_FEATURE_V7))
|
1619 | a49ea279 | pbrook | return 0; |
1620 | a49ea279 | pbrook | |
1621 | a49ea279 | pbrook | switch (op2) {
|
1622 | a49ea279 | pbrook | case 0: |
1623 | a49ea279 | pbrook | return env->cp15.c0_ccsid[env->cp15.c0_cssel];
|
1624 | a49ea279 | pbrook | case 1: |
1625 | a49ea279 | pbrook | return env->cp15.c0_clid;
|
1626 | a49ea279 | pbrook | case 7: |
1627 | a49ea279 | pbrook | return 0; |
1628 | a49ea279 | pbrook | } |
1629 | a49ea279 | pbrook | goto bad_reg;
|
1630 | a49ea279 | pbrook | case 2: |
1631 | a49ea279 | pbrook | if (op2 != 0 || crm != 0) |
1632 | 610c3c8a | balrog | goto bad_reg;
|
1633 | a49ea279 | pbrook | return env->cp15.c0_cssel;
|
1634 | 9ee6e8bb | pbrook | default:
|
1635 | 9ee6e8bb | pbrook | goto bad_reg;
|
1636 | b5ff1b31 | bellard | } |
1637 | b5ff1b31 | bellard | case 1: /* System configuration. */ |
1638 | c3d2689d | balrog | if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1639 | c3d2689d | balrog | op2 = 0;
|
1640 | b5ff1b31 | bellard | switch (op2) {
|
1641 | b5ff1b31 | bellard | case 0: /* Control register. */ |
1642 | b5ff1b31 | bellard | return env->cp15.c1_sys;
|
1643 | b5ff1b31 | bellard | case 1: /* Auxiliary control register. */ |
1644 | c1713132 | balrog | if (arm_feature(env, ARM_FEATURE_XSCALE))
|
1645 | 610c3c8a | balrog | return env->cp15.c1_xscaleauxcr;
|
1646 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_AUXCR))
|
1647 | 9ee6e8bb | pbrook | goto bad_reg;
|
1648 | 9ee6e8bb | pbrook | switch (ARM_CPUID(env)) {
|
1649 | 9ee6e8bb | pbrook | case ARM_CPUID_ARM1026:
|
1650 | 9ee6e8bb | pbrook | return 1; |
1651 | 9ee6e8bb | pbrook | case ARM_CPUID_ARM1136:
|
1652 | 827df9f3 | balrog | case ARM_CPUID_ARM1136_R2:
|
1653 | 9ee6e8bb | pbrook | return 7; |
1654 | 9ee6e8bb | pbrook | case ARM_CPUID_ARM11MPCORE:
|
1655 | 9ee6e8bb | pbrook | return 1; |
1656 | 9ee6e8bb | pbrook | case ARM_CPUID_CORTEXA8:
|
1657 | 533d177a | aurel32 | return 2; |
1658 | 10055562 | Paul Brook | case ARM_CPUID_CORTEXA9:
|
1659 | 10055562 | Paul Brook | return 0; |
1660 | 9ee6e8bb | pbrook | default:
|
1661 | 9ee6e8bb | pbrook | goto bad_reg;
|
1662 | 9ee6e8bb | pbrook | } |
1663 | b5ff1b31 | bellard | case 2: /* Coprocessor access register. */ |
1664 | 610c3c8a | balrog | if (arm_feature(env, ARM_FEATURE_XSCALE))
|
1665 | 610c3c8a | balrog | goto bad_reg;
|
1666 | b5ff1b31 | bellard | return env->cp15.c1_coproc;
|
1667 | b5ff1b31 | bellard | default:
|
1668 | b5ff1b31 | bellard | goto bad_reg;
|
1669 | b5ff1b31 | bellard | } |
1670 | ce819861 | pbrook | case 2: /* MMU Page table control / MPU cache control. */ |
1671 | ce819861 | pbrook | if (arm_feature(env, ARM_FEATURE_MPU)) {
|
1672 | ce819861 | pbrook | switch (op2) {
|
1673 | ce819861 | pbrook | case 0: |
1674 | ce819861 | pbrook | return env->cp15.c2_data;
|
1675 | ce819861 | pbrook | break;
|
1676 | ce819861 | pbrook | case 1: |
1677 | ce819861 | pbrook | return env->cp15.c2_insn;
|
1678 | ce819861 | pbrook | break;
|
1679 | ce819861 | pbrook | default:
|
1680 | ce819861 | pbrook | goto bad_reg;
|
1681 | ce819861 | pbrook | } |
1682 | ce819861 | pbrook | } else {
|
1683 | 9ee6e8bb | pbrook | switch (op2) {
|
1684 | 9ee6e8bb | pbrook | case 0: |
1685 | 9ee6e8bb | pbrook | return env->cp15.c2_base0;
|
1686 | 9ee6e8bb | pbrook | case 1: |
1687 | 9ee6e8bb | pbrook | return env->cp15.c2_base1;
|
1688 | 9ee6e8bb | pbrook | case 2: |
1689 | b2fa1797 | pbrook | return env->cp15.c2_control;
|
1690 | 9ee6e8bb | pbrook | default:
|
1691 | 9ee6e8bb | pbrook | goto bad_reg;
|
1692 | 9ee6e8bb | pbrook | } |
1693 | 9ee6e8bb | pbrook | } |
1694 | ce819861 | pbrook | case 3: /* MMU Domain access control / MPU write buffer control. */ |
1695 | b5ff1b31 | bellard | return env->cp15.c3;
|
1696 | b5ff1b31 | bellard | case 4: /* Reserved. */ |
1697 | b5ff1b31 | bellard | goto bad_reg;
|
1698 | ce819861 | pbrook | case 5: /* MMU Fault status / MPU access permission. */ |
1699 | c3d2689d | balrog | if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1700 | c3d2689d | balrog | op2 = 0;
|
1701 | b5ff1b31 | bellard | switch (op2) {
|
1702 | b5ff1b31 | bellard | case 0: |
1703 | ce819861 | pbrook | if (arm_feature(env, ARM_FEATURE_MPU))
|
1704 | ce819861 | pbrook | return simple_mpu_ap_bits(env->cp15.c5_data);
|
1705 | b5ff1b31 | bellard | return env->cp15.c5_data;
|
1706 | b5ff1b31 | bellard | case 1: |
1707 | ce819861 | pbrook | if (arm_feature(env, ARM_FEATURE_MPU))
|
1708 | ce819861 | pbrook | return simple_mpu_ap_bits(env->cp15.c5_data);
|
1709 | ce819861 | pbrook | return env->cp15.c5_insn;
|
1710 | ce819861 | pbrook | case 2: |
1711 | ce819861 | pbrook | if (!arm_feature(env, ARM_FEATURE_MPU))
|
1712 | ce819861 | pbrook | goto bad_reg;
|
1713 | ce819861 | pbrook | return env->cp15.c5_data;
|
1714 | ce819861 | pbrook | case 3: |
1715 | ce819861 | pbrook | if (!arm_feature(env, ARM_FEATURE_MPU))
|
1716 | ce819861 | pbrook | goto bad_reg;
|
1717 | b5ff1b31 | bellard | return env->cp15.c5_insn;
|
1718 | b5ff1b31 | bellard | default:
|
1719 | b5ff1b31 | bellard | goto bad_reg;
|
1720 | b5ff1b31 | bellard | } |
1721 | 9ee6e8bb | pbrook | case 6: /* MMU Fault address. */ |
1722 | ce819861 | pbrook | if (arm_feature(env, ARM_FEATURE_MPU)) {
|
1723 | 9ee6e8bb | pbrook | if (crm >= 8) |
1724 | ce819861 | pbrook | goto bad_reg;
|
1725 | 9ee6e8bb | pbrook | return env->cp15.c6_region[crm];
|
1726 | ce819861 | pbrook | } else {
|
1727 | c3d2689d | balrog | if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1728 | c3d2689d | balrog | op2 = 0;
|
1729 | 9ee6e8bb | pbrook | switch (op2) {
|
1730 | 9ee6e8bb | pbrook | case 0: |
1731 | 9ee6e8bb | pbrook | return env->cp15.c6_data;
|
1732 | 9ee6e8bb | pbrook | case 1: |
1733 | 9ee6e8bb | pbrook | if (arm_feature(env, ARM_FEATURE_V6)) {
|
1734 | 9ee6e8bb | pbrook | /* Watchpoint Fault Adrress. */
|
1735 | 9ee6e8bb | pbrook | return 0; /* Not implemented. */ |
1736 | 9ee6e8bb | pbrook | } else {
|
1737 | 9ee6e8bb | pbrook | /* Instruction Fault Adrress. */
|
1738 | 9ee6e8bb | pbrook | /* Arm9 doesn't have an IFAR, but implementing it anyway
|
1739 | 9ee6e8bb | pbrook | shouldn't do any harm. */
|
1740 | 9ee6e8bb | pbrook | return env->cp15.c6_insn;
|
1741 | 9ee6e8bb | pbrook | } |
1742 | 9ee6e8bb | pbrook | case 2: |
1743 | 9ee6e8bb | pbrook | if (arm_feature(env, ARM_FEATURE_V6)) {
|
1744 | 9ee6e8bb | pbrook | /* Instruction Fault Adrress. */
|
1745 | 9ee6e8bb | pbrook | return env->cp15.c6_insn;
|
1746 | 9ee6e8bb | pbrook | } else {
|
1747 | 9ee6e8bb | pbrook | goto bad_reg;
|
1748 | 9ee6e8bb | pbrook | } |
1749 | 9ee6e8bb | pbrook | default:
|
1750 | 9ee6e8bb | pbrook | goto bad_reg;
|
1751 | 9ee6e8bb | pbrook | } |
1752 | b5ff1b31 | bellard | } |
1753 | b5ff1b31 | bellard | case 7: /* Cache control. */ |
1754 | 6fbe23d5 | pbrook | /* FIXME: Should only clear Z flag if destination is r15. */
|
1755 | 6fbe23d5 | pbrook | env->ZF = 0;
|
1756 | b5ff1b31 | bellard | return 0; |
1757 | b5ff1b31 | bellard | case 8: /* MMU TLB control. */ |
1758 | b5ff1b31 | bellard | goto bad_reg;
|
1759 | b5ff1b31 | bellard | case 9: /* Cache lockdown. */ |
1760 | 9ee6e8bb | pbrook | switch (op1) {
|
1761 | 9ee6e8bb | pbrook | case 0: /* L1 cache. */ |
1762 | 9ee6e8bb | pbrook | if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1763 | 9ee6e8bb | pbrook | return 0; |
1764 | 9ee6e8bb | pbrook | switch (op2) {
|
1765 | 9ee6e8bb | pbrook | case 0: |
1766 | 9ee6e8bb | pbrook | return env->cp15.c9_data;
|
1767 | 9ee6e8bb | pbrook | case 1: |
1768 | 9ee6e8bb | pbrook | return env->cp15.c9_insn;
|
1769 | 9ee6e8bb | pbrook | default:
|
1770 | 9ee6e8bb | pbrook | goto bad_reg;
|
1771 | 9ee6e8bb | pbrook | } |
1772 | 9ee6e8bb | pbrook | case 1: /* L2 cache */ |
1773 | 9ee6e8bb | pbrook | if (crm != 0) |
1774 | 9ee6e8bb | pbrook | goto bad_reg;
|
1775 | 9ee6e8bb | pbrook | /* L2 Lockdown and Auxiliary control. */
|
1776 | c3d2689d | balrog | return 0; |
1777 | b5ff1b31 | bellard | default:
|
1778 | b5ff1b31 | bellard | goto bad_reg;
|
1779 | b5ff1b31 | bellard | } |
1780 | b5ff1b31 | bellard | case 10: /* MMU TLB lockdown. */ |
1781 | b5ff1b31 | bellard | /* ??? TLB lockdown not implemented. */
|
1782 | b5ff1b31 | bellard | return 0; |
1783 | b5ff1b31 | bellard | case 11: /* TCM DMA control. */ |
1784 | b5ff1b31 | bellard | case 12: /* Reserved. */ |
1785 | b5ff1b31 | bellard | goto bad_reg;
|
1786 | b5ff1b31 | bellard | case 13: /* Process ID. */ |
1787 | b5ff1b31 | bellard | switch (op2) {
|
1788 | b5ff1b31 | bellard | case 0: |
1789 | b5ff1b31 | bellard | return env->cp15.c13_fcse;
|
1790 | b5ff1b31 | bellard | case 1: |
1791 | b5ff1b31 | bellard | return env->cp15.c13_context;
|
1792 | b5ff1b31 | bellard | default:
|
1793 | b5ff1b31 | bellard | goto bad_reg;
|
1794 | b5ff1b31 | bellard | } |
1795 | b5ff1b31 | bellard | case 14: /* Reserved. */ |
1796 | b5ff1b31 | bellard | goto bad_reg;
|
1797 | b5ff1b31 | bellard | case 15: /* Implementation specific. */ |
1798 | c1713132 | balrog | if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
1799 | c3d2689d | balrog | if (op2 == 0 && crm == 1) |
1800 | c1713132 | balrog | return env->cp15.c15_cpar;
|
1801 | c1713132 | balrog | |
1802 | c1713132 | balrog | goto bad_reg;
|
1803 | c1713132 | balrog | } |
1804 | c3d2689d | balrog | if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
|
1805 | c3d2689d | balrog | switch (crm) {
|
1806 | c3d2689d | balrog | case 0: |
1807 | c3d2689d | balrog | return 0; |
1808 | c3d2689d | balrog | case 1: /* Read TI925T configuration. */ |
1809 | c3d2689d | balrog | return env->cp15.c15_ticonfig;
|
1810 | c3d2689d | balrog | case 2: /* Read I_max. */ |
1811 | c3d2689d | balrog | return env->cp15.c15_i_max;
|
1812 | c3d2689d | balrog | case 3: /* Read I_min. */ |
1813 | c3d2689d | balrog | return env->cp15.c15_i_min;
|
1814 | c3d2689d | balrog | case 4: /* Read thread-ID. */ |
1815 | c3d2689d | balrog | return env->cp15.c15_threadid;
|
1816 | c3d2689d | balrog | case 8: /* TI925T_status */ |
1817 | c3d2689d | balrog | return 0; |
1818 | c3d2689d | balrog | } |
1819 | 827df9f3 | balrog | /* TODO: Peripheral port remap register:
|
1820 | 827df9f3 | balrog | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
|
1821 | 827df9f3 | balrog | * controller base address at $rn & ~0xfff and map size of
|
1822 | 827df9f3 | balrog | * 0x200 << ($rn & 0xfff), when MMU is off. */
|
1823 | c3d2689d | balrog | goto bad_reg;
|
1824 | c3d2689d | balrog | } |
1825 | b5ff1b31 | bellard | return 0; |
1826 | b5ff1b31 | bellard | } |
1827 | b5ff1b31 | bellard | bad_reg:
|
1828 | b5ff1b31 | bellard | /* ??? For debugging only. Should raise illegal instruction exception. */
|
1829 | 9ee6e8bb | pbrook | cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
|
1830 | 9ee6e8bb | pbrook | (insn >> 16) & 0xf, crm, op1, op2); |
1831 | b5ff1b31 | bellard | return 0; |
1832 | b5ff1b31 | bellard | } |
1833 | b5ff1b31 | bellard | |
1834 | b0109805 | pbrook | void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
|
1835 | 9ee6e8bb | pbrook | { |
1836 | 9ee6e8bb | pbrook | env->banked_r13[bank_number(mode)] = val; |
1837 | 9ee6e8bb | pbrook | } |
1838 | 9ee6e8bb | pbrook | |
1839 | b0109805 | pbrook | uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode) |
1840 | 9ee6e8bb | pbrook | { |
1841 | 9ee6e8bb | pbrook | return env->banked_r13[bank_number(mode)];
|
1842 | 9ee6e8bb | pbrook | } |
1843 | 9ee6e8bb | pbrook | |
1844 | 8984bd2e | pbrook | uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) |
1845 | 9ee6e8bb | pbrook | { |
1846 | 9ee6e8bb | pbrook | switch (reg) {
|
1847 | 9ee6e8bb | pbrook | case 0: /* APSR */ |
1848 | 9ee6e8bb | pbrook | return xpsr_read(env) & 0xf8000000; |
1849 | 9ee6e8bb | pbrook | case 1: /* IAPSR */ |
1850 | 9ee6e8bb | pbrook | return xpsr_read(env) & 0xf80001ff; |
1851 | 9ee6e8bb | pbrook | case 2: /* EAPSR */ |
1852 | 9ee6e8bb | pbrook | return xpsr_read(env) & 0xff00fc00; |
1853 | 9ee6e8bb | pbrook | case 3: /* xPSR */ |
1854 | 9ee6e8bb | pbrook | return xpsr_read(env) & 0xff00fdff; |
1855 | 9ee6e8bb | pbrook | case 5: /* IPSR */ |
1856 | 9ee6e8bb | pbrook | return xpsr_read(env) & 0x000001ff; |
1857 | 9ee6e8bb | pbrook | case 6: /* EPSR */ |
1858 | 9ee6e8bb | pbrook | return xpsr_read(env) & 0x0700fc00; |
1859 | 9ee6e8bb | pbrook | case 7: /* IEPSR */ |
1860 | 9ee6e8bb | pbrook | return xpsr_read(env) & 0x0700edff; |
1861 | 9ee6e8bb | pbrook | case 8: /* MSP */ |
1862 | 9ee6e8bb | pbrook | return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; |
1863 | 9ee6e8bb | pbrook | case 9: /* PSP */ |
1864 | 9ee6e8bb | pbrook | return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; |
1865 | 9ee6e8bb | pbrook | case 16: /* PRIMASK */ |
1866 | 9ee6e8bb | pbrook | return (env->uncached_cpsr & CPSR_I) != 0; |
1867 | 9ee6e8bb | pbrook | case 17: /* FAULTMASK */ |
1868 | 9ee6e8bb | pbrook | return (env->uncached_cpsr & CPSR_F) != 0; |
1869 | 9ee6e8bb | pbrook | case 18: /* BASEPRI */ |
1870 | 9ee6e8bb | pbrook | case 19: /* BASEPRI_MAX */ |
1871 | 9ee6e8bb | pbrook | return env->v7m.basepri;
|
1872 | 9ee6e8bb | pbrook | case 20: /* CONTROL */ |
1873 | 9ee6e8bb | pbrook | return env->v7m.control;
|
1874 | 9ee6e8bb | pbrook | default:
|
1875 | 9ee6e8bb | pbrook | /* ??? For debugging only. */
|
1876 | 9ee6e8bb | pbrook | cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
|
1877 | 9ee6e8bb | pbrook | return 0; |
1878 | 9ee6e8bb | pbrook | } |
1879 | 9ee6e8bb | pbrook | } |
1880 | 9ee6e8bb | pbrook | |
1881 | 8984bd2e | pbrook | void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
|
1882 | 9ee6e8bb | pbrook | { |
1883 | 9ee6e8bb | pbrook | switch (reg) {
|
1884 | 9ee6e8bb | pbrook | case 0: /* APSR */ |
1885 | 9ee6e8bb | pbrook | xpsr_write(env, val, 0xf8000000);
|
1886 | 9ee6e8bb | pbrook | break;
|
1887 | 9ee6e8bb | pbrook | case 1: /* IAPSR */ |
1888 | 9ee6e8bb | pbrook | xpsr_write(env, val, 0xf8000000);
|
1889 | 9ee6e8bb | pbrook | break;
|
1890 | 9ee6e8bb | pbrook | case 2: /* EAPSR */ |
1891 | 9ee6e8bb | pbrook | xpsr_write(env, val, 0xfe00fc00);
|
1892 | 9ee6e8bb | pbrook | break;
|
1893 | 9ee6e8bb | pbrook | case 3: /* xPSR */ |
1894 | 9ee6e8bb | pbrook | xpsr_write(env, val, 0xfe00fc00);
|
1895 | 9ee6e8bb | pbrook | break;
|
1896 | 9ee6e8bb | pbrook | case 5: /* IPSR */ |
1897 | 9ee6e8bb | pbrook | /* IPSR bits are readonly. */
|
1898 | 9ee6e8bb | pbrook | break;
|
1899 | 9ee6e8bb | pbrook | case 6: /* EPSR */ |
1900 | 9ee6e8bb | pbrook | xpsr_write(env, val, 0x0600fc00);
|
1901 | 9ee6e8bb | pbrook | break;
|
1902 | 9ee6e8bb | pbrook | case 7: /* IEPSR */ |
1903 | 9ee6e8bb | pbrook | xpsr_write(env, val, 0x0600fc00);
|
1904 | 9ee6e8bb | pbrook | break;
|
1905 | 9ee6e8bb | pbrook | case 8: /* MSP */ |
1906 | 9ee6e8bb | pbrook | if (env->v7m.current_sp)
|
1907 | 9ee6e8bb | pbrook | env->v7m.other_sp = val; |
1908 | 9ee6e8bb | pbrook | else
|
1909 | 9ee6e8bb | pbrook | env->regs[13] = val;
|
1910 | 9ee6e8bb | pbrook | break;
|
1911 | 9ee6e8bb | pbrook | case 9: /* PSP */ |
1912 | 9ee6e8bb | pbrook | if (env->v7m.current_sp)
|
1913 | 9ee6e8bb | pbrook | env->regs[13] = val;
|
1914 | 9ee6e8bb | pbrook | else
|
1915 | 9ee6e8bb | pbrook | env->v7m.other_sp = val; |
1916 | 9ee6e8bb | pbrook | break;
|
1917 | 9ee6e8bb | pbrook | case 16: /* PRIMASK */ |
1918 | 9ee6e8bb | pbrook | if (val & 1) |
1919 | 9ee6e8bb | pbrook | env->uncached_cpsr |= CPSR_I; |
1920 | 9ee6e8bb | pbrook | else
|
1921 | 9ee6e8bb | pbrook | env->uncached_cpsr &= ~CPSR_I; |
1922 | 9ee6e8bb | pbrook | break;
|
1923 | 9ee6e8bb | pbrook | case 17: /* FAULTMASK */ |
1924 | 9ee6e8bb | pbrook | if (val & 1) |
1925 | 9ee6e8bb | pbrook | env->uncached_cpsr |= CPSR_F; |
1926 | 9ee6e8bb | pbrook | else
|
1927 | 9ee6e8bb | pbrook | env->uncached_cpsr &= ~CPSR_F; |
1928 | 9ee6e8bb | pbrook | break;
|
1929 | 9ee6e8bb | pbrook | case 18: /* BASEPRI */ |
1930 | 9ee6e8bb | pbrook | env->v7m.basepri = val & 0xff;
|
1931 | 9ee6e8bb | pbrook | break;
|
1932 | 9ee6e8bb | pbrook | case 19: /* BASEPRI_MAX */ |
1933 | 9ee6e8bb | pbrook | val &= 0xff;
|
1934 | 9ee6e8bb | pbrook | if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) |
1935 | 9ee6e8bb | pbrook | env->v7m.basepri = val; |
1936 | 9ee6e8bb | pbrook | break;
|
1937 | 9ee6e8bb | pbrook | case 20: /* CONTROL */ |
1938 | 9ee6e8bb | pbrook | env->v7m.control = val & 3;
|
1939 | 9ee6e8bb | pbrook | switch_v7m_sp(env, (val & 2) != 0); |
1940 | 9ee6e8bb | pbrook | break;
|
1941 | 9ee6e8bb | pbrook | default:
|
1942 | 9ee6e8bb | pbrook | /* ??? For debugging only. */
|
1943 | 9ee6e8bb | pbrook | cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
|
1944 | 9ee6e8bb | pbrook | return;
|
1945 | 9ee6e8bb | pbrook | } |
1946 | 9ee6e8bb | pbrook | } |
1947 | 9ee6e8bb | pbrook | |
1948 | c1713132 | balrog | void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
1949 | c1713132 | balrog | ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, |
1950 | c1713132 | balrog | void *opaque)
|
1951 | c1713132 | balrog | { |
1952 | c1713132 | balrog | if (cpnum < 0 || cpnum > 14) { |
1953 | c1713132 | balrog | cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
|
1954 | c1713132 | balrog | return;
|
1955 | c1713132 | balrog | } |
1956 | c1713132 | balrog | |
1957 | c1713132 | balrog | env->cp[cpnum].cp_read = cp_read; |
1958 | c1713132 | balrog | env->cp[cpnum].cp_write = cp_write; |
1959 | c1713132 | balrog | env->cp[cpnum].opaque = opaque; |
1960 | c1713132 | balrog | } |
1961 | c1713132 | balrog | |
1962 | b5ff1b31 | bellard | #endif
|
1963 | 6ddbc6e4 | pbrook | |
1964 | 6ddbc6e4 | pbrook | /* Note that signed overflow is undefined in C. The following routines are
|
1965 | 6ddbc6e4 | pbrook | careful to use unsigned types where modulo arithmetic is required.
|
1966 | 6ddbc6e4 | pbrook | Failure to do so _will_ break on newer gcc. */
|
1967 | 6ddbc6e4 | pbrook | |
1968 | 6ddbc6e4 | pbrook | /* Signed saturating arithmetic. */
|
1969 | 6ddbc6e4 | pbrook | |
1970 | 1654b2d6 | aurel32 | /* Perform 16-bit signed saturating addition. */
|
1971 | 6ddbc6e4 | pbrook | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
1972 | 6ddbc6e4 | pbrook | { |
1973 | 6ddbc6e4 | pbrook | uint16_t res; |
1974 | 6ddbc6e4 | pbrook | |
1975 | 6ddbc6e4 | pbrook | res = a + b; |
1976 | 6ddbc6e4 | pbrook | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { |
1977 | 6ddbc6e4 | pbrook | if (a & 0x8000) |
1978 | 6ddbc6e4 | pbrook | res = 0x8000;
|
1979 | 6ddbc6e4 | pbrook | else
|
1980 | 6ddbc6e4 | pbrook | res = 0x7fff;
|
1981 | 6ddbc6e4 | pbrook | } |
1982 | 6ddbc6e4 | pbrook | return res;
|
1983 | 6ddbc6e4 | pbrook | } |
1984 | 6ddbc6e4 | pbrook | |
1985 | 1654b2d6 | aurel32 | /* Perform 8-bit signed saturating addition. */
|
1986 | 6ddbc6e4 | pbrook | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
1987 | 6ddbc6e4 | pbrook | { |
1988 | 6ddbc6e4 | pbrook | uint8_t res; |
1989 | 6ddbc6e4 | pbrook | |
1990 | 6ddbc6e4 | pbrook | res = a + b; |
1991 | 6ddbc6e4 | pbrook | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { |
1992 | 6ddbc6e4 | pbrook | if (a & 0x80) |
1993 | 6ddbc6e4 | pbrook | res = 0x80;
|
1994 | 6ddbc6e4 | pbrook | else
|
1995 | 6ddbc6e4 | pbrook | res = 0x7f;
|
1996 | 6ddbc6e4 | pbrook | } |
1997 | 6ddbc6e4 | pbrook | return res;
|
1998 | 6ddbc6e4 | pbrook | } |
1999 | 6ddbc6e4 | pbrook | |
2000 | 1654b2d6 | aurel32 | /* Perform 16-bit signed saturating subtraction. */
|
2001 | 6ddbc6e4 | pbrook | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
2002 | 6ddbc6e4 | pbrook | { |
2003 | 6ddbc6e4 | pbrook | uint16_t res; |
2004 | 6ddbc6e4 | pbrook | |
2005 | 6ddbc6e4 | pbrook | res = a - b; |
2006 | 6ddbc6e4 | pbrook | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { |
2007 | 6ddbc6e4 | pbrook | if (a & 0x8000) |
2008 | 6ddbc6e4 | pbrook | res = 0x8000;
|
2009 | 6ddbc6e4 | pbrook | else
|
2010 | 6ddbc6e4 | pbrook | res = 0x7fff;
|
2011 | 6ddbc6e4 | pbrook | } |
2012 | 6ddbc6e4 | pbrook | return res;
|
2013 | 6ddbc6e4 | pbrook | } |
2014 | 6ddbc6e4 | pbrook | |
2015 | 1654b2d6 | aurel32 | /* Perform 8-bit signed saturating subtraction. */
|
2016 | 6ddbc6e4 | pbrook | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
2017 | 6ddbc6e4 | pbrook | { |
2018 | 6ddbc6e4 | pbrook | uint8_t res; |
2019 | 6ddbc6e4 | pbrook | |
2020 | 6ddbc6e4 | pbrook | res = a - b; |
2021 | 6ddbc6e4 | pbrook | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { |
2022 | 6ddbc6e4 | pbrook | if (a & 0x80) |
2023 | 6ddbc6e4 | pbrook | res = 0x80;
|
2024 | 6ddbc6e4 | pbrook | else
|
2025 | 6ddbc6e4 | pbrook | res = 0x7f;
|
2026 | 6ddbc6e4 | pbrook | } |
2027 | 6ddbc6e4 | pbrook | return res;
|
2028 | 6ddbc6e4 | pbrook | } |
2029 | 6ddbc6e4 | pbrook | |
2030 | 6ddbc6e4 | pbrook | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); |
2031 | 6ddbc6e4 | pbrook | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); |
2032 | 6ddbc6e4 | pbrook | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); |
2033 | 6ddbc6e4 | pbrook | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); |
2034 | 6ddbc6e4 | pbrook | #define PFX q
|
2035 | 6ddbc6e4 | pbrook | |
2036 | 6ddbc6e4 | pbrook | #include "op_addsub.h" |
2037 | 6ddbc6e4 | pbrook | |
2038 | 6ddbc6e4 | pbrook | /* Unsigned saturating arithmetic. */
|
2039 | 460a09c1 | pbrook | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
2040 | 6ddbc6e4 | pbrook | { |
2041 | 6ddbc6e4 | pbrook | uint16_t res; |
2042 | 6ddbc6e4 | pbrook | res = a + b; |
2043 | 6ddbc6e4 | pbrook | if (res < a)
|
2044 | 6ddbc6e4 | pbrook | res = 0xffff;
|
2045 | 6ddbc6e4 | pbrook | return res;
|
2046 | 6ddbc6e4 | pbrook | } |
2047 | 6ddbc6e4 | pbrook | |
2048 | 460a09c1 | pbrook | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
2049 | 6ddbc6e4 | pbrook | { |
2050 | 4c4fd3f8 | Chih-Min Chao | if (a > b)
|
2051 | 6ddbc6e4 | pbrook | return a - b;
|
2052 | 6ddbc6e4 | pbrook | else
|
2053 | 6ddbc6e4 | pbrook | return 0; |
2054 | 6ddbc6e4 | pbrook | } |
2055 | 6ddbc6e4 | pbrook | |
2056 | 6ddbc6e4 | pbrook | static inline uint8_t add8_usat(uint8_t a, uint8_t b) |
2057 | 6ddbc6e4 | pbrook | { |
2058 | 6ddbc6e4 | pbrook | uint8_t res; |
2059 | 6ddbc6e4 | pbrook | res = a + b; |
2060 | 6ddbc6e4 | pbrook | if (res < a)
|
2061 | 6ddbc6e4 | pbrook | res = 0xff;
|
2062 | 6ddbc6e4 | pbrook | return res;
|
2063 | 6ddbc6e4 | pbrook | } |
2064 | 6ddbc6e4 | pbrook | |
2065 | 6ddbc6e4 | pbrook | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) |
2066 | 6ddbc6e4 | pbrook | { |
2067 | 4c4fd3f8 | Chih-Min Chao | if (a > b)
|
2068 | 6ddbc6e4 | pbrook | return a - b;
|
2069 | 6ddbc6e4 | pbrook | else
|
2070 | 6ddbc6e4 | pbrook | return 0; |
2071 | 6ddbc6e4 | pbrook | } |
2072 | 6ddbc6e4 | pbrook | |
2073 | 6ddbc6e4 | pbrook | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); |
2074 | 6ddbc6e4 | pbrook | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); |
2075 | 6ddbc6e4 | pbrook | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); |
2076 | 6ddbc6e4 | pbrook | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); |
2077 | 6ddbc6e4 | pbrook | #define PFX uq
|
2078 | 6ddbc6e4 | pbrook | |
2079 | 6ddbc6e4 | pbrook | #include "op_addsub.h" |
2080 | 6ddbc6e4 | pbrook | |
2081 | 6ddbc6e4 | pbrook | /* Signed modulo arithmetic. */
|
2082 | 6ddbc6e4 | pbrook | #define SARITH16(a, b, n, op) do { \ |
2083 | 6ddbc6e4 | pbrook | int32_t sum; \ |
2084 | 6ddbc6e4 | pbrook | sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \ |
2085 | 6ddbc6e4 | pbrook | RESULT(sum, n, 16); \
|
2086 | 6ddbc6e4 | pbrook | if (sum >= 0) \ |
2087 | 6ddbc6e4 | pbrook | ge |= 3 << (n * 2); \ |
2088 | 6ddbc6e4 | pbrook | } while(0) |
2089 | 6ddbc6e4 | pbrook | |
2090 | 6ddbc6e4 | pbrook | #define SARITH8(a, b, n, op) do { \ |
2091 | 6ddbc6e4 | pbrook | int32_t sum; \ |
2092 | 6ddbc6e4 | pbrook | sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \ |
2093 | 6ddbc6e4 | pbrook | RESULT(sum, n, 8); \
|
2094 | 6ddbc6e4 | pbrook | if (sum >= 0) \ |
2095 | 6ddbc6e4 | pbrook | ge |= 1 << n; \
|
2096 | 6ddbc6e4 | pbrook | } while(0) |
2097 | 6ddbc6e4 | pbrook | |
2098 | 6ddbc6e4 | pbrook | |
2099 | 6ddbc6e4 | pbrook | #define ADD16(a, b, n) SARITH16(a, b, n, +)
|
2100 | 6ddbc6e4 | pbrook | #define SUB16(a, b, n) SARITH16(a, b, n, -)
|
2101 | 6ddbc6e4 | pbrook | #define ADD8(a, b, n) SARITH8(a, b, n, +)
|
2102 | 6ddbc6e4 | pbrook | #define SUB8(a, b, n) SARITH8(a, b, n, -)
|
2103 | 6ddbc6e4 | pbrook | #define PFX s
|
2104 | 6ddbc6e4 | pbrook | #define ARITH_GE
|
2105 | 6ddbc6e4 | pbrook | |
2106 | 6ddbc6e4 | pbrook | #include "op_addsub.h" |
2107 | 6ddbc6e4 | pbrook | |
2108 | 6ddbc6e4 | pbrook | /* Unsigned modulo arithmetic. */
|
2109 | 6ddbc6e4 | pbrook | #define ADD16(a, b, n) do { \ |
2110 | 6ddbc6e4 | pbrook | uint32_t sum; \ |
2111 | 6ddbc6e4 | pbrook | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ |
2112 | 6ddbc6e4 | pbrook | RESULT(sum, n, 16); \
|
2113 | a87aa10b | balrog | if ((sum >> 16) == 1) \ |
2114 | 6ddbc6e4 | pbrook | ge |= 3 << (n * 2); \ |
2115 | 6ddbc6e4 | pbrook | } while(0) |
2116 | 6ddbc6e4 | pbrook | |
2117 | 6ddbc6e4 | pbrook | #define ADD8(a, b, n) do { \ |
2118 | 6ddbc6e4 | pbrook | uint32_t sum; \ |
2119 | 6ddbc6e4 | pbrook | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ |
2120 | 6ddbc6e4 | pbrook | RESULT(sum, n, 8); \
|
2121 | a87aa10b | balrog | if ((sum >> 8) == 1) \ |
2122 | a87aa10b | balrog | ge |= 1 << n; \
|
2123 | 6ddbc6e4 | pbrook | } while(0) |
2124 | 6ddbc6e4 | pbrook | |
2125 | 6ddbc6e4 | pbrook | #define SUB16(a, b, n) do { \ |
2126 | 6ddbc6e4 | pbrook | uint32_t sum; \ |
2127 | 6ddbc6e4 | pbrook | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ |
2128 | 6ddbc6e4 | pbrook | RESULT(sum, n, 16); \
|
2129 | 6ddbc6e4 | pbrook | if ((sum >> 16) == 0) \ |
2130 | 6ddbc6e4 | pbrook | ge |= 3 << (n * 2); \ |
2131 | 6ddbc6e4 | pbrook | } while(0) |
2132 | 6ddbc6e4 | pbrook | |
2133 | 6ddbc6e4 | pbrook | #define SUB8(a, b, n) do { \ |
2134 | 6ddbc6e4 | pbrook | uint32_t sum; \ |
2135 | 6ddbc6e4 | pbrook | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ |
2136 | 6ddbc6e4 | pbrook | RESULT(sum, n, 8); \
|
2137 | 6ddbc6e4 | pbrook | if ((sum >> 8) == 0) \ |
2138 | a87aa10b | balrog | ge |= 1 << n; \
|
2139 | 6ddbc6e4 | pbrook | } while(0) |
2140 | 6ddbc6e4 | pbrook | |
2141 | 6ddbc6e4 | pbrook | #define PFX u
|
2142 | 6ddbc6e4 | pbrook | #define ARITH_GE
|
2143 | 6ddbc6e4 | pbrook | |
2144 | 6ddbc6e4 | pbrook | #include "op_addsub.h" |
2145 | 6ddbc6e4 | pbrook | |
2146 | 6ddbc6e4 | pbrook | /* Halved signed arithmetic. */
|
2147 | 6ddbc6e4 | pbrook | #define ADD16(a, b, n) \
|
2148 | 6ddbc6e4 | pbrook | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) |
2149 | 6ddbc6e4 | pbrook | #define SUB16(a, b, n) \
|
2150 | 6ddbc6e4 | pbrook | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) |
2151 | 6ddbc6e4 | pbrook | #define ADD8(a, b, n) \
|
2152 | 6ddbc6e4 | pbrook | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) |
2153 | 6ddbc6e4 | pbrook | #define SUB8(a, b, n) \
|
2154 | 6ddbc6e4 | pbrook | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) |
2155 | 6ddbc6e4 | pbrook | #define PFX sh
|
2156 | 6ddbc6e4 | pbrook | |
2157 | 6ddbc6e4 | pbrook | #include "op_addsub.h" |
2158 | 6ddbc6e4 | pbrook | |
2159 | 6ddbc6e4 | pbrook | /* Halved unsigned arithmetic. */
|
2160 | 6ddbc6e4 | pbrook | #define ADD16(a, b, n) \
|
2161 | 6ddbc6e4 | pbrook | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) |
2162 | 6ddbc6e4 | pbrook | #define SUB16(a, b, n) \
|
2163 | 6ddbc6e4 | pbrook | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) |
2164 | 6ddbc6e4 | pbrook | #define ADD8(a, b, n) \
|
2165 | 6ddbc6e4 | pbrook | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) |
2166 | 6ddbc6e4 | pbrook | #define SUB8(a, b, n) \
|
2167 | 6ddbc6e4 | pbrook | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) |
2168 | 6ddbc6e4 | pbrook | #define PFX uh
|
2169 | 6ddbc6e4 | pbrook | |
2170 | 6ddbc6e4 | pbrook | #include "op_addsub.h" |
2171 | 6ddbc6e4 | pbrook | |
2172 | 6ddbc6e4 | pbrook | static inline uint8_t do_usad(uint8_t a, uint8_t b) |
2173 | 6ddbc6e4 | pbrook | { |
2174 | 6ddbc6e4 | pbrook | if (a > b)
|
2175 | 6ddbc6e4 | pbrook | return a - b;
|
2176 | 6ddbc6e4 | pbrook | else
|
2177 | 6ddbc6e4 | pbrook | return b - a;
|
2178 | 6ddbc6e4 | pbrook | } |
2179 | 6ddbc6e4 | pbrook | |
2180 | 6ddbc6e4 | pbrook | /* Unsigned sum of absolute byte differences. */
|
2181 | 6ddbc6e4 | pbrook | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) |
2182 | 6ddbc6e4 | pbrook | { |
2183 | 6ddbc6e4 | pbrook | uint32_t sum; |
2184 | 6ddbc6e4 | pbrook | sum = do_usad(a, b); |
2185 | 6ddbc6e4 | pbrook | sum += do_usad(a >> 8, b >> 8); |
2186 | 6ddbc6e4 | pbrook | sum += do_usad(a >> 16, b >>16); |
2187 | 6ddbc6e4 | pbrook | sum += do_usad(a >> 24, b >> 24); |
2188 | 6ddbc6e4 | pbrook | return sum;
|
2189 | 6ddbc6e4 | pbrook | } |
2190 | 6ddbc6e4 | pbrook | |
2191 | 6ddbc6e4 | pbrook | /* For ARMv6 SEL instruction. */
|
2192 | 6ddbc6e4 | pbrook | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) |
2193 | 6ddbc6e4 | pbrook | { |
2194 | 6ddbc6e4 | pbrook | uint32_t mask; |
2195 | 6ddbc6e4 | pbrook | |
2196 | 6ddbc6e4 | pbrook | mask = 0;
|
2197 | 6ddbc6e4 | pbrook | if (flags & 1) |
2198 | 6ddbc6e4 | pbrook | mask |= 0xff;
|
2199 | 6ddbc6e4 | pbrook | if (flags & 2) |
2200 | 6ddbc6e4 | pbrook | mask |= 0xff00;
|
2201 | 6ddbc6e4 | pbrook | if (flags & 4) |
2202 | 6ddbc6e4 | pbrook | mask |= 0xff0000;
|
2203 | 6ddbc6e4 | pbrook | if (flags & 8) |
2204 | 6ddbc6e4 | pbrook | mask |= 0xff000000;
|
2205 | 6ddbc6e4 | pbrook | return (a & mask) | (b & ~mask);
|
2206 | 6ddbc6e4 | pbrook | } |
2207 | 6ddbc6e4 | pbrook | |
2208 | 5e3f878a | pbrook | uint32_t HELPER(logicq_cc)(uint64_t val) |
2209 | 5e3f878a | pbrook | { |
2210 | 5e3f878a | pbrook | return (val >> 32) | (val != 0); |
2211 | 5e3f878a | pbrook | } |
2212 | 4373f3ce | pbrook | |
2213 | 4373f3ce | pbrook | /* VFP support. We follow the convention used for VFP instrunctions:
|
2214 | 4373f3ce | pbrook | Single precition routines have a "s" suffix, double precision a
|
2215 | 4373f3ce | pbrook | "d" suffix. */
|
2216 | 4373f3ce | pbrook | |
2217 | 4373f3ce | pbrook | /* Convert host exception flags to vfp form. */
|
2218 | 4373f3ce | pbrook | static inline int vfp_exceptbits_from_host(int host_bits) |
2219 | 4373f3ce | pbrook | { |
2220 | 4373f3ce | pbrook | int target_bits = 0; |
2221 | 4373f3ce | pbrook | |
2222 | 4373f3ce | pbrook | if (host_bits & float_flag_invalid)
|
2223 | 4373f3ce | pbrook | target_bits |= 1;
|
2224 | 4373f3ce | pbrook | if (host_bits & float_flag_divbyzero)
|
2225 | 4373f3ce | pbrook | target_bits |= 2;
|
2226 | 4373f3ce | pbrook | if (host_bits & float_flag_overflow)
|
2227 | 4373f3ce | pbrook | target_bits |= 4;
|
2228 | 4373f3ce | pbrook | if (host_bits & float_flag_underflow)
|
2229 | 4373f3ce | pbrook | target_bits |= 8;
|
2230 | 4373f3ce | pbrook | if (host_bits & float_flag_inexact)
|
2231 | 4373f3ce | pbrook | target_bits |= 0x10;
|
2232 | 4373f3ce | pbrook | return target_bits;
|
2233 | 4373f3ce | pbrook | } |
2234 | 4373f3ce | pbrook | |
2235 | 4373f3ce | pbrook | uint32_t HELPER(vfp_get_fpscr)(CPUState *env) |
2236 | 4373f3ce | pbrook | { |
2237 | 4373f3ce | pbrook | int i;
|
2238 | 4373f3ce | pbrook | uint32_t fpscr; |
2239 | 4373f3ce | pbrook | |
2240 | 4373f3ce | pbrook | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
|
2241 | 4373f3ce | pbrook | | (env->vfp.vec_len << 16)
|
2242 | 4373f3ce | pbrook | | (env->vfp.vec_stride << 20);
|
2243 | 4373f3ce | pbrook | i = get_float_exception_flags(&env->vfp.fp_status); |
2244 | 4373f3ce | pbrook | fpscr |= vfp_exceptbits_from_host(i); |
2245 | 4373f3ce | pbrook | return fpscr;
|
2246 | 4373f3ce | pbrook | } |
2247 | 4373f3ce | pbrook | |
2248 | 4373f3ce | pbrook | /* Convert vfp exception flags to target form. */
|
2249 | 4373f3ce | pbrook | static inline int vfp_exceptbits_to_host(int target_bits) |
2250 | 4373f3ce | pbrook | { |
2251 | 4373f3ce | pbrook | int host_bits = 0; |
2252 | 4373f3ce | pbrook | |
2253 | 4373f3ce | pbrook | if (target_bits & 1) |
2254 | 4373f3ce | pbrook | host_bits |= float_flag_invalid; |
2255 | 4373f3ce | pbrook | if (target_bits & 2) |
2256 | 4373f3ce | pbrook | host_bits |= float_flag_divbyzero; |
2257 | 4373f3ce | pbrook | if (target_bits & 4) |
2258 | 4373f3ce | pbrook | host_bits |= float_flag_overflow; |
2259 | 4373f3ce | pbrook | if (target_bits & 8) |
2260 | 4373f3ce | pbrook | host_bits |= float_flag_underflow; |
2261 | 4373f3ce | pbrook | if (target_bits & 0x10) |
2262 | 4373f3ce | pbrook | host_bits |= float_flag_inexact; |
2263 | 4373f3ce | pbrook | return host_bits;
|
2264 | 4373f3ce | pbrook | } |
2265 | 4373f3ce | pbrook | |
2266 | 4373f3ce | pbrook | void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
|
2267 | 4373f3ce | pbrook | { |
2268 | 4373f3ce | pbrook | int i;
|
2269 | 4373f3ce | pbrook | uint32_t changed; |
2270 | 4373f3ce | pbrook | |
2271 | 4373f3ce | pbrook | changed = env->vfp.xregs[ARM_VFP_FPSCR]; |
2272 | 4373f3ce | pbrook | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
|
2273 | 4373f3ce | pbrook | env->vfp.vec_len = (val >> 16) & 7; |
2274 | 4373f3ce | pbrook | env->vfp.vec_stride = (val >> 20) & 3; |
2275 | 4373f3ce | pbrook | |
2276 | 4373f3ce | pbrook | changed ^= val; |
2277 | 4373f3ce | pbrook | if (changed & (3 << 22)) { |
2278 | 4373f3ce | pbrook | i = (val >> 22) & 3; |
2279 | 4373f3ce | pbrook | switch (i) {
|
2280 | 4373f3ce | pbrook | case 0: |
2281 | 4373f3ce | pbrook | i = float_round_nearest_even; |
2282 | 4373f3ce | pbrook | break;
|
2283 | 4373f3ce | pbrook | case 1: |
2284 | 4373f3ce | pbrook | i = float_round_up; |
2285 | 4373f3ce | pbrook | break;
|
2286 | 4373f3ce | pbrook | case 2: |
2287 | 4373f3ce | pbrook | i = float_round_down; |
2288 | 4373f3ce | pbrook | break;
|
2289 | 4373f3ce | pbrook | case 3: |
2290 | 4373f3ce | pbrook | i = float_round_to_zero; |
2291 | 4373f3ce | pbrook | break;
|
2292 | 4373f3ce | pbrook | } |
2293 | 4373f3ce | pbrook | set_float_rounding_mode(i, &env->vfp.fp_status); |
2294 | 4373f3ce | pbrook | } |
2295 | fe76d976 | pbrook | if (changed & (1 << 24)) |
2296 | fe76d976 | pbrook | set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
2297 | 5c7908ed | pbrook | if (changed & (1 << 25)) |
2298 | 5c7908ed | pbrook | set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); |
2299 | 4373f3ce | pbrook | |
2300 | 4373f3ce | pbrook | i = vfp_exceptbits_to_host((val >> 8) & 0x1f); |
2301 | 4373f3ce | pbrook | set_float_exception_flags(i, &env->vfp.fp_status); |
2302 | 4373f3ce | pbrook | } |
2303 | 4373f3ce | pbrook | |
2304 | 4373f3ce | pbrook | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
|
2305 | 4373f3ce | pbrook | |
2306 | 4373f3ce | pbrook | #define VFP_BINOP(name) \
|
2307 | 4373f3ce | pbrook | float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \ |
2308 | 4373f3ce | pbrook | { \ |
2309 | 4373f3ce | pbrook | return float32_ ## name (a, b, &env->vfp.fp_status); \ |
2310 | 4373f3ce | pbrook | } \ |
2311 | 4373f3ce | pbrook | float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \ |
2312 | 4373f3ce | pbrook | { \ |
2313 | 4373f3ce | pbrook | return float64_ ## name (a, b, &env->vfp.fp_status); \ |
2314 | 4373f3ce | pbrook | } |
2315 | 4373f3ce | pbrook | VFP_BINOP(add) |
2316 | 4373f3ce | pbrook | VFP_BINOP(sub) |
2317 | 4373f3ce | pbrook | VFP_BINOP(mul) |
2318 | 4373f3ce | pbrook | VFP_BINOP(div) |
2319 | 4373f3ce | pbrook | #undef VFP_BINOP
|
2320 | 4373f3ce | pbrook | |
2321 | 4373f3ce | pbrook | float32 VFP_HELPER(neg, s)(float32 a) |
2322 | 4373f3ce | pbrook | { |
2323 | 4373f3ce | pbrook | return float32_chs(a);
|
2324 | 4373f3ce | pbrook | } |
2325 | 4373f3ce | pbrook | |
2326 | 4373f3ce | pbrook | float64 VFP_HELPER(neg, d)(float64 a) |
2327 | 4373f3ce | pbrook | { |
2328 | 66230e0d | balrog | return float64_chs(a);
|
2329 | 4373f3ce | pbrook | } |
2330 | 4373f3ce | pbrook | |
2331 | 4373f3ce | pbrook | float32 VFP_HELPER(abs, s)(float32 a) |
2332 | 4373f3ce | pbrook | { |
2333 | 4373f3ce | pbrook | return float32_abs(a);
|
2334 | 4373f3ce | pbrook | } |
2335 | 4373f3ce | pbrook | |
2336 | 4373f3ce | pbrook | float64 VFP_HELPER(abs, d)(float64 a) |
2337 | 4373f3ce | pbrook | { |
2338 | 66230e0d | balrog | return float64_abs(a);
|
2339 | 4373f3ce | pbrook | } |
2340 | 4373f3ce | pbrook | |
2341 | 4373f3ce | pbrook | float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env) |
2342 | 4373f3ce | pbrook | { |
2343 | 4373f3ce | pbrook | return float32_sqrt(a, &env->vfp.fp_status);
|
2344 | 4373f3ce | pbrook | } |
2345 | 4373f3ce | pbrook | |
2346 | 4373f3ce | pbrook | float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env) |
2347 | 4373f3ce | pbrook | { |
2348 | 4373f3ce | pbrook | return float64_sqrt(a, &env->vfp.fp_status);
|
2349 | 4373f3ce | pbrook | } |
2350 | 4373f3ce | pbrook | |
2351 | 4373f3ce | pbrook | /* XXX: check quiet/signaling case */
|
2352 | 4373f3ce | pbrook | #define DO_VFP_cmp(p, type) \
|
2353 | 4373f3ce | pbrook | void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
|
2354 | 4373f3ce | pbrook | { \ |
2355 | 4373f3ce | pbrook | uint32_t flags; \ |
2356 | 4373f3ce | pbrook | switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ |
2357 | 4373f3ce | pbrook | case 0: flags = 0x6; break; \ |
2358 | 4373f3ce | pbrook | case -1: flags = 0x8; break; \ |
2359 | 4373f3ce | pbrook | case 1: flags = 0x2; break; \ |
2360 | 4373f3ce | pbrook | default: case 2: flags = 0x3; break; \ |
2361 | 4373f3ce | pbrook | } \ |
2362 | 4373f3ce | pbrook | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
|
2363 | 4373f3ce | pbrook | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
|
2364 | 4373f3ce | pbrook | } \ |
2365 | 4373f3ce | pbrook | void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
|
2366 | 4373f3ce | pbrook | { \ |
2367 | 4373f3ce | pbrook | uint32_t flags; \ |
2368 | 4373f3ce | pbrook | switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ |
2369 | 4373f3ce | pbrook | case 0: flags = 0x6; break; \ |
2370 | 4373f3ce | pbrook | case -1: flags = 0x8; break; \ |
2371 | 4373f3ce | pbrook | case 1: flags = 0x2; break; \ |
2372 | 4373f3ce | pbrook | default: case 2: flags = 0x3; break; \ |
2373 | 4373f3ce | pbrook | } \ |
2374 | 4373f3ce | pbrook | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
|
2375 | 4373f3ce | pbrook | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
|
2376 | 4373f3ce | pbrook | } |
2377 | 4373f3ce | pbrook | DO_VFP_cmp(s, float32) |
2378 | 4373f3ce | pbrook | DO_VFP_cmp(d, float64) |
2379 | 4373f3ce | pbrook | #undef DO_VFP_cmp
|
2380 | 4373f3ce | pbrook | |
2381 | 4373f3ce | pbrook | /* Helper routines to perform bitwise copies between float and int. */
|
2382 | 4373f3ce | pbrook | static inline float32 vfp_itos(uint32_t i) |
2383 | 4373f3ce | pbrook | { |
2384 | 4373f3ce | pbrook | union {
|
2385 | 4373f3ce | pbrook | uint32_t i; |
2386 | 4373f3ce | pbrook | float32 s; |
2387 | 4373f3ce | pbrook | } v; |
2388 | 4373f3ce | pbrook | |
2389 | 4373f3ce | pbrook | v.i = i; |
2390 | 4373f3ce | pbrook | return v.s;
|
2391 | 4373f3ce | pbrook | } |
2392 | 4373f3ce | pbrook | |
2393 | 4373f3ce | pbrook | static inline uint32_t vfp_stoi(float32 s) |
2394 | 4373f3ce | pbrook | { |
2395 | 4373f3ce | pbrook | union {
|
2396 | 4373f3ce | pbrook | uint32_t i; |
2397 | 4373f3ce | pbrook | float32 s; |
2398 | 4373f3ce | pbrook | } v; |
2399 | 4373f3ce | pbrook | |
2400 | 4373f3ce | pbrook | v.s = s; |
2401 | 4373f3ce | pbrook | return v.i;
|
2402 | 4373f3ce | pbrook | } |
2403 | 4373f3ce | pbrook | |
2404 | 4373f3ce | pbrook | static inline float64 vfp_itod(uint64_t i) |
2405 | 4373f3ce | pbrook | { |
2406 | 4373f3ce | pbrook | union {
|
2407 | 4373f3ce | pbrook | uint64_t i; |
2408 | 4373f3ce | pbrook | float64 d; |
2409 | 4373f3ce | pbrook | } v; |
2410 | 4373f3ce | pbrook | |
2411 | 4373f3ce | pbrook | v.i = i; |
2412 | 4373f3ce | pbrook | return v.d;
|
2413 | 4373f3ce | pbrook | } |
2414 | 4373f3ce | pbrook | |
2415 | 4373f3ce | pbrook | static inline uint64_t vfp_dtoi(float64 d) |
2416 | 4373f3ce | pbrook | { |
2417 | 4373f3ce | pbrook | union {
|
2418 | 4373f3ce | pbrook | uint64_t i; |
2419 | 4373f3ce | pbrook | float64 d; |
2420 | 4373f3ce | pbrook | } v; |
2421 | 4373f3ce | pbrook | |
2422 | 4373f3ce | pbrook | v.d = d; |
2423 | 4373f3ce | pbrook | return v.i;
|
2424 | 4373f3ce | pbrook | } |
2425 | 4373f3ce | pbrook | |
2426 | 4373f3ce | pbrook | /* Integer to float conversion. */
|
2427 | 4373f3ce | pbrook | float32 VFP_HELPER(uito, s)(float32 x, CPUState *env) |
2428 | 4373f3ce | pbrook | { |
2429 | 4373f3ce | pbrook | return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
|
2430 | 4373f3ce | pbrook | } |
2431 | 4373f3ce | pbrook | |
2432 | 4373f3ce | pbrook | float64 VFP_HELPER(uito, d)(float32 x, CPUState *env) |
2433 | 4373f3ce | pbrook | { |
2434 | 4373f3ce | pbrook | return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
|
2435 | 4373f3ce | pbrook | } |
2436 | 4373f3ce | pbrook | |
2437 | 4373f3ce | pbrook | float32 VFP_HELPER(sito, s)(float32 x, CPUState *env) |
2438 | 4373f3ce | pbrook | { |
2439 | 4373f3ce | pbrook | return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
|
2440 | 4373f3ce | pbrook | } |
2441 | 4373f3ce | pbrook | |
2442 | 4373f3ce | pbrook | float64 VFP_HELPER(sito, d)(float32 x, CPUState *env) |
2443 | 4373f3ce | pbrook | { |
2444 | 4373f3ce | pbrook | return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
|
2445 | 4373f3ce | pbrook | } |
2446 | 4373f3ce | pbrook | |
2447 | 4373f3ce | pbrook | /* Float to integer conversion. */
|
2448 | 4373f3ce | pbrook | float32 VFP_HELPER(toui, s)(float32 x, CPUState *env) |
2449 | 4373f3ce | pbrook | { |
2450 | 4373f3ce | pbrook | return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status));
|
2451 | 4373f3ce | pbrook | } |
2452 | 4373f3ce | pbrook | |
2453 | 4373f3ce | pbrook | float32 VFP_HELPER(toui, d)(float64 x, CPUState *env) |
2454 | 4373f3ce | pbrook | { |
2455 | 4373f3ce | pbrook | return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status));
|
2456 | 4373f3ce | pbrook | } |
2457 | 4373f3ce | pbrook | |
2458 | 4373f3ce | pbrook | float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env) |
2459 | 4373f3ce | pbrook | { |
2460 | 4373f3ce | pbrook | return vfp_itos(float32_to_int32(x, &env->vfp.fp_status));
|
2461 | 4373f3ce | pbrook | } |
2462 | 4373f3ce | pbrook | |
2463 | 4373f3ce | pbrook | float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env) |
2464 | 4373f3ce | pbrook | { |
2465 | 4373f3ce | pbrook | return vfp_itos(float64_to_int32(x, &env->vfp.fp_status));
|
2466 | 4373f3ce | pbrook | } |
2467 | 4373f3ce | pbrook | |
2468 | 4373f3ce | pbrook | float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env) |
2469 | 4373f3ce | pbrook | { |
2470 | 4373f3ce | pbrook | return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status));
|
2471 | 4373f3ce | pbrook | } |
2472 | 4373f3ce | pbrook | |
2473 | 4373f3ce | pbrook | float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env) |
2474 | 4373f3ce | pbrook | { |
2475 | 4373f3ce | pbrook | return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status));
|
2476 | 4373f3ce | pbrook | } |
2477 | 4373f3ce | pbrook | |
2478 | 4373f3ce | pbrook | float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env) |
2479 | 4373f3ce | pbrook | { |
2480 | 4373f3ce | pbrook | return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status));
|
2481 | 4373f3ce | pbrook | } |
2482 | 4373f3ce | pbrook | |
2483 | 4373f3ce | pbrook | float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env) |
2484 | 4373f3ce | pbrook | { |
2485 | 4373f3ce | pbrook | return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status));
|
2486 | 4373f3ce | pbrook | } |
2487 | 4373f3ce | pbrook | |
2488 | 4373f3ce | pbrook | /* floating point conversion */
|
2489 | 4373f3ce | pbrook | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env) |
2490 | 4373f3ce | pbrook | { |
2491 | 4373f3ce | pbrook | return float32_to_float64(x, &env->vfp.fp_status);
|
2492 | 4373f3ce | pbrook | } |
2493 | 4373f3ce | pbrook | |
2494 | 4373f3ce | pbrook | float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env) |
2495 | 4373f3ce | pbrook | { |
2496 | 4373f3ce | pbrook | return float64_to_float32(x, &env->vfp.fp_status);
|
2497 | 4373f3ce | pbrook | } |
2498 | 4373f3ce | pbrook | |
2499 | 4373f3ce | pbrook | /* VFP3 fixed point conversion. */
|
2500 | 4373f3ce | pbrook | #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
|
2501 | 4373f3ce | pbrook | ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \ |
2502 | 4373f3ce | pbrook | { \ |
2503 | 4373f3ce | pbrook | ftype tmp; \ |
2504 | 4373f3ce | pbrook | tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \ |
2505 | 4373f3ce | pbrook | &env->vfp.fp_status); \ |
2506 | 644ad806 | pbrook | return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \ |
2507 | 4373f3ce | pbrook | } \ |
2508 | 4373f3ce | pbrook | ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \ |
2509 | 4373f3ce | pbrook | { \ |
2510 | 4373f3ce | pbrook | ftype tmp; \ |
2511 | 4373f3ce | pbrook | tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \ |
2512 | 4373f3ce | pbrook | return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \ |
2513 | 4373f3ce | pbrook | &env->vfp.fp_status)); \ |
2514 | 4373f3ce | pbrook | } |
2515 | 4373f3ce | pbrook | |
2516 | 4373f3ce | pbrook | VFP_CONV_FIX(sh, d, float64, int16, ) |
2517 | 4373f3ce | pbrook | VFP_CONV_FIX(sl, d, float64, int32, ) |
2518 | 4373f3ce | pbrook | VFP_CONV_FIX(uh, d, float64, uint16, u) |
2519 | 4373f3ce | pbrook | VFP_CONV_FIX(ul, d, float64, uint32, u) |
2520 | 4373f3ce | pbrook | VFP_CONV_FIX(sh, s, float32, int16, ) |
2521 | 4373f3ce | pbrook | VFP_CONV_FIX(sl, s, float32, int32, ) |
2522 | 4373f3ce | pbrook | VFP_CONV_FIX(uh, s, float32, uint16, u) |
2523 | 4373f3ce | pbrook | VFP_CONV_FIX(ul, s, float32, uint32, u) |
2524 | 4373f3ce | pbrook | #undef VFP_CONV_FIX
|
2525 | 4373f3ce | pbrook | |
2526 | 60011498 | Paul Brook | /* Half precision conversions. */
|
2527 | 60011498 | Paul Brook | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env) |
2528 | 60011498 | Paul Brook | { |
2529 | 60011498 | Paul Brook | float_status *s = &env->vfp.fp_status; |
2530 | 60011498 | Paul Brook | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
2531 | 60011498 | Paul Brook | return float16_to_float32(a, ieee, s);
|
2532 | 60011498 | Paul Brook | } |
2533 | 60011498 | Paul Brook | |
2534 | 60011498 | Paul Brook | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env) |
2535 | 60011498 | Paul Brook | { |
2536 | 60011498 | Paul Brook | float_status *s = &env->vfp.fp_status; |
2537 | 60011498 | Paul Brook | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
2538 | 60011498 | Paul Brook | return float32_to_float16(a, ieee, s);
|
2539 | 60011498 | Paul Brook | } |
2540 | 60011498 | Paul Brook | |
2541 | 4373f3ce | pbrook | float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env) |
2542 | 4373f3ce | pbrook | { |
2543 | 4373f3ce | pbrook | float_status *s = &env->vfp.fp_status; |
2544 | 4373f3ce | pbrook | float32 two = int32_to_float32(2, s);
|
2545 | 4373f3ce | pbrook | return float32_sub(two, float32_mul(a, b, s), s);
|
2546 | 4373f3ce | pbrook | } |
2547 | 4373f3ce | pbrook | |
2548 | 4373f3ce | pbrook | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env) |
2549 | 4373f3ce | pbrook | { |
2550 | 4373f3ce | pbrook | float_status *s = &env->vfp.fp_status; |
2551 | 4373f3ce | pbrook | float32 three = int32_to_float32(3, s);
|
2552 | 4373f3ce | pbrook | return float32_sub(three, float32_mul(a, b, s), s);
|
2553 | 4373f3ce | pbrook | } |
2554 | 4373f3ce | pbrook | |
2555 | 8f8e3aa4 | pbrook | /* NEON helpers. */
|
2556 | 8f8e3aa4 | pbrook | |
2557 | 4373f3ce | pbrook | /* TODO: The architecture specifies the value that the estimate functions
|
2558 | 4373f3ce | pbrook | should return. We return the exact reciprocal/root instead. */
|
2559 | 4373f3ce | pbrook | float32 HELPER(recpe_f32)(float32 a, CPUState *env) |
2560 | 4373f3ce | pbrook | { |
2561 | 4373f3ce | pbrook | float_status *s = &env->vfp.fp_status; |
2562 | 4373f3ce | pbrook | float32 one = int32_to_float32(1, s);
|
2563 | 4373f3ce | pbrook | return float32_div(one, a, s);
|
2564 | 4373f3ce | pbrook | } |
2565 | 4373f3ce | pbrook | |
2566 | 4373f3ce | pbrook | float32 HELPER(rsqrte_f32)(float32 a, CPUState *env) |
2567 | 4373f3ce | pbrook | { |
2568 | 4373f3ce | pbrook | float_status *s = &env->vfp.fp_status; |
2569 | 4373f3ce | pbrook | float32 one = int32_to_float32(1, s);
|
2570 | 4373f3ce | pbrook | return float32_div(one, float32_sqrt(a, s), s);
|
2571 | 4373f3ce | pbrook | } |
2572 | 4373f3ce | pbrook | |
2573 | 4373f3ce | pbrook | uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env) |
2574 | 4373f3ce | pbrook | { |
2575 | 4373f3ce | pbrook | float_status *s = &env->vfp.fp_status; |
2576 | 4373f3ce | pbrook | float32 tmp; |
2577 | 4373f3ce | pbrook | tmp = int32_to_float32(a, s); |
2578 | 4373f3ce | pbrook | tmp = float32_scalbn(tmp, -32, s);
|
2579 | 4373f3ce | pbrook | tmp = helper_recpe_f32(tmp, env); |
2580 | 4373f3ce | pbrook | tmp = float32_scalbn(tmp, 31, s);
|
2581 | 4373f3ce | pbrook | return float32_to_int32(tmp, s);
|
2582 | 4373f3ce | pbrook | } |
2583 | 4373f3ce | pbrook | |
2584 | 4373f3ce | pbrook | uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env) |
2585 | 4373f3ce | pbrook | { |
2586 | 4373f3ce | pbrook | float_status *s = &env->vfp.fp_status; |
2587 | 4373f3ce | pbrook | float32 tmp; |
2588 | 4373f3ce | pbrook | tmp = int32_to_float32(a, s); |
2589 | 4373f3ce | pbrook | tmp = float32_scalbn(tmp, -32, s);
|
2590 | 4373f3ce | pbrook | tmp = helper_rsqrte_f32(tmp, env); |
2591 | 4373f3ce | pbrook | tmp = float32_scalbn(tmp, 31, s);
|
2592 | 4373f3ce | pbrook | return float32_to_int32(tmp, s);
|
2593 | 4373f3ce | pbrook | } |
2594 | fe1479c3 | pbrook | |
2595 | fe1479c3 | pbrook | void HELPER(set_teecr)(CPUState *env, uint32_t val)
|
2596 | fe1479c3 | pbrook | { |
2597 | fe1479c3 | pbrook | val &= 1;
|
2598 | fe1479c3 | pbrook | if (env->teecr != val) {
|
2599 | fe1479c3 | pbrook | env->teecr = val; |
2600 | fe1479c3 | pbrook | tb_flush(env); |
2601 | fe1479c3 | pbrook | } |
2602 | fe1479c3 | pbrook | } |