root / target-i386 / svm.h @ a88790a1
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1 | 239fbd86 | ths | #ifndef __SVM_H
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2 | 239fbd86 | ths | #define __SVM_H
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3 | 239fbd86 | ths | |
4 | 239fbd86 | ths | #define TLB_CONTROL_DO_NOTHING 0 |
5 | 239fbd86 | ths | #define TLB_CONTROL_FLUSH_ALL_ASID 1 |
6 | 239fbd86 | ths | |
7 | 239fbd86 | ths | #define V_TPR_MASK 0x0f |
8 | 239fbd86 | ths | |
9 | 239fbd86 | ths | #define V_IRQ_SHIFT 8 |
10 | 239fbd86 | ths | #define V_IRQ_MASK (1 << V_IRQ_SHIFT) |
11 | 239fbd86 | ths | |
12 | 239fbd86 | ths | #define V_INTR_PRIO_SHIFT 16 |
13 | 239fbd86 | ths | #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) |
14 | 239fbd86 | ths | |
15 | 239fbd86 | ths | #define V_IGN_TPR_SHIFT 20 |
16 | 239fbd86 | ths | #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) |
17 | 239fbd86 | ths | |
18 | 239fbd86 | ths | #define V_INTR_MASKING_SHIFT 24 |
19 | 239fbd86 | ths | #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) |
20 | 239fbd86 | ths | |
21 | 239fbd86 | ths | #define SVM_INTERRUPT_SHADOW_MASK 1 |
22 | 239fbd86 | ths | |
23 | 239fbd86 | ths | #define SVM_IOIO_STR_SHIFT 2 |
24 | 239fbd86 | ths | #define SVM_IOIO_REP_SHIFT 3 |
25 | 239fbd86 | ths | #define SVM_IOIO_SIZE_SHIFT 4 |
26 | 239fbd86 | ths | #define SVM_IOIO_ASIZE_SHIFT 7 |
27 | 239fbd86 | ths | |
28 | 239fbd86 | ths | #define SVM_IOIO_TYPE_MASK 1 |
29 | 239fbd86 | ths | #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) |
30 | 239fbd86 | ths | #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) |
31 | 239fbd86 | ths | #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) |
32 | 239fbd86 | ths | #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) |
33 | 239fbd86 | ths | |
34 | 239fbd86 | ths | #define SVM_EVTINJ_VEC_MASK 0xff |
35 | 239fbd86 | ths | |
36 | 239fbd86 | ths | #define SVM_EVTINJ_TYPE_SHIFT 8 |
37 | 239fbd86 | ths | #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) |
38 | 239fbd86 | ths | |
39 | 239fbd86 | ths | #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) |
40 | 239fbd86 | ths | #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) |
41 | 239fbd86 | ths | #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) |
42 | 239fbd86 | ths | #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) |
43 | 239fbd86 | ths | |
44 | 239fbd86 | ths | #define SVM_EVTINJ_VALID (1 << 31) |
45 | 239fbd86 | ths | #define SVM_EVTINJ_VALID_ERR (1 << 11) |
46 | 239fbd86 | ths | |
47 | 239fbd86 | ths | #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
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48 | 239fbd86 | ths | |
49 | 239fbd86 | ths | #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
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50 | 239fbd86 | ths | #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
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51 | 239fbd86 | ths | #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
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52 | 239fbd86 | ths | #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
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53 | 239fbd86 | ths | |
54 | 239fbd86 | ths | #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
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55 | 239fbd86 | ths | #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
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56 | 239fbd86 | ths | |
57 | 239fbd86 | ths | #define SVM_EXIT_READ_CR0 0x000 |
58 | 239fbd86 | ths | #define SVM_EXIT_READ_CR3 0x003 |
59 | 239fbd86 | ths | #define SVM_EXIT_READ_CR4 0x004 |
60 | 239fbd86 | ths | #define SVM_EXIT_READ_CR8 0x008 |
61 | 239fbd86 | ths | #define SVM_EXIT_WRITE_CR0 0x010 |
62 | 239fbd86 | ths | #define SVM_EXIT_WRITE_CR3 0x013 |
63 | 239fbd86 | ths | #define SVM_EXIT_WRITE_CR4 0x014 |
64 | 239fbd86 | ths | #define SVM_EXIT_WRITE_CR8 0x018 |
65 | 239fbd86 | ths | #define SVM_EXIT_READ_DR0 0x020 |
66 | 239fbd86 | ths | #define SVM_EXIT_READ_DR1 0x021 |
67 | 239fbd86 | ths | #define SVM_EXIT_READ_DR2 0x022 |
68 | 239fbd86 | ths | #define SVM_EXIT_READ_DR3 0x023 |
69 | 239fbd86 | ths | #define SVM_EXIT_READ_DR4 0x024 |
70 | 239fbd86 | ths | #define SVM_EXIT_READ_DR5 0x025 |
71 | 239fbd86 | ths | #define SVM_EXIT_READ_DR6 0x026 |
72 | 239fbd86 | ths | #define SVM_EXIT_READ_DR7 0x027 |
73 | 239fbd86 | ths | #define SVM_EXIT_WRITE_DR0 0x030 |
74 | 239fbd86 | ths | #define SVM_EXIT_WRITE_DR1 0x031 |
75 | 239fbd86 | ths | #define SVM_EXIT_WRITE_DR2 0x032 |
76 | 239fbd86 | ths | #define SVM_EXIT_WRITE_DR3 0x033 |
77 | 239fbd86 | ths | #define SVM_EXIT_WRITE_DR4 0x034 |
78 | 239fbd86 | ths | #define SVM_EXIT_WRITE_DR5 0x035 |
79 | 239fbd86 | ths | #define SVM_EXIT_WRITE_DR6 0x036 |
80 | 239fbd86 | ths | #define SVM_EXIT_WRITE_DR7 0x037 |
81 | 239fbd86 | ths | #define SVM_EXIT_EXCP_BASE 0x040 |
82 | 239fbd86 | ths | #define SVM_EXIT_INTR 0x060 |
83 | 239fbd86 | ths | #define SVM_EXIT_NMI 0x061 |
84 | 239fbd86 | ths | #define SVM_EXIT_SMI 0x062 |
85 | 239fbd86 | ths | #define SVM_EXIT_INIT 0x063 |
86 | 239fbd86 | ths | #define SVM_EXIT_VINTR 0x064 |
87 | 239fbd86 | ths | #define SVM_EXIT_CR0_SEL_WRITE 0x065 |
88 | 239fbd86 | ths | #define SVM_EXIT_IDTR_READ 0x066 |
89 | 239fbd86 | ths | #define SVM_EXIT_GDTR_READ 0x067 |
90 | 239fbd86 | ths | #define SVM_EXIT_LDTR_READ 0x068 |
91 | 239fbd86 | ths | #define SVM_EXIT_TR_READ 0x069 |
92 | 239fbd86 | ths | #define SVM_EXIT_IDTR_WRITE 0x06a |
93 | 239fbd86 | ths | #define SVM_EXIT_GDTR_WRITE 0x06b |
94 | 239fbd86 | ths | #define SVM_EXIT_LDTR_WRITE 0x06c |
95 | 239fbd86 | ths | #define SVM_EXIT_TR_WRITE 0x06d |
96 | 239fbd86 | ths | #define SVM_EXIT_RDTSC 0x06e |
97 | 239fbd86 | ths | #define SVM_EXIT_RDPMC 0x06f |
98 | 239fbd86 | ths | #define SVM_EXIT_PUSHF 0x070 |
99 | 239fbd86 | ths | #define SVM_EXIT_POPF 0x071 |
100 | 239fbd86 | ths | #define SVM_EXIT_CPUID 0x072 |
101 | 239fbd86 | ths | #define SVM_EXIT_RSM 0x073 |
102 | 239fbd86 | ths | #define SVM_EXIT_IRET 0x074 |
103 | 239fbd86 | ths | #define SVM_EXIT_SWINT 0x075 |
104 | 239fbd86 | ths | #define SVM_EXIT_INVD 0x076 |
105 | 239fbd86 | ths | #define SVM_EXIT_PAUSE 0x077 |
106 | 239fbd86 | ths | #define SVM_EXIT_HLT 0x078 |
107 | 239fbd86 | ths | #define SVM_EXIT_INVLPG 0x079 |
108 | 239fbd86 | ths | #define SVM_EXIT_INVLPGA 0x07a |
109 | 239fbd86 | ths | #define SVM_EXIT_IOIO 0x07b |
110 | 239fbd86 | ths | #define SVM_EXIT_MSR 0x07c |
111 | 239fbd86 | ths | #define SVM_EXIT_TASK_SWITCH 0x07d |
112 | 239fbd86 | ths | #define SVM_EXIT_FERR_FREEZE 0x07e |
113 | 239fbd86 | ths | #define SVM_EXIT_SHUTDOWN 0x07f |
114 | 239fbd86 | ths | #define SVM_EXIT_VMRUN 0x080 |
115 | 239fbd86 | ths | #define SVM_EXIT_VMMCALL 0x081 |
116 | 239fbd86 | ths | #define SVM_EXIT_VMLOAD 0x082 |
117 | 239fbd86 | ths | #define SVM_EXIT_VMSAVE 0x083 |
118 | 239fbd86 | ths | #define SVM_EXIT_STGI 0x084 |
119 | 239fbd86 | ths | #define SVM_EXIT_CLGI 0x085 |
120 | 239fbd86 | ths | #define SVM_EXIT_SKINIT 0x086 |
121 | 239fbd86 | ths | #define SVM_EXIT_RDTSCP 0x087 |
122 | 239fbd86 | ths | #define SVM_EXIT_ICEBP 0x088 |
123 | 239fbd86 | ths | #define SVM_EXIT_WBINVD 0x089 |
124 | 239fbd86 | ths | /* only included in documentation, maybe wrong */
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125 | 239fbd86 | ths | #define SVM_EXIT_MONITOR 0x08a |
126 | 239fbd86 | ths | #define SVM_EXIT_MWAIT 0x08b |
127 | 239fbd86 | ths | #define SVM_EXIT_NPF 0x400 |
128 | 239fbd86 | ths | |
129 | 239fbd86 | ths | #define SVM_EXIT_ERR -1 |
130 | 239fbd86 | ths | |
131 | 239fbd86 | ths | #define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */ |
132 | 239fbd86 | ths | |
133 | 872929aa | bellard | struct __attribute__ ((__packed__)) vmcb_control_area {
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134 | 872929aa | bellard | uint16_t intercept_cr_read; |
135 | 872929aa | bellard | uint16_t intercept_cr_write; |
136 | 872929aa | bellard | uint16_t intercept_dr_read; |
137 | 872929aa | bellard | uint16_t intercept_dr_write; |
138 | 872929aa | bellard | uint32_t intercept_exceptions; |
139 | 872929aa | bellard | uint64_t intercept; |
140 | 872929aa | bellard | uint8_t reserved_1[44];
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141 | 872929aa | bellard | uint64_t iopm_base_pa; |
142 | 872929aa | bellard | uint64_t msrpm_base_pa; |
143 | 872929aa | bellard | uint64_t tsc_offset; |
144 | 872929aa | bellard | uint32_t asid; |
145 | 872929aa | bellard | uint8_t tlb_ctl; |
146 | 872929aa | bellard | uint8_t reserved_2[3];
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147 | 872929aa | bellard | uint32_t int_ctl; |
148 | 872929aa | bellard | uint32_t int_vector; |
149 | 872929aa | bellard | uint32_t int_state; |
150 | 872929aa | bellard | uint8_t reserved_3[4];
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151 | 872929aa | bellard | uint64_t exit_code; |
152 | 872929aa | bellard | uint64_t exit_info_1; |
153 | 872929aa | bellard | uint64_t exit_info_2; |
154 | 872929aa | bellard | uint32_t exit_int_info; |
155 | 872929aa | bellard | uint32_t exit_int_info_err; |
156 | 872929aa | bellard | uint64_t nested_ctl; |
157 | 872929aa | bellard | uint8_t reserved_4[16];
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158 | 872929aa | bellard | uint32_t event_inj; |
159 | 872929aa | bellard | uint32_t event_inj_err; |
160 | 872929aa | bellard | uint64_t nested_cr3; |
161 | 872929aa | bellard | uint64_t lbr_ctl; |
162 | 872929aa | bellard | uint8_t reserved_5[832];
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163 | 872929aa | bellard | }; |
164 | 239fbd86 | ths | |
165 | 872929aa | bellard | struct __attribute__ ((__packed__)) vmcb_seg {
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166 | 872929aa | bellard | uint16_t selector; |
167 | 872929aa | bellard | uint16_t attrib; |
168 | 872929aa | bellard | uint32_t limit; |
169 | 872929aa | bellard | uint64_t base; |
170 | 872929aa | bellard | }; |
171 | 239fbd86 | ths | |
172 | 872929aa | bellard | struct __attribute__ ((__packed__)) vmcb_save_area {
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173 | 872929aa | bellard | struct vmcb_seg es;
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174 | 872929aa | bellard | struct vmcb_seg cs;
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175 | 872929aa | bellard | struct vmcb_seg ss;
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176 | 872929aa | bellard | struct vmcb_seg ds;
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177 | 872929aa | bellard | struct vmcb_seg fs;
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178 | 872929aa | bellard | struct vmcb_seg gs;
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179 | 872929aa | bellard | struct vmcb_seg gdtr;
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180 | 872929aa | bellard | struct vmcb_seg ldtr;
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181 | 872929aa | bellard | struct vmcb_seg idtr;
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182 | 872929aa | bellard | struct vmcb_seg tr;
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183 | 872929aa | bellard | uint8_t reserved_1[43];
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184 | 872929aa | bellard | uint8_t cpl; |
185 | 872929aa | bellard | uint8_t reserved_2[4];
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186 | 872929aa | bellard | uint64_t efer; |
187 | 872929aa | bellard | uint8_t reserved_3[112];
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188 | 872929aa | bellard | uint64_t cr4; |
189 | 872929aa | bellard | uint64_t cr3; |
190 | 872929aa | bellard | uint64_t cr0; |
191 | 872929aa | bellard | uint64_t dr7; |
192 | 872929aa | bellard | uint64_t dr6; |
193 | 872929aa | bellard | uint64_t rflags; |
194 | 872929aa | bellard | uint64_t rip; |
195 | 872929aa | bellard | uint8_t reserved_4[88];
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196 | 872929aa | bellard | uint64_t rsp; |
197 | 872929aa | bellard | uint8_t reserved_5[24];
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198 | 872929aa | bellard | uint64_t rax; |
199 | 872929aa | bellard | uint64_t star; |
200 | 872929aa | bellard | uint64_t lstar; |
201 | 872929aa | bellard | uint64_t cstar; |
202 | 872929aa | bellard | uint64_t sfmask; |
203 | 872929aa | bellard | uint64_t kernel_gs_base; |
204 | 872929aa | bellard | uint64_t sysenter_cs; |
205 | 872929aa | bellard | uint64_t sysenter_esp; |
206 | 872929aa | bellard | uint64_t sysenter_eip; |
207 | 872929aa | bellard | uint64_t cr2; |
208 | db620f46 | bellard | uint8_t reserved_6[32];
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209 | 872929aa | bellard | uint64_t g_pat; |
210 | 872929aa | bellard | uint64_t dbgctl; |
211 | 872929aa | bellard | uint64_t br_from; |
212 | 872929aa | bellard | uint64_t br_to; |
213 | 872929aa | bellard | uint64_t last_excp_from; |
214 | 872929aa | bellard | uint64_t last_excp_to; |
215 | 872929aa | bellard | }; |
216 | 239fbd86 | ths | |
217 | 872929aa | bellard | struct __attribute__ ((__packed__)) vmcb {
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218 | 872929aa | bellard | struct vmcb_control_area control;
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219 | 872929aa | bellard | struct vmcb_save_area save;
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220 | 872929aa | bellard | }; |
221 | 239fbd86 | ths | |
222 | 239fbd86 | ths | #endif |