root / target-sh4 / helper.c @ a88790a1
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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 emulation
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3 | 5fafdf24 | ths | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | fdf9b3e8 | bellard | */
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19 | fdf9b3e8 | bellard | #include <stdarg.h> |
20 | fdf9b3e8 | bellard | #include <stdlib.h> |
21 | fdf9b3e8 | bellard | #include <stdio.h> |
22 | fdf9b3e8 | bellard | #include <string.h> |
23 | fdf9b3e8 | bellard | #include <inttypes.h> |
24 | fdf9b3e8 | bellard | #include <signal.h> |
25 | fdf9b3e8 | bellard | |
26 | fdf9b3e8 | bellard | #include "cpu.h" |
27 | fdf9b3e8 | bellard | #include "exec-all.h" |
28 | e96e2044 | ths | #include "hw/sh_intc.h" |
29 | fdf9b3e8 | bellard | |
30 | 355fb23d | pbrook | #if defined(CONFIG_USER_ONLY)
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31 | 355fb23d | pbrook | |
32 | 355fb23d | pbrook | void do_interrupt (CPUState *env)
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33 | 355fb23d | pbrook | { |
34 | 355fb23d | pbrook | env->exception_index = -1;
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35 | 355fb23d | pbrook | } |
36 | 355fb23d | pbrook | |
37 | 355fb23d | pbrook | int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
38 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
39 | 355fb23d | pbrook | { |
40 | 355fb23d | pbrook | env->tea = address; |
41 | ee0dc6d3 | Blue Swirl | env->exception_index = -1;
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42 | 355fb23d | pbrook | switch (rw) {
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43 | 355fb23d | pbrook | case 0: |
44 | 355fb23d | pbrook | env->exception_index = 0x0a0;
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45 | 355fb23d | pbrook | break;
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46 | 355fb23d | pbrook | case 1: |
47 | 355fb23d | pbrook | env->exception_index = 0x0c0;
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48 | 355fb23d | pbrook | break;
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49 | cf7055bd | aurel32 | case 2: |
50 | cf7055bd | aurel32 | env->exception_index = 0x0a0;
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51 | cf7055bd | aurel32 | break;
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52 | 355fb23d | pbrook | } |
53 | 355fb23d | pbrook | return 1; |
54 | 355fb23d | pbrook | } |
55 | 355fb23d | pbrook | |
56 | 3c1adf12 | edgar_igl | int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
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57 | 3c1adf12 | edgar_igl | { |
58 | 3c1adf12 | edgar_igl | /* For user mode, only U0 area is cachable. */
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59 | 679dee3c | edgar_igl | return !(addr & 0x80000000); |
60 | 3c1adf12 | edgar_igl | } |
61 | 3c1adf12 | edgar_igl | |
62 | 355fb23d | pbrook | #else /* !CONFIG_USER_ONLY */ |
63 | 355fb23d | pbrook | |
64 | fdf9b3e8 | bellard | #define MMU_OK 0 |
65 | fdf9b3e8 | bellard | #define MMU_ITLB_MISS (-1) |
66 | fdf9b3e8 | bellard | #define MMU_ITLB_MULTIPLE (-2) |
67 | fdf9b3e8 | bellard | #define MMU_ITLB_VIOLATION (-3) |
68 | fdf9b3e8 | bellard | #define MMU_DTLB_MISS_READ (-4) |
69 | fdf9b3e8 | bellard | #define MMU_DTLB_MISS_WRITE (-5) |
70 | fdf9b3e8 | bellard | #define MMU_DTLB_INITIAL_WRITE (-6) |
71 | fdf9b3e8 | bellard | #define MMU_DTLB_VIOLATION_READ (-7) |
72 | fdf9b3e8 | bellard | #define MMU_DTLB_VIOLATION_WRITE (-8) |
73 | fdf9b3e8 | bellard | #define MMU_DTLB_MULTIPLE (-9) |
74 | fdf9b3e8 | bellard | #define MMU_DTLB_MISS (-10) |
75 | cf7055bd | aurel32 | #define MMU_IADDR_ERROR (-11) |
76 | cf7055bd | aurel32 | #define MMU_DADDR_ERROR_READ (-12) |
77 | cf7055bd | aurel32 | #define MMU_DADDR_ERROR_WRITE (-13) |
78 | fdf9b3e8 | bellard | |
79 | fdf9b3e8 | bellard | void do_interrupt(CPUState * env)
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80 | fdf9b3e8 | bellard | { |
81 | e96e2044 | ths | int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
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82 | e96e2044 | ths | int do_exp, irq_vector = env->exception_index;
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83 | e96e2044 | ths | |
84 | e96e2044 | ths | /* prioritize exceptions over interrupts */
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85 | e96e2044 | ths | |
86 | e96e2044 | ths | do_exp = env->exception_index != -1;
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87 | e96e2044 | ths | do_irq = do_irq && (env->exception_index == -1);
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88 | e96e2044 | ths | |
89 | e96e2044 | ths | if (env->sr & SR_BL) {
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90 | e96e2044 | ths | if (do_exp && env->exception_index != 0x1e0) { |
91 | e96e2044 | ths | env->exception_index = 0x000; /* masked exception -> reset */ |
92 | e96e2044 | ths | } |
93 | 833ed386 | aurel32 | if (do_irq && !env->intr_at_halt) {
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94 | e96e2044 | ths | return; /* masked */ |
95 | e96e2044 | ths | } |
96 | 833ed386 | aurel32 | env->intr_at_halt = 0;
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97 | e96e2044 | ths | } |
98 | e96e2044 | ths | |
99 | e96e2044 | ths | if (do_irq) {
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100 | e96e2044 | ths | irq_vector = sh_intc_get_pending_vector(env->intc_handle, |
101 | e96e2044 | ths | (env->sr >> 4) & 0xf); |
102 | e96e2044 | ths | if (irq_vector == -1) { |
103 | e96e2044 | ths | return; /* masked */ |
104 | e96e2044 | ths | } |
105 | e96e2044 | ths | } |
106 | e96e2044 | ths | |
107 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_INT)) {
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108 | fdf9b3e8 | bellard | const char *expname; |
109 | fdf9b3e8 | bellard | switch (env->exception_index) {
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110 | fdf9b3e8 | bellard | case 0x0e0: |
111 | fdf9b3e8 | bellard | expname = "addr_error";
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112 | fdf9b3e8 | bellard | break;
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113 | fdf9b3e8 | bellard | case 0x040: |
114 | fdf9b3e8 | bellard | expname = "tlb_miss";
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115 | fdf9b3e8 | bellard | break;
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116 | fdf9b3e8 | bellard | case 0x0a0: |
117 | fdf9b3e8 | bellard | expname = "tlb_violation";
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118 | fdf9b3e8 | bellard | break;
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119 | fdf9b3e8 | bellard | case 0x180: |
120 | fdf9b3e8 | bellard | expname = "illegal_instruction";
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121 | fdf9b3e8 | bellard | break;
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122 | fdf9b3e8 | bellard | case 0x1a0: |
123 | fdf9b3e8 | bellard | expname = "slot_illegal_instruction";
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124 | fdf9b3e8 | bellard | break;
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125 | fdf9b3e8 | bellard | case 0x800: |
126 | fdf9b3e8 | bellard | expname = "fpu_disable";
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127 | fdf9b3e8 | bellard | break;
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128 | fdf9b3e8 | bellard | case 0x820: |
129 | fdf9b3e8 | bellard | expname = "slot_fpu";
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130 | fdf9b3e8 | bellard | break;
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131 | fdf9b3e8 | bellard | case 0x100: |
132 | fdf9b3e8 | bellard | expname = "data_write";
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133 | fdf9b3e8 | bellard | break;
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134 | fdf9b3e8 | bellard | case 0x060: |
135 | fdf9b3e8 | bellard | expname = "dtlb_miss_write";
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136 | fdf9b3e8 | bellard | break;
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137 | fdf9b3e8 | bellard | case 0x0c0: |
138 | fdf9b3e8 | bellard | expname = "dtlb_violation_write";
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139 | fdf9b3e8 | bellard | break;
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140 | fdf9b3e8 | bellard | case 0x120: |
141 | fdf9b3e8 | bellard | expname = "fpu_exception";
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142 | fdf9b3e8 | bellard | break;
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143 | fdf9b3e8 | bellard | case 0x080: |
144 | fdf9b3e8 | bellard | expname = "initial_page_write";
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145 | fdf9b3e8 | bellard | break;
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146 | fdf9b3e8 | bellard | case 0x160: |
147 | fdf9b3e8 | bellard | expname = "trapa";
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148 | fdf9b3e8 | bellard | break;
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149 | fdf9b3e8 | bellard | default:
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150 | e96e2044 | ths | expname = do_irq ? "interrupt" : "???"; |
151 | e96e2044 | ths | break;
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152 | fdf9b3e8 | bellard | } |
153 | 93fcfe39 | aliguori | qemu_log("exception 0x%03x [%s] raised\n",
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154 | 93fcfe39 | aliguori | irq_vector, expname); |
155 | 93fcfe39 | aliguori | log_cpu_state(env, 0);
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156 | fdf9b3e8 | bellard | } |
157 | fdf9b3e8 | bellard | |
158 | fdf9b3e8 | bellard | env->ssr = env->sr; |
159 | e96e2044 | ths | env->spc = env->pc; |
160 | fdf9b3e8 | bellard | env->sgr = env->gregs[15];
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161 | fdf9b3e8 | bellard | env->sr |= SR_BL | SR_MD | SR_RB; |
162 | fdf9b3e8 | bellard | |
163 | 274a9e70 | aurel32 | if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
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164 | 274a9e70 | aurel32 | /* Branch instruction should be executed again before delay slot. */
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165 | 274a9e70 | aurel32 | env->spc -= 2;
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166 | 274a9e70 | aurel32 | /* Clear flags for exception/interrupt routine. */
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167 | 274a9e70 | aurel32 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE); |
168 | 274a9e70 | aurel32 | } |
169 | 274a9e70 | aurel32 | if (env->flags & DELAY_SLOT_CLEARME)
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170 | 274a9e70 | aurel32 | env->flags = 0;
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171 | 274a9e70 | aurel32 | |
172 | e96e2044 | ths | if (do_exp) {
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173 | e96e2044 | ths | env->expevt = env->exception_index; |
174 | e96e2044 | ths | switch (env->exception_index) {
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175 | e96e2044 | ths | case 0x000: |
176 | e96e2044 | ths | case 0x020: |
177 | e96e2044 | ths | case 0x140: |
178 | e96e2044 | ths | env->sr &= ~SR_FD; |
179 | e96e2044 | ths | env->sr |= 0xf << 4; /* IMASK */ |
180 | e96e2044 | ths | env->pc = 0xa0000000;
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181 | e96e2044 | ths | break;
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182 | e96e2044 | ths | case 0x040: |
183 | e96e2044 | ths | case 0x060: |
184 | e96e2044 | ths | env->pc = env->vbr + 0x400;
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185 | e96e2044 | ths | break;
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186 | e96e2044 | ths | case 0x160: |
187 | e96e2044 | ths | env->spc += 2; /* special case for TRAPA */ |
188 | e96e2044 | ths | /* fall through */
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189 | e96e2044 | ths | default:
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190 | e96e2044 | ths | env->pc = env->vbr + 0x100;
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191 | e96e2044 | ths | break;
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192 | e96e2044 | ths | } |
193 | e96e2044 | ths | return;
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194 | e96e2044 | ths | } |
195 | e96e2044 | ths | |
196 | e96e2044 | ths | if (do_irq) {
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197 | e96e2044 | ths | env->intevt = irq_vector; |
198 | e96e2044 | ths | env->pc = env->vbr + 0x600;
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199 | e96e2044 | ths | return;
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200 | fdf9b3e8 | bellard | } |
201 | fdf9b3e8 | bellard | } |
202 | fdf9b3e8 | bellard | |
203 | fdf9b3e8 | bellard | static void update_itlb_use(CPUState * env, int itlbnb) |
204 | fdf9b3e8 | bellard | { |
205 | fdf9b3e8 | bellard | uint8_t or_mask = 0, and_mask = (uint8_t) - 1; |
206 | fdf9b3e8 | bellard | |
207 | fdf9b3e8 | bellard | switch (itlbnb) {
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208 | fdf9b3e8 | bellard | case 0: |
209 | ea2b542a | aurel32 | and_mask = 0x1f;
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210 | fdf9b3e8 | bellard | break;
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211 | fdf9b3e8 | bellard | case 1: |
212 | fdf9b3e8 | bellard | and_mask = 0xe7;
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213 | fdf9b3e8 | bellard | or_mask = 0x80;
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214 | fdf9b3e8 | bellard | break;
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215 | fdf9b3e8 | bellard | case 2: |
216 | fdf9b3e8 | bellard | and_mask = 0xfb;
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217 | fdf9b3e8 | bellard | or_mask = 0x50;
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218 | fdf9b3e8 | bellard | break;
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219 | fdf9b3e8 | bellard | case 3: |
220 | fdf9b3e8 | bellard | or_mask = 0x2c;
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221 | fdf9b3e8 | bellard | break;
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222 | fdf9b3e8 | bellard | } |
223 | fdf9b3e8 | bellard | |
224 | ea2b542a | aurel32 | env->mmucr &= (and_mask << 24) | 0x00ffffff; |
225 | fdf9b3e8 | bellard | env->mmucr |= (or_mask << 24);
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226 | fdf9b3e8 | bellard | } |
227 | fdf9b3e8 | bellard | |
228 | fdf9b3e8 | bellard | static int itlb_replacement(CPUState * env) |
229 | fdf9b3e8 | bellard | { |
230 | fdf9b3e8 | bellard | if ((env->mmucr & 0xe0000000) == 0xe0000000) |
231 | fdf9b3e8 | bellard | return 0; |
232 | ea2b542a | aurel32 | if ((env->mmucr & 0x98000000) == 0x18000000) |
233 | fdf9b3e8 | bellard | return 1; |
234 | fdf9b3e8 | bellard | if ((env->mmucr & 0x54000000) == 0x04000000) |
235 | fdf9b3e8 | bellard | return 2; |
236 | fdf9b3e8 | bellard | if ((env->mmucr & 0x2c000000) == 0x00000000) |
237 | fdf9b3e8 | bellard | return 3; |
238 | 43dc2a64 | Blue Swirl | cpu_abort(env, "Unhandled itlb_replacement");
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239 | fdf9b3e8 | bellard | } |
240 | fdf9b3e8 | bellard | |
241 | fdf9b3e8 | bellard | /* Find the corresponding entry in the right TLB
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242 | fdf9b3e8 | bellard | Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
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243 | fdf9b3e8 | bellard | */
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244 | fdf9b3e8 | bellard | static int find_tlb_entry(CPUState * env, target_ulong address, |
245 | fdf9b3e8 | bellard | tlb_t * entries, uint8_t nbtlb, int use_asid)
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246 | fdf9b3e8 | bellard | { |
247 | fdf9b3e8 | bellard | int match = MMU_DTLB_MISS;
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248 | fdf9b3e8 | bellard | uint32_t start, end; |
249 | fdf9b3e8 | bellard | uint8_t asid; |
250 | fdf9b3e8 | bellard | int i;
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251 | fdf9b3e8 | bellard | |
252 | fdf9b3e8 | bellard | asid = env->pteh & 0xff;
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253 | fdf9b3e8 | bellard | |
254 | fdf9b3e8 | bellard | for (i = 0; i < nbtlb; i++) { |
255 | fdf9b3e8 | bellard | if (!entries[i].v)
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256 | fdf9b3e8 | bellard | continue; /* Invalid entry */ |
257 | eeda6778 | aurel32 | if (!entries[i].sh && use_asid && entries[i].asid != asid)
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258 | fdf9b3e8 | bellard | continue; /* Bad ASID */ |
259 | fdf9b3e8 | bellard | start = (entries[i].vpn << 10) & ~(entries[i].size - 1); |
260 | fdf9b3e8 | bellard | end = start + entries[i].size - 1;
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261 | fdf9b3e8 | bellard | if (address >= start && address <= end) { /* Match */ |
262 | ea2b542a | aurel32 | if (match != MMU_DTLB_MISS)
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263 | fdf9b3e8 | bellard | return MMU_DTLB_MULTIPLE; /* Multiple match */ |
264 | fdf9b3e8 | bellard | match = i; |
265 | fdf9b3e8 | bellard | } |
266 | fdf9b3e8 | bellard | } |
267 | fdf9b3e8 | bellard | return match;
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268 | fdf9b3e8 | bellard | } |
269 | fdf9b3e8 | bellard | |
270 | 29e179bc | aurel32 | static void increment_urc(CPUState * env) |
271 | 29e179bc | aurel32 | { |
272 | 29e179bc | aurel32 | uint8_t urb, urc; |
273 | 29e179bc | aurel32 | |
274 | 29e179bc | aurel32 | /* Increment URC */
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275 | 29e179bc | aurel32 | urb = ((env->mmucr) >> 18) & 0x3f; |
276 | 29e179bc | aurel32 | urc = ((env->mmucr) >> 10) & 0x3f; |
277 | 29e179bc | aurel32 | urc++; |
278 | 927e3a4e | aurel32 | if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1)) |
279 | 29e179bc | aurel32 | urc = 0;
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280 | 29e179bc | aurel32 | env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); |
281 | 29e179bc | aurel32 | } |
282 | 29e179bc | aurel32 | |
283 | fdf9b3e8 | bellard | /* Find itlb entry - update itlb from utlb if necessary and asked for
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284 | fdf9b3e8 | bellard | Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
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285 | fdf9b3e8 | bellard | Update the itlb from utlb if update is not 0
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286 | fdf9b3e8 | bellard | */
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287 | ef7ec1c1 | aurel32 | static int find_itlb_entry(CPUState * env, target_ulong address, |
288 | ef7ec1c1 | aurel32 | int use_asid, int update) |
289 | fdf9b3e8 | bellard | { |
290 | fdf9b3e8 | bellard | int e, n;
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291 | fdf9b3e8 | bellard | |
292 | fdf9b3e8 | bellard | e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); |
293 | fdf9b3e8 | bellard | if (e == MMU_DTLB_MULTIPLE)
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294 | fdf9b3e8 | bellard | e = MMU_ITLB_MULTIPLE; |
295 | fdf9b3e8 | bellard | else if (e == MMU_DTLB_MISS && update) { |
296 | fdf9b3e8 | bellard | e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); |
297 | fdf9b3e8 | bellard | if (e >= 0) { |
298 | 06afe2c8 | aurel32 | tlb_t * ientry; |
299 | fdf9b3e8 | bellard | n = itlb_replacement(env); |
300 | 06afe2c8 | aurel32 | ientry = &env->itlb[n]; |
301 | 06afe2c8 | aurel32 | if (ientry->v) {
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302 | 5a25cc2b | Aurelien Jarno | tlb_flush_page(env, ientry->vpn << 10);
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303 | 06afe2c8 | aurel32 | } |
304 | 06afe2c8 | aurel32 | *ientry = env->utlb[e]; |
305 | fdf9b3e8 | bellard | e = n; |
306 | ea2b542a | aurel32 | } else if (e == MMU_DTLB_MISS) |
307 | ea2b542a | aurel32 | e = MMU_ITLB_MISS; |
308 | ea2b542a | aurel32 | } else if (e == MMU_DTLB_MISS) |
309 | ea2b542a | aurel32 | e = MMU_ITLB_MISS; |
310 | fdf9b3e8 | bellard | if (e >= 0) |
311 | fdf9b3e8 | bellard | update_itlb_use(env, e); |
312 | fdf9b3e8 | bellard | return e;
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313 | fdf9b3e8 | bellard | } |
314 | fdf9b3e8 | bellard | |
315 | fdf9b3e8 | bellard | /* Find utlb entry
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316 | fdf9b3e8 | bellard | Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
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317 | ef7ec1c1 | aurel32 | static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid) |
318 | fdf9b3e8 | bellard | { |
319 | 29e179bc | aurel32 | /* per utlb access */
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320 | 29e179bc | aurel32 | increment_urc(env); |
321 | fdf9b3e8 | bellard | |
322 | fdf9b3e8 | bellard | /* Return entry */
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323 | fdf9b3e8 | bellard | return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
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324 | fdf9b3e8 | bellard | } |
325 | fdf9b3e8 | bellard | |
326 | fdf9b3e8 | bellard | /* Match address against MMU
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327 | fdf9b3e8 | bellard | Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
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328 | fdf9b3e8 | bellard | MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
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329 | fdf9b3e8 | bellard | MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
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330 | cf7055bd | aurel32 | MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
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331 | cf7055bd | aurel32 | MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
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332 | fdf9b3e8 | bellard | */
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333 | fdf9b3e8 | bellard | static int get_mmu_address(CPUState * env, target_ulong * physical, |
334 | fdf9b3e8 | bellard | int *prot, target_ulong address,
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335 | fdf9b3e8 | bellard | int rw, int access_type) |
336 | fdf9b3e8 | bellard | { |
337 | cf7055bd | aurel32 | int use_asid, n;
|
338 | fdf9b3e8 | bellard | tlb_t *matching = NULL;
|
339 | fdf9b3e8 | bellard | |
340 | 06afe2c8 | aurel32 | use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0; |
341 | fdf9b3e8 | bellard | |
342 | cf7055bd | aurel32 | if (rw == 2) { |
343 | fdf9b3e8 | bellard | n = find_itlb_entry(env, address, use_asid, 1);
|
344 | fdf9b3e8 | bellard | if (n >= 0) { |
345 | fdf9b3e8 | bellard | matching = &env->itlb[n]; |
346 | 4d1e4ff6 | Aurelien Jarno | if (!(env->sr & SR_MD) && !(matching->pr & 2)) |
347 | fdf9b3e8 | bellard | n = MMU_ITLB_VIOLATION; |
348 | fdf9b3e8 | bellard | else
|
349 | 5a25cc2b | Aurelien Jarno | *prot = PAGE_EXEC; |
350 | fdf9b3e8 | bellard | } |
351 | fdf9b3e8 | bellard | } else {
|
352 | fdf9b3e8 | bellard | n = find_utlb_entry(env, address, use_asid); |
353 | fdf9b3e8 | bellard | if (n >= 0) { |
354 | fdf9b3e8 | bellard | matching = &env->utlb[n]; |
355 | 628b61a0 | Aurelien Jarno | if (!(env->sr & SR_MD) && !(matching->pr & 2)) { |
356 | 628b61a0 | Aurelien Jarno | n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
|
357 | 628b61a0 | Aurelien Jarno | MMU_DTLB_VIOLATION_READ; |
358 | 628b61a0 | Aurelien Jarno | } else if ((rw == 1) && !(matching->pr & 1)) { |
359 | 628b61a0 | Aurelien Jarno | n = MMU_DTLB_VIOLATION_WRITE; |
360 | 628b61a0 | Aurelien Jarno | } else if ((rw == 1) & !matching->d) { |
361 | 628b61a0 | Aurelien Jarno | n = MMU_DTLB_INITIAL_WRITE; |
362 | 628b61a0 | Aurelien Jarno | } else {
|
363 | 628b61a0 | Aurelien Jarno | *prot = PAGE_READ; |
364 | 628b61a0 | Aurelien Jarno | if ((matching->pr & 1) && matching->d) { |
365 | 628b61a0 | Aurelien Jarno | *prot |= PAGE_WRITE; |
366 | 628b61a0 | Aurelien Jarno | } |
367 | 628b61a0 | Aurelien Jarno | } |
368 | fdf9b3e8 | bellard | } else if (n == MMU_DTLB_MISS) { |
369 | cf7055bd | aurel32 | n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
|
370 | fdf9b3e8 | bellard | MMU_DTLB_MISS_READ; |
371 | fdf9b3e8 | bellard | } |
372 | fdf9b3e8 | bellard | } |
373 | fdf9b3e8 | bellard | if (n >= 0) { |
374 | 628b61a0 | Aurelien Jarno | n = MMU_OK; |
375 | fdf9b3e8 | bellard | *physical = ((matching->ppn << 10) & ~(matching->size - 1)) | |
376 | fdf9b3e8 | bellard | (address & (matching->size - 1));
|
377 | fdf9b3e8 | bellard | } |
378 | fdf9b3e8 | bellard | return n;
|
379 | fdf9b3e8 | bellard | } |
380 | fdf9b3e8 | bellard | |
381 | ef7ec1c1 | aurel32 | static int get_physical_address(CPUState * env, target_ulong * physical, |
382 | ef7ec1c1 | aurel32 | int *prot, target_ulong address,
|
383 | ef7ec1c1 | aurel32 | int rw, int access_type) |
384 | fdf9b3e8 | bellard | { |
385 | fdf9b3e8 | bellard | /* P1, P2 and P4 areas do not use translation */
|
386 | fdf9b3e8 | bellard | if ((address >= 0x80000000 && address < 0xc0000000) || |
387 | fdf9b3e8 | bellard | address >= 0xe0000000) {
|
388 | fdf9b3e8 | bellard | if (!(env->sr & SR_MD)
|
389 | 03e3b61e | Aurelien Jarno | && (address < 0xe0000000 || address >= 0xe4000000)) { |
390 | fdf9b3e8 | bellard | /* Unauthorized access in user mode (only store queues are available) */
|
391 | fdf9b3e8 | bellard | fprintf(stderr, "Unauthorized access\n");
|
392 | cf7055bd | aurel32 | if (rw == 0) |
393 | cf7055bd | aurel32 | return MMU_DADDR_ERROR_READ;
|
394 | cf7055bd | aurel32 | else if (rw == 1) |
395 | cf7055bd | aurel32 | return MMU_DADDR_ERROR_WRITE;
|
396 | cf7055bd | aurel32 | else
|
397 | cf7055bd | aurel32 | return MMU_IADDR_ERROR;
|
398 | fdf9b3e8 | bellard | } |
399 | 29e179bc | aurel32 | if (address >= 0x80000000 && address < 0xc0000000) { |
400 | 29e179bc | aurel32 | /* Mask upper 3 bits for P1 and P2 areas */
|
401 | 29e179bc | aurel32 | *physical = address & 0x1fffffff;
|
402 | 29e179bc | aurel32 | } else {
|
403 | 29e179bc | aurel32 | *physical = address; |
404 | 29e179bc | aurel32 | } |
405 | 5a25cc2b | Aurelien Jarno | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
406 | fdf9b3e8 | bellard | return MMU_OK;
|
407 | fdf9b3e8 | bellard | } |
408 | fdf9b3e8 | bellard | |
409 | fdf9b3e8 | bellard | /* If MMU is disabled, return the corresponding physical page */
|
410 | fdf9b3e8 | bellard | if (!env->mmucr & MMUCR_AT) {
|
411 | fdf9b3e8 | bellard | *physical = address & 0x1FFFFFFF;
|
412 | 5a25cc2b | Aurelien Jarno | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
413 | fdf9b3e8 | bellard | return MMU_OK;
|
414 | fdf9b3e8 | bellard | } |
415 | fdf9b3e8 | bellard | |
416 | fdf9b3e8 | bellard | /* We need to resort to the MMU */
|
417 | fdf9b3e8 | bellard | return get_mmu_address(env, physical, prot, address, rw, access_type);
|
418 | fdf9b3e8 | bellard | } |
419 | fdf9b3e8 | bellard | |
420 | fdf9b3e8 | bellard | int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
421 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
422 | fdf9b3e8 | bellard | { |
423 | 0f3f1ec7 | Aurelien Jarno | target_ulong physical; |
424 | fdf9b3e8 | bellard | int prot, ret, access_type;
|
425 | fdf9b3e8 | bellard | |
426 | fdf9b3e8 | bellard | access_type = ACCESS_INT; |
427 | fdf9b3e8 | bellard | ret = |
428 | fdf9b3e8 | bellard | get_physical_address(env, &physical, &prot, address, rw, |
429 | fdf9b3e8 | bellard | access_type); |
430 | fdf9b3e8 | bellard | |
431 | fdf9b3e8 | bellard | if (ret != MMU_OK) {
|
432 | fdf9b3e8 | bellard | env->tea = address; |
433 | fdf9b3e8 | bellard | switch (ret) {
|
434 | fdf9b3e8 | bellard | case MMU_ITLB_MISS:
|
435 | fdf9b3e8 | bellard | case MMU_DTLB_MISS_READ:
|
436 | fdf9b3e8 | bellard | env->exception_index = 0x040;
|
437 | fdf9b3e8 | bellard | break;
|
438 | fdf9b3e8 | bellard | case MMU_DTLB_MULTIPLE:
|
439 | fdf9b3e8 | bellard | case MMU_ITLB_MULTIPLE:
|
440 | fdf9b3e8 | bellard | env->exception_index = 0x140;
|
441 | fdf9b3e8 | bellard | break;
|
442 | fdf9b3e8 | bellard | case MMU_ITLB_VIOLATION:
|
443 | fdf9b3e8 | bellard | env->exception_index = 0x0a0;
|
444 | fdf9b3e8 | bellard | break;
|
445 | fdf9b3e8 | bellard | case MMU_DTLB_MISS_WRITE:
|
446 | fdf9b3e8 | bellard | env->exception_index = 0x060;
|
447 | fdf9b3e8 | bellard | break;
|
448 | fdf9b3e8 | bellard | case MMU_DTLB_INITIAL_WRITE:
|
449 | fdf9b3e8 | bellard | env->exception_index = 0x080;
|
450 | fdf9b3e8 | bellard | break;
|
451 | fdf9b3e8 | bellard | case MMU_DTLB_VIOLATION_READ:
|
452 | fdf9b3e8 | bellard | env->exception_index = 0x0a0;
|
453 | fdf9b3e8 | bellard | break;
|
454 | fdf9b3e8 | bellard | case MMU_DTLB_VIOLATION_WRITE:
|
455 | fdf9b3e8 | bellard | env->exception_index = 0x0c0;
|
456 | fdf9b3e8 | bellard | break;
|
457 | cf7055bd | aurel32 | case MMU_IADDR_ERROR:
|
458 | cf7055bd | aurel32 | case MMU_DADDR_ERROR_READ:
|
459 | cf7055bd | aurel32 | env->exception_index = 0x0c0;
|
460 | cf7055bd | aurel32 | break;
|
461 | cf7055bd | aurel32 | case MMU_DADDR_ERROR_WRITE:
|
462 | cf7055bd | aurel32 | env->exception_index = 0x100;
|
463 | cf7055bd | aurel32 | break;
|
464 | fdf9b3e8 | bellard | default:
|
465 | 43dc2a64 | Blue Swirl | cpu_abort(env, "Unhandled MMU fault");
|
466 | fdf9b3e8 | bellard | } |
467 | fdf9b3e8 | bellard | return 1; |
468 | fdf9b3e8 | bellard | } |
469 | fdf9b3e8 | bellard | |
470 | 0f3f1ec7 | Aurelien Jarno | address &= TARGET_PAGE_MASK; |
471 | 0f3f1ec7 | Aurelien Jarno | physical &= TARGET_PAGE_MASK; |
472 | fdf9b3e8 | bellard | |
473 | d4c430a8 | Paul Brook | tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); |
474 | d4c430a8 | Paul Brook | return 0; |
475 | fdf9b3e8 | bellard | } |
476 | 355fb23d | pbrook | |
477 | c227f099 | Anthony Liguori | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
478 | 355fb23d | pbrook | { |
479 | 355fb23d | pbrook | target_ulong physical; |
480 | 355fb23d | pbrook | int prot;
|
481 | 355fb23d | pbrook | |
482 | cf7055bd | aurel32 | get_physical_address(env, &physical, &prot, addr, 0, 0); |
483 | 355fb23d | pbrook | return physical;
|
484 | 355fb23d | pbrook | } |
485 | 355fb23d | pbrook | |
486 | ef7ec1c1 | aurel32 | void cpu_load_tlb(CPUSH4State * env)
|
487 | ea2b542a | aurel32 | { |
488 | ea2b542a | aurel32 | int n = cpu_mmucr_urc(env->mmucr);
|
489 | ea2b542a | aurel32 | tlb_t * entry = &env->utlb[n]; |
490 | ea2b542a | aurel32 | |
491 | 06afe2c8 | aurel32 | if (entry->v) {
|
492 | 06afe2c8 | aurel32 | /* Overwriting valid entry in utlb. */
|
493 | 06afe2c8 | aurel32 | target_ulong address = entry->vpn << 10;
|
494 | 5a25cc2b | Aurelien Jarno | tlb_flush_page(env, address); |
495 | 06afe2c8 | aurel32 | } |
496 | 06afe2c8 | aurel32 | |
497 | ea2b542a | aurel32 | /* Take values into cpu status from registers. */
|
498 | ea2b542a | aurel32 | entry->asid = (uint8_t)cpu_pteh_asid(env->pteh); |
499 | ea2b542a | aurel32 | entry->vpn = cpu_pteh_vpn(env->pteh); |
500 | ea2b542a | aurel32 | entry->v = (uint8_t)cpu_ptel_v(env->ptel); |
501 | ea2b542a | aurel32 | entry->ppn = cpu_ptel_ppn(env->ptel); |
502 | ea2b542a | aurel32 | entry->sz = (uint8_t)cpu_ptel_sz(env->ptel); |
503 | ea2b542a | aurel32 | switch (entry->sz) {
|
504 | ea2b542a | aurel32 | case 0: /* 00 */ |
505 | ea2b542a | aurel32 | entry->size = 1024; /* 1K */ |
506 | ea2b542a | aurel32 | break;
|
507 | ea2b542a | aurel32 | case 1: /* 01 */ |
508 | ea2b542a | aurel32 | entry->size = 1024 * 4; /* 4K */ |
509 | ea2b542a | aurel32 | break;
|
510 | ea2b542a | aurel32 | case 2: /* 10 */ |
511 | ea2b542a | aurel32 | entry->size = 1024 * 64; /* 64K */ |
512 | ea2b542a | aurel32 | break;
|
513 | ea2b542a | aurel32 | case 3: /* 11 */ |
514 | ea2b542a | aurel32 | entry->size = 1024 * 1024; /* 1M */ |
515 | ea2b542a | aurel32 | break;
|
516 | ea2b542a | aurel32 | default:
|
517 | 43dc2a64 | Blue Swirl | cpu_abort(env, "Unhandled load_tlb");
|
518 | ea2b542a | aurel32 | break;
|
519 | ea2b542a | aurel32 | } |
520 | ea2b542a | aurel32 | entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); |
521 | ea2b542a | aurel32 | entry->c = (uint8_t)cpu_ptel_c(env->ptel); |
522 | ea2b542a | aurel32 | entry->pr = (uint8_t)cpu_ptel_pr(env->ptel); |
523 | ea2b542a | aurel32 | entry->d = (uint8_t)cpu_ptel_d(env->ptel); |
524 | ea2b542a | aurel32 | entry->wt = (uint8_t)cpu_ptel_wt(env->ptel); |
525 | ea2b542a | aurel32 | entry->sa = (uint8_t)cpu_ptea_sa(env->ptea); |
526 | ea2b542a | aurel32 | entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); |
527 | ea2b542a | aurel32 | } |
528 | ea2b542a | aurel32 | |
529 | e0bcb9ca | Aurelien Jarno | void cpu_sh4_invalidate_tlb(CPUSH4State *s)
|
530 | e0bcb9ca | Aurelien Jarno | { |
531 | e0bcb9ca | Aurelien Jarno | int i;
|
532 | e0bcb9ca | Aurelien Jarno | |
533 | e0bcb9ca | Aurelien Jarno | /* UTLB */
|
534 | e0bcb9ca | Aurelien Jarno | for (i = 0; i < UTLB_SIZE; i++) { |
535 | e0bcb9ca | Aurelien Jarno | tlb_t * entry = &s->utlb[i]; |
536 | e0bcb9ca | Aurelien Jarno | entry->v = 0;
|
537 | e0bcb9ca | Aurelien Jarno | } |
538 | e0bcb9ca | Aurelien Jarno | /* ITLB */
|
539 | e0bcb9ca | Aurelien Jarno | for (i = 0; i < UTLB_SIZE; i++) { |
540 | e0bcb9ca | Aurelien Jarno | tlb_t * entry = &s->utlb[i]; |
541 | e0bcb9ca | Aurelien Jarno | entry->v = 0;
|
542 | e0bcb9ca | Aurelien Jarno | } |
543 | e0bcb9ca | Aurelien Jarno | |
544 | e0bcb9ca | Aurelien Jarno | tlb_flush(s, 1);
|
545 | e0bcb9ca | Aurelien Jarno | } |
546 | e0bcb9ca | Aurelien Jarno | |
547 | c227f099 | Anthony Liguori | void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
|
548 | 29e179bc | aurel32 | uint32_t mem_value) |
549 | 29e179bc | aurel32 | { |
550 | 29e179bc | aurel32 | int associate = addr & 0x0000080; |
551 | 29e179bc | aurel32 | uint32_t vpn = (mem_value & 0xfffffc00) >> 10; |
552 | 29e179bc | aurel32 | uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9); |
553 | 29e179bc | aurel32 | uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); |
554 | 29e179bc | aurel32 | uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
|
555 | eeda6778 | aurel32 | int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0; |
556 | 29e179bc | aurel32 | |
557 | 29e179bc | aurel32 | if (associate) {
|
558 | 29e179bc | aurel32 | int i;
|
559 | 29e179bc | aurel32 | tlb_t * utlb_match_entry = NULL;
|
560 | 29e179bc | aurel32 | int needs_tlb_flush = 0; |
561 | 29e179bc | aurel32 | |
562 | 29e179bc | aurel32 | /* search UTLB */
|
563 | 29e179bc | aurel32 | for (i = 0; i < UTLB_SIZE; i++) { |
564 | 29e179bc | aurel32 | tlb_t * entry = &s->utlb[i]; |
565 | 29e179bc | aurel32 | if (!entry->v)
|
566 | 29e179bc | aurel32 | continue;
|
567 | 29e179bc | aurel32 | |
568 | eeda6778 | aurel32 | if (entry->vpn == vpn
|
569 | eeda6778 | aurel32 | && (!use_asid || entry->asid == asid || entry->sh)) { |
570 | 29e179bc | aurel32 | if (utlb_match_entry) {
|
571 | 29e179bc | aurel32 | /* Multiple TLB Exception */
|
572 | 29e179bc | aurel32 | s->exception_index = 0x140;
|
573 | 29e179bc | aurel32 | s->tea = addr; |
574 | 29e179bc | aurel32 | break;
|
575 | 29e179bc | aurel32 | } |
576 | 29e179bc | aurel32 | if (entry->v && !v)
|
577 | 29e179bc | aurel32 | needs_tlb_flush = 1;
|
578 | 29e179bc | aurel32 | entry->v = v; |
579 | 29e179bc | aurel32 | entry->d = d; |
580 | 29e179bc | aurel32 | utlb_match_entry = entry; |
581 | 29e179bc | aurel32 | } |
582 | 29e179bc | aurel32 | increment_urc(s); /* per utlb access */
|
583 | 29e179bc | aurel32 | } |
584 | 29e179bc | aurel32 | |
585 | 29e179bc | aurel32 | /* search ITLB */
|
586 | 29e179bc | aurel32 | for (i = 0; i < ITLB_SIZE; i++) { |
587 | 29e179bc | aurel32 | tlb_t * entry = &s->itlb[i]; |
588 | eeda6778 | aurel32 | if (entry->vpn == vpn
|
589 | eeda6778 | aurel32 | && (!use_asid || entry->asid == asid || entry->sh)) { |
590 | 29e179bc | aurel32 | if (entry->v && !v)
|
591 | 29e179bc | aurel32 | needs_tlb_flush = 1;
|
592 | 29e179bc | aurel32 | if (utlb_match_entry)
|
593 | 29e179bc | aurel32 | *entry = *utlb_match_entry; |
594 | 29e179bc | aurel32 | else
|
595 | 29e179bc | aurel32 | entry->v = v; |
596 | 29e179bc | aurel32 | break;
|
597 | 29e179bc | aurel32 | } |
598 | 29e179bc | aurel32 | } |
599 | 29e179bc | aurel32 | |
600 | 29e179bc | aurel32 | if (needs_tlb_flush)
|
601 | 29e179bc | aurel32 | tlb_flush_page(s, vpn << 10);
|
602 | 29e179bc | aurel32 | |
603 | 29e179bc | aurel32 | } else {
|
604 | 29e179bc | aurel32 | int index = (addr & 0x00003f00) >> 8; |
605 | 29e179bc | aurel32 | tlb_t * entry = &s->utlb[index]; |
606 | 29e179bc | aurel32 | if (entry->v) {
|
607 | 29e179bc | aurel32 | /* Overwriting valid entry in utlb. */
|
608 | 29e179bc | aurel32 | target_ulong address = entry->vpn << 10;
|
609 | 5a25cc2b | Aurelien Jarno | tlb_flush_page(s, address); |
610 | 29e179bc | aurel32 | } |
611 | 29e179bc | aurel32 | entry->asid = asid; |
612 | 29e179bc | aurel32 | entry->vpn = vpn; |
613 | 29e179bc | aurel32 | entry->d = d; |
614 | 29e179bc | aurel32 | entry->v = v; |
615 | 29e179bc | aurel32 | increment_urc(s); |
616 | 29e179bc | aurel32 | } |
617 | 29e179bc | aurel32 | } |
618 | 29e179bc | aurel32 | |
619 | 852d481f | edgar_igl | int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
|
620 | 852d481f | edgar_igl | { |
621 | 852d481f | edgar_igl | int n;
|
622 | 852d481f | edgar_igl | int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0; |
623 | 852d481f | edgar_igl | |
624 | 852d481f | edgar_igl | /* check area */
|
625 | 852d481f | edgar_igl | if (env->sr & SR_MD) {
|
626 | 852d481f | edgar_igl | /* For previledged mode, P2 and P4 area is not cachable. */
|
627 | 852d481f | edgar_igl | if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr) |
628 | 852d481f | edgar_igl | return 0; |
629 | 852d481f | edgar_igl | } else {
|
630 | 852d481f | edgar_igl | /* For user mode, only U0 area is cachable. */
|
631 | 852d481f | edgar_igl | if (0x80000000 <= addr) |
632 | 852d481f | edgar_igl | return 0; |
633 | 852d481f | edgar_igl | } |
634 | 852d481f | edgar_igl | |
635 | 852d481f | edgar_igl | /*
|
636 | 852d481f | edgar_igl | * TODO : Evaluate CCR and check if the cache is on or off.
|
637 | 852d481f | edgar_igl | * Now CCR is not in CPUSH4State, but in SH7750State.
|
638 | 852d481f | edgar_igl | * When you move the ccr inot CPUSH4State, the code will be
|
639 | 852d481f | edgar_igl | * as follows.
|
640 | 852d481f | edgar_igl | */
|
641 | 852d481f | edgar_igl | #if 0
|
642 | 852d481f | edgar_igl | /* check if operand cache is enabled or not. */
|
643 | 852d481f | edgar_igl | if (!(env->ccr & 1))
|
644 | 852d481f | edgar_igl | return 0;
|
645 | 852d481f | edgar_igl | #endif
|
646 | 852d481f | edgar_igl | |
647 | 852d481f | edgar_igl | /* if MMU is off, no check for TLB. */
|
648 | 852d481f | edgar_igl | if (env->mmucr & MMUCR_AT)
|
649 | 852d481f | edgar_igl | return 1; |
650 | 852d481f | edgar_igl | |
651 | 852d481f | edgar_igl | /* check TLB */
|
652 | 852d481f | edgar_igl | n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid); |
653 | 852d481f | edgar_igl | if (n >= 0) |
654 | 852d481f | edgar_igl | return env->itlb[n].c;
|
655 | 852d481f | edgar_igl | |
656 | 852d481f | edgar_igl | n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid); |
657 | 852d481f | edgar_igl | if (n >= 0) |
658 | 852d481f | edgar_igl | return env->utlb[n].c;
|
659 | 852d481f | edgar_igl | |
660 | 852d481f | edgar_igl | return 0; |
661 | 852d481f | edgar_igl | } |
662 | 852d481f | edgar_igl | |
663 | 355fb23d | pbrook | #endif |