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# Date Author Comment
a88790a1 07/03/2010 09:48 am Paolo Bonzini

remove exec-all.h inclusion from cpu.h

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Blue Swirl <>

10eb0cc0 07/03/2010 09:48 am Paolo Bonzini

move cpu_pc_from_tb to target-*/exec.h

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Blue Swirl <>

bb42e28b 07/02/2010 12:45 am Chih-Min Chao

target-arm: fix addsub/subadd implementation

Signed-off-by: Chih-Min Chao <>
Signed-off-by: Aurelien Jarno <>

ed89a2f1 07/02/2010 12:45 am Chih-Min Chao

target-arm : fix thumb2 parallel add/sub opcode decoding

Signed-off-by: Chih-Min Chao <>
Signed-off-by: Aurelien Jarno <>

4c4fd3f8 07/02/2010 12:45 am Chih-Min Chao

target-arm : fix parallel saturated subtraction implementation

Signed-off-by: Chih-Min Chao <>
Signed-off-by: Aurelien Jarno <>

41ba8341 06/11/2010 10:37 pm Paul Brook

NEON vldN optimization

When combining multiple values as part of a NEON array load, do explcit
shift/or rather than using gen_bfi. This voids redundant mask
operations.

Signed-off-by: Paul Brook <>

e03c22a9 05/31/2010 08:40 pm Lars Munch

arm: fix arm kernel boot for non zero start addr

Booting an arm kernel has been broken a while when booting from non zero start
address. This is due to the order of events: board init loads the kernel and
sets register 15 to the start address and then qemu_system_reset reset the cpu...

9ba8c3f4 05/28/2010 10:25 pm Lars Munch

arm: prevent coprocessor IO reset

This prevent coprocessor IO structure from being reset on cpu reset. This was
a problem for PXA which uses coprocessor 6 and 14.

Signed-off-by: Lars Munch <>
Signed-off-by: Aurelien Jarno <>

22ed1d34 04/25/2010 10:31 pm Blue Swirl

arm: remove dead assignments, spotted by clang analyzer

Value stored is never read.

Signed-off-by: Blue Swirl <>

8e31209e 04/08/2010 10:12 pm Juha Riihimäki

target-arm: fix neon vmon/vmvn with modified immediate

Signed-Off-By: Riku Voipio <>
Signed-off-by: Juha Riihimäki <>
Signed-off-by: Aurelien Jarno <>

d9968827 04/08/2010 12:11 pm Lars Munch

target-arm: resource leak fixes for iwmmxt disassemble

This patch fixes few resource leaks in the iwmmxt disassemble.

Signed-off-by: Lars Munch <>
Signed-off-by: Aurelien Jarno <>

4f78c9ad 04/05/2010 09:56 pm Paul Brook

Fix arm-linux-user

Only include hw/loader.h from target-arm/helper.c when building for
system emulation.

Signed-off-by: Paul Brook <>

983fe826 04/05/2010 09:43 pm Paul Brook

ARMv7-M reset fixes

Move ARMv7-M PC/SP initialization to the CPU reset routine. Add a board
reset routine to call this. Also load values directly from ROM as
images have not been copied yet.

Avoid clearing the NVIC pointer on cpu reset.

Signed-off-by: Paul Brook <>

3ad493fc 03/27/2010 03:14 pm Rabin Vincent

target-arm: disable PAGE_EXEC for XN pages

Don't set PAGE_EXEC for XN pages, to avoid a bypass of XN protection
checking if the page is already in the TLB.

Signed-off-by: Rabin Vincent <>
Signed-off-by: Aurelien Jarno <>

bedd2912 03/23/2010 11:10 pm Johan Bengtsson

target-arm: Fix handling of AL condition in IT instruction

Do not try to insert a conditional jump over next instruction when the
condition code is AL as this will trigger an internal error.

Signed-off-by: Johan Bengtsson <>
Signed-off-by: Aurelien Jarno <>

d4c430a8 03/17/2010 04:44 am Paul Brook

Large page TLB flush

QEMU uses a fixed page size for the CPU TLB. If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate...

ea825eee 03/13/2010 01:01 pm Adam Lackorzynski

target-arm: make RFE usable with any register

The rfe instruction can be used with any register, not just sp. Adjust the
condition check accordingly.

Signed-off-by: Adam Lackorzynski <>
Signed-off-by: Aurelien Jarno <>

4fcc562b 03/12/2010 08:34 pm Paul Brook

Remove cpu_get_phys_page_debug from userspace emulation

cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <>

52705890 03/12/2010 06:28 pm Richard Henderson

Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.

Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha. This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place....

a990f58f 03/07/2010 12:22 am Adam Lackorzynski

target-arm: Fix missing 'return' in SRS handling.

There's a return missing in the srs handling which leads to srs always being
treated an an invalid op.

Signed-off-by: Adam Lackorzynski <>
Signed-off-by: Aurelien Jarno <>

30d11a2a 02/28/2010 08:30 pm Juha Riihimäki

target-arm: neon vshll instruction fix

implementation only widened the 32bit source vector elements into a
64bit destination vector but forgot to perform the actual shifting
operation.

Signed-off-by: Juha Riihimäki <>
Signed-off-by: Riku Voipio <>...

79b0e534 02/28/2010 08:30 pm Riku Voipio

target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHN

The rounding/truncating options were inverted. truncating
was done when rounding was meant and vice verse.

Signed-off-by: Riku Voipio <>
Acked-by: Laurent Desnogues <>...

c5883be2 02/23/2010 04:45 pm Paul Brook

ARM CP15 tls fix

Fix temporary handling in cp15 tls register load/store.

Signed-off-by: Paul Brook <>

30a8cac1 02/19/2010 05:20 pm Rabin Vincent

target-arm: support thumb exception handlers

When handling an exception, switch to the correct mode based on the
Thumb Exception (TE) bit in the SCTLR.

Signed-off-by: Rabin Vincent <>

b8b45b68 02/19/2010 03:38 pm Rabin Vincent

target-arm: implement Thumb-2 exception return

Support the "subs pc, lr" Thumb-2 exception return instruction.

Signed-off-by: Rabin Vincent <>
Signed-off-by: Paul Brook <>

fa26df03 02/19/2010 03:38 pm Rabin Vincent

target-arm: fix thumb CPS

The Thumb CPS currently does not work correctly: CPSID touches more bits
than the instruction wants to, and CPSIE does nothing. Fix it by
passing the correct mask (the "affect" bits) and value.

Signed-off-by: Rabin Vincent <>

3f26c122 02/06/2010 06:19 pm Riku Voipio

target-arm: refactor cp15.c13 register access

Access the cp15.c13 TLS registers directly with TCG ops instead of with
a slow helper. If the the cp15 read/write was not TLS register access,
fall back to the cp15 helper.

This makes accessing __thread variables in linux-user when apps are compiled...

49a945a3 01/20/2010 12:31 am Paolo Bonzini

kill regs_to_env and env_to_regs

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Anthony Liguori <>

502e64fe 12/24/2009 01:18 am Aurelien Jarno

target-arm: fix strexd

Signed-off-by: Aurelien Jarno <>

426f5abc 11/22/2009 11:35 pm Paul Brook

ARM atomic ops rewrite

Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.

Signed-off-by: Paul Brook <>

60011498 11/19/2009 06:45 pm Paul Brook

ARM FP16 support

Implement the ARM VFP half precision floating point extensions.

Signed-off-by: Paul Brook <>

10055562 11/19/2009 06:45 pm Paul Brook

ARM Cortex-A9 cpu support

Basic Cortex-A9 support.

Signed-off-by: Paul Brook <>

f669df27 10/27/2009 10:46 am Aurelien Jarno

target-arm: use native tcg-ops for ror/bic/vorn

Acked-by: Laurent Desnogues <>
Signed-off-by: Aurelien Jarno <>

2301db49 10/27/2009 10:46 am Juha Riihimäki

target-arm: fix neon vshrn/vrshrn ops

In the existing code shift value is clobbered during the pass loop.
This patch changes the code so that it stores the intermediate
result in the target neon register directly and eliminates the need
to use a temporary to hold the intermediate value thus leaving the...

84496233 10/27/2009 10:46 am Juha Riihimäki

target-arm: add support for neon vld1.64/vst1.64 instructions

Add support for NEON vld1.64 and vst1.64 instructions. This patch is
revised to follow more closely the specification and raises
undefined exception if 64bit element size is used for vld2/vst2 or...

71b3c3de 10/27/2009 10:46 am Juha Riihimäki

target-arm: allow modifying vfp fpexc en bit only

All other bits except for the EN in the VFP FPEXC register are defined
as subarchitecture specific and real functionality for any of the
other bits has not been implemented in QEMU. However, current code
allows modifying all bits in the VFP FPEXC register leading to...

ca9a32e4 10/27/2009 10:46 am Juha Riihimäki

target-arm: fix neon vsri, vshl and vsli ops

Shift by immediate value is incorrectly overwritten by a temporary
variable in the processing of NEON vsri, vshl and vsli instructions.
This patch has been revised to also include a fix for the special
case where the code would previously try to shift an integer value...

50f67e95 10/27/2009 10:46 am Juha Riihimäki

target-arm: fix neon shift helper functions

Current code is broken at least on recent compilers, comparison
between signed and unsigned types yield incorrect code and render
the neon shift helper functions defunct. This is the third revision
of this patch, casting all comparisons with the sizeof operator to...

25aeb69b 10/26/2009 09:36 pm Juha Riihimäki

target-arm: fix incorrect temporary variable freeing

tmp4 and tmp5 temporary variables are allocated using tcg_const_i32
but incorrectly released using dead_tmp which will cause resource
leak tracking to report false leaks.

Signed-off-by: Juha Riihimäki <>...

7b2919a0 10/23/2009 06:22 pm Juha.Riihimaki@nokia.com

target-arm: optimize thumb 32-bit multiply

Current implementation of thumb mul instruction is implemented as a
32x32->64 multiply which then uses only 32 least significant bits of
the result. Replace that with a simple 32x32->32 multiply.

Signed-off-by: Juha Riihimäki <>...

b75263d6 10/23/2009 06:11 pm Juha Riihimäki

target-arm: cleanup internal resource leaks

Revised patch for getting rid of tcg temporary variable leaks in
target-arm/translate.c. This version also includes the leak patch for
gen_set_cpsr macro, now converted as a static inline function, which I
sent earlier as a separate patch on top of this patch....

7bbcb0af 10/23/2009 01:05 am Aurelien Jarno

target-arm: use clz32() instead of a for loop

Signed-off-by: Aurelien Jarno <>
Acked-by: Laurent Desnogues <>

686eeb93 10/23/2009 01:05 am Aurelien Jarno

target-arm: fix sdiv helper

(INT32_MIN / -1) triggers an overflow, and the result depends on the
host architecture (INT32_MIN on arm, -1 on ppc, SIGFPE on x86). Use a
test to output the correct value.

Signed-off-by: Aurelien Jarno <>...

dcc65026 10/18/2009 05:00 pm Aurelien Jarno

target-arm: fix bugs introduced by 1b2b1e547bd912b7d3c4863d0a0f75f6f38330ed

Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.

Signed-off-by: Aurelien Jarno <>

98a46317 10/18/2009 04:53 pm Aurelien Jarno

target-arm: fix bugs introduced by 3174f8e91fecf8756e861d1febb049f3c619a2c7

Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.

Signed-off-by: Aurelien Jarno <>

b567b38c 10/18/2009 12:53 am Aurelien Jarno

target-arm: remove T0 and T1

Signed-off-by: Aurelien Jarno <>

747a651e 10/18/2009 12:52 am Filip Navara

target-arm: remove cpu_T for ARM once and for all

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

a6445c52 10/18/2009 12:52 am Filip Navara

target-arm: convert gen_lookup_tb not to use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

19457615 10/18/2009 12:52 am Filip Navara

target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCG

The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16
helpers used fixed registers to return values. This patch replaces that with
TCG code, so T0/T1 is no longer directly used by the helper functions....

15bb4eac 10/18/2009 12:52 am Filip Navara

target-arm: fix TANDC and TORC instructions

Uninitialized register was used instead of proper TCG variable.

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

396e467c 10/18/2009 12:52 am Filip Navara

target-arm: replace thumb usage of cpu_T registers by proper register allocations

The goal is eventually to get rid of all cpu_T register usage and to use
just short-lived tmp/tmp2 registers. This patch converts all the places where
cpu_T was used in the Thumb code and replaces it with explicit TCG register...

3174f8e9 10/18/2009 12:52 am Filip Navara

target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

dd8fbd78 10/18/2009 12:52 am Filip Navara

target-arm: convert disas_neon_data_insn and helpers not to use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

1b2b1e54 10/18/2009 12:52 am Filip Navara

target-arm: convert disas_neon_ls_insn not to use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

3a554c0f 10/18/2009 12:52 am Filip Navara

target-arm: convert disas_dsp_insn not use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

da6b5335 10/18/2009 12:52 am Filip Navara

target-arm: convert disas_iwmmxt_insn not to use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

312eea9f 10/18/2009 12:52 am Filip Navara

target-arm: convert VFP not to use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

155c3eac 10/18/2009 12:52 am Filip Navara

target-arm: use tcg_global_mem_new_i32 to allocate registers

Currently each read/write of ARM register involves a LD/ST TCG operation. This
patch uses TCG memory-backed registers to represent the ARM register set. With
memory-backed registers the LD/ST operations are transparently generated by TCG...

12edd4f2 10/18/2009 12:52 am Filip Navara

target-arm: get rid of temporary variable cache

The temporary variable cache in no longer need since tcg_temp_free was introduced.

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

288eebe5 10/18/2009 12:52 am Filip Navara

target-arm: remove useless line that sets register that is never used again

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

217aff9c 10/18/2009 12:52 am Filip Navara

target-arm: remove unused gen_movl_T2_reg function

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

c67b6b71 10/18/2009 12:52 am Filip Navara

target-arm: fix SRS/RFE instructions

The encoding of 'IA' and 'DB' conditions was swapped.
SRS instruction must store banked SPSR instead of CPSR at the specific address.
Missing 'return' statement at the end of RFE handling.
Fixed write-back code to reference correct registers....

2fbac54b 10/18/2009 12:52 am Filip Navara

target-arm: get rid of gen_set_psr_T0 and replace it by gen_set_psr/gen_set_psr_im

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

c227f099 10/02/2009 12:12 am Anthony Liguori

Revert "Get rid of _t suffix"

In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem. Something
like this must be presented on the list first so people can provide input...

99a0949b 10/01/2009 09:45 pm malc

Get rid of _t suffix

Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <>

72cf2d4f 09/12/2009 10:36 am Blue Swirl

Fix sys-queue.h conflict for good

Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...

0b5c1ce8 08/24/2009 04:21 pm Nathan Froyd

cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal

handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations. This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets...

ffe47d33 07/31/2009 03:19 pm Paul Brook

Save/restore ARMv6 MMU state

Correctly save/restore ARMV6 MMU state.

Signed-off-by: Paul Brook <>

e2542fe2 07/27/2009 10:09 pm Juan Quintela

rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN

Signed-off-by: Juan Quintela <>
Signed-off-by: Anthony Liguori <>

8167ee88 07/16/2009 11:47 pm Blue Swirl

Update to a hopefully more future proof FSF address

Signed-off-by: Blue Swirl <>

024589f1 06/24/2009 05:09 pm Filip Navara

Remove unused gen_bx_T0 function.

Signed-off-by: Filip Navara <>
Signed-off-by: Anthony Liguori <>

f80f9ec9 05/21/2009 04:47 pm Anthony Liguori

Convert machine registration to use module init functions

This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.

Signed-off-by: Anthony Liguori <>

21aeb343 05/15/2009 05:18 am Juha Riihimäki

fix ARMv7 data processing instructions

ARMv7 defines a new behavior for ARM data processing instructions
compared to earlier architecture revisions; when the destination
register is R15, a Branch and Exchange operation is executed rather
than a simple Branch to the target address. This patch corrects the...

e9bb4aa9 05/15/2009 04:48 am Juha Riihimäki

fix ARMv7 data processing instructions

Modernize parts of target-arm/translate.c in preparation for the
modifications in the subsequent patch in this patch set. This is done
in order to avoid writing new code to target-arm/translate.c that
would use deprecated methods and/or variables....

4af39611 05/15/2009 01:11 am Paul Brook

Syborg (Symbian Virtual Platform) board

A virtual reference platform for SymbianOS development/debugging.

Signed-off-by: Paul Brook <>

cb76e138 05/10/2009 01:12 am Paul Brook

Fixe ARM NEON vrshl.

Signed-off-by: Paul Brook <>

0bf46a40 04/24/2009 09:03 pm aliguori

qemu: introduce qemu_init_vcpu (Marcelo Tosatti)

Signed-off-by: Marcelo Tosatti <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162

6a4955a8 04/24/2009 09:03 pm aliguori

qemu: per-arch cpu_has_work (Marcelo Tosatti)

Blue Swirl: fix Sparc32 breakage

Signed-off-by: Marcelo Tosatti <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162

37f9ba46 04/08/2009 01:48 am aurel32

target-arm: don't use T[x] in helper

(Torbjörn Andersson)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7034 c046a42c-6fe2-441c-8c8c-71466251a162

1b530a6d 04/05/2009 11:08 pm aurel32

Add new command line option -singlestep for tcg single stepping.

This replaces a compile time option for some targets and adds
this feature to targets which did not have a compile time option.

Add monitor command to enable or disable single step mode.

Modify monitor command "info status" to display single step mode....

cbbccffc 03/17/2009 02:19 pm pbrook

Fix ARM quadword VDUP (core register).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6857 c046a42c-6fe2-441c-8c8c-71466251a162

66896cb8 03/13/2009 11:34 am aurel32

tcg: rename bswap_i32/i64 functions

Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162

533d177a 03/08/2009 12:10 am aurel32

Fix correct reset value for ARM CP15 c1 auxiliary control register

According to ARM Cortex A8 Technical Reference Manual, the reset value for CP15 c1 auxiliary control
register is 2, not zero (page 3.12).

Signed-off-by: Riku Voipio <>
Acked-by: Laurent Desnogues <>...

2b3ea315 03/07/2009 11:48 pm aurel32

clean build: Fix arm build warnings

Fix remaining arm warnings - except for the mess in the NetWinder FP
emulator.

Signed-off-by: Jan Kiszka <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6766 c046a42c-6fe2-441c-8c8c-71466251a162

c2764719 03/07/2009 05:24 pm pbrook

The _exit syscall is used for both thread termination in NPTL applications,
and process termination in legacy applications. Try to guess which we want
based on the presence of multiple threads.

Also implement locking when modifying the CPU list.

Signed-off-by: Paul Brook <>...

84a031c6 02/07/2009 05:19 pm aurel32

Fix cpu_arm_handle_mmu_fault warning

This patch fixes:

/scratch/froydnj/qemu.git/target-arm/helper.c:451: warning: no previous prototype for 'cpu_arm_handle_mmu_fault'

by moving the declaration of the function to cpu.h from exec.h. cpu.h
seems to be the place most other ports declare the corresponding...

0d0266a5 02/06/2009 12:06 am aliguori

targets: remove error handling from qemu_malloc() callers (Avi Kivity)

Signed-off-by: Avi Kivity <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162

eca1bdf4 01/26/2009 09:54 pm aliguori

Log reset events (Jan Kiszka)

Original idea&code by Kevin Wolf, split-up in two patches and added more
archs.

This patch introduces a flag to log CPU resets. Useful for tracing
unexpected resets (such as those triggered by x86 triple faults).

Signed-off-by: Jan Kiszka <>...

8fec2b8c 01/16/2009 12:36 am aliguori

global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)

These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.

Signed-off-by: Eduardo Habkost <>
Signed-off-by: Anthony Liguori <>...

93fcfe39 01/16/2009 12:34 am aliguori

Convert references to logfile/loglevel to use qemu_log*() macros

This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <>
Signed-off-by: Anthony Liguori <>...

fad6cb1a 01/05/2009 12:05 am aurel32

Update FSF address in GPL/LGPL boilerplate

The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <>
Signed-off-by: Aurelien Jarno <>...

fe76d976 12/19/2008 04:33 pm pbrook

Implement flush-to-zero mode (denormal results are replaced with zero).

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6107 c046a42c-6fe2-441c-8c8c-71466251a162

5c7908ed 12/19/2008 03:53 pm pbrook

Implement default-NaN mode.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6106 c046a42c-6fe2-441c-8c8c-71466251a162

a49ea279 12/19/2008 03:37 pm pbrook

Implement ARMv7 cp15 cache ID registers.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6105 c046a42c-6fe2-441c-8c8c-71466251a162

fe1479c3 12/19/2008 03:18 pm pbrook

Implement (very) basic Thumb2-EE support. This doesn't actually implement
EE state, just the associated system coprocessor registers. It is sufficient
to keep OS setup and context switching code happy.

Signed-off-by: Paul Brook <>
...

644ad806 12/19/2008 03:02 pm pbrook

Fix VFP fixed point conversion routines.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6103 c046a42c-6fe2-441c-8c8c-71466251a162

d4934d18 12/19/2008 02:39 pm pbrook

Implement ARMv7 MMU access permissions.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6099 c046a42c-6fe2-441c-8c8c-71466251a162

997641a8 12/15/2008 04:05 am balrog

ARM: basic SX1-cellphone sysemu support (Jean-Christophe PLAGNIOL-VILLARD).

The TSC2102 chip is not included in documentation because a patch is
pending.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6038 c046a42c-6fe2-441c-8c8c-71466251a162

1d6198c3 12/13/2008 11:32 am blueswir1

Remove unnecessary trailing newlines

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162

db8d9902 12/07/2008 08:15 pm aurel32

Remove FORCE_RET() and RETURN

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162