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#if !defined (__MIPS_CPU_H__)
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#define __MIPS_CPU_H__
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#define TARGET_HAS_ICE 1
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#define ELF_MACHINE        EM_MIPS
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#define CPUState struct CPUMIPSState
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#include "config.h"
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#include "mips-defs.h"
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#include "cpu-defs.h"
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#include "softfloat.h"
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// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
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// XXX: move that elsewhere
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#if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10
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typedef unsigned char           uint_fast8_t;
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typedef unsigned int            uint_fast16_t;
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#endif
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struct CPUMIPSState;
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typedef struct r4k_tlb_t r4k_tlb_t;
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struct r4k_tlb_t {
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    target_ulong VPN;
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    uint32_t PageMask;
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    uint_fast8_t ASID;
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    uint_fast16_t G:1;
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    uint_fast16_t C0:3;
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    uint_fast16_t C1:3;
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    uint_fast16_t V0:1;
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    uint_fast16_t V1:1;
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    uint_fast16_t D0:1;
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    uint_fast16_t D1:1;
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    target_ulong PFN[2];
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};
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#if !defined(CONFIG_USER_ONLY)
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typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
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struct CPUMIPSTLBContext {
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    uint32_t nb_tlb;
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    uint32_t tlb_in_use;
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    int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type);
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    void (*helper_tlbwi) (void);
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    void (*helper_tlbwr) (void);
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    void (*helper_tlbp) (void);
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    void (*helper_tlbr) (void);
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    union {
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        struct {
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            r4k_tlb_t tlb[MIPS_TLB_MAX];
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        } r4k;
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    } mmu;
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};
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#endif
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typedef union fpr_t fpr_t;
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union fpr_t {
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    float64  fd;   /* ieee double precision */
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    float32  fs[2];/* ieee single precision */
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    uint64_t d;    /* binary double fixed-point */
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    uint32_t w[2]; /* binary single fixed-point */
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};
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/* define FP_ENDIAN_IDX to access the same location
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 * in the fpr_t union regardless of the host endianess
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 */
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#if defined(HOST_WORDS_BIGENDIAN)
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#  define FP_ENDIAN_IDX 1
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#else
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#  define FP_ENDIAN_IDX 0
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#endif
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typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
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struct CPUMIPSFPUContext {
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    /* Floating point registers */
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    fpr_t fpr[32];
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    float_status fp_status;
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    /* fpu implementation/revision register (fir) */
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    uint32_t fcr0;
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#define FCR0_F64 22
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#define FCR0_L 21
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#define FCR0_W 20
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#define FCR0_3D 19
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#define FCR0_PS 18
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#define FCR0_D 17
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#define FCR0_S 16
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#define FCR0_PRID 8
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#define FCR0_REV 0
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    /* fcsr */
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    uint32_t fcr31;
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#define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
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#define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
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#define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
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#define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
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#define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
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#define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
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#define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
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#define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
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#define FP_INEXACT        1
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#define FP_UNDERFLOW      2
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#define FP_OVERFLOW       4
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#define FP_DIV0           8
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#define FP_INVALID        16
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#define FP_UNIMPLEMENTED  32
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};
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#define NB_MMU_MODES 3
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typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
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struct CPUMIPSMVPContext {
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    int32_t CP0_MVPControl;
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#define CP0MVPCo_CPA        3
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#define CP0MVPCo_STLB        2
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#define CP0MVPCo_VPC        1
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#define CP0MVPCo_EVP        0
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    int32_t CP0_MVPConf0;
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#define CP0MVPC0_M        31
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#define CP0MVPC0_TLBS        29
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#define CP0MVPC0_GS        28
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#define CP0MVPC0_PCP        27
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#define CP0MVPC0_PTLBE        16
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#define CP0MVPC0_TCA        15
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#define CP0MVPC0_PVPE        10
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#define CP0MVPC0_PTC        0
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    int32_t CP0_MVPConf1;
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#define CP0MVPC1_CIM        31
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#define CP0MVPC1_CIF        30
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#define CP0MVPC1_PCX        20
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#define CP0MVPC1_PCP2        10
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#define CP0MVPC1_PCP1        0
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};
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typedef struct mips_def_t mips_def_t;
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#define MIPS_SHADOW_SET_MAX 16
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#define MIPS_TC_MAX 5
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#define MIPS_FPU_MAX 1
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#define MIPS_DSP_ACC 4
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typedef struct TCState TCState;
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struct TCState {
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    target_ulong gpr[32];
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    target_ulong PC;
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    target_ulong HI[MIPS_DSP_ACC];
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    target_ulong LO[MIPS_DSP_ACC];
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    target_ulong ACX[MIPS_DSP_ACC];
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    target_ulong DSPControl;
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    int32_t CP0_TCStatus;
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#define CP0TCSt_TCU3        31
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#define CP0TCSt_TCU2        30
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#define CP0TCSt_TCU1        29
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#define CP0TCSt_TCU0        28
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#define CP0TCSt_TMX        27
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#define CP0TCSt_RNST        23
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#define CP0TCSt_TDS        21
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#define CP0TCSt_DT        20
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#define CP0TCSt_DA        15
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#define CP0TCSt_A        13
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#define CP0TCSt_TKSU        11
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#define CP0TCSt_IXMT        10
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#define CP0TCSt_TASID        0
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    int32_t CP0_TCBind;
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#define CP0TCBd_CurTC        21
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#define CP0TCBd_TBE        17
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#define CP0TCBd_CurVPE        0
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    target_ulong CP0_TCHalt;
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    target_ulong CP0_TCContext;
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    target_ulong CP0_TCSchedule;
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    target_ulong CP0_TCScheFBack;
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    int32_t CP0_Debug_tcstatus;
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};
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typedef struct CPUMIPSState CPUMIPSState;
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struct CPUMIPSState {
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    TCState active_tc;
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    CPUMIPSFPUContext active_fpu;
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    uint32_t current_tc;
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    uint32_t current_fpu;
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    uint32_t SEGBITS;
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    uint32_t PABITS;
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    target_ulong SEGMask;
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    target_ulong PAMask;
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    int32_t CP0_Index;
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    /* CP0_MVP* are per MVP registers. */
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    int32_t CP0_Random;
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    int32_t CP0_VPEControl;
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#define CP0VPECo_YSI        21
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#define CP0VPECo_GSI        20
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#define CP0VPECo_EXCPT        16
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#define CP0VPECo_TE        15
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#define CP0VPECo_TargTC        0
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    int32_t CP0_VPEConf0;
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#define CP0VPEC0_M        31
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#define CP0VPEC0_XTC        21
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#define CP0VPEC0_TCS        19
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#define CP0VPEC0_SCS        18
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#define CP0VPEC0_DSC        17
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#define CP0VPEC0_ICS        16
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#define CP0VPEC0_MVP        1
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#define CP0VPEC0_VPA        0
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    int32_t CP0_VPEConf1;
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#define CP0VPEC1_NCX        20
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#define CP0VPEC1_NCP2        10
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#define CP0VPEC1_NCP1        0
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    target_ulong CP0_YQMask;
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    target_ulong CP0_VPESchedule;
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    target_ulong CP0_VPEScheFBack;
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    int32_t CP0_VPEOpt;
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#define CP0VPEOpt_IWX7        15
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#define CP0VPEOpt_IWX6        14
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#define CP0VPEOpt_IWX5        13
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#define CP0VPEOpt_IWX4        12
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#define CP0VPEOpt_IWX3        11
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#define CP0VPEOpt_IWX2        10
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#define CP0VPEOpt_IWX1        9
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#define CP0VPEOpt_IWX0        8
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#define CP0VPEOpt_DWX7        7
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#define CP0VPEOpt_DWX6        6
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#define CP0VPEOpt_DWX5        5
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#define CP0VPEOpt_DWX4        4
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#define CP0VPEOpt_DWX3        3
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#define CP0VPEOpt_DWX2        2
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#define CP0VPEOpt_DWX1        1
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#define CP0VPEOpt_DWX0        0
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    target_ulong CP0_EntryLo0;
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    target_ulong CP0_EntryLo1;
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    target_ulong CP0_Context;
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    int32_t CP0_PageMask;
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    int32_t CP0_PageGrain;
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    int32_t CP0_Wired;
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    int32_t CP0_SRSConf0_rw_bitmask;
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    int32_t CP0_SRSConf0;
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#define CP0SRSC0_M        31
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#define CP0SRSC0_SRS3        20
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#define CP0SRSC0_SRS2        10
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#define CP0SRSC0_SRS1        0
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    int32_t CP0_SRSConf1_rw_bitmask;
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    int32_t CP0_SRSConf1;
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#define CP0SRSC1_M        31
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#define CP0SRSC1_SRS6        20
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#define CP0SRSC1_SRS5        10
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#define CP0SRSC1_SRS4        0
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    int32_t CP0_SRSConf2_rw_bitmask;
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    int32_t CP0_SRSConf2;
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#define CP0SRSC2_M        31
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#define CP0SRSC2_SRS9        20
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#define CP0SRSC2_SRS8        10
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#define CP0SRSC2_SRS7        0
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    int32_t CP0_SRSConf3_rw_bitmask;
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    int32_t CP0_SRSConf3;
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#define CP0SRSC3_M        31
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#define CP0SRSC3_SRS12        20
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#define CP0SRSC3_SRS11        10
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#define CP0SRSC3_SRS10        0
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    int32_t CP0_SRSConf4_rw_bitmask;
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    int32_t CP0_SRSConf4;
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#define CP0SRSC4_SRS15        20
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#define CP0SRSC4_SRS14        10
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#define CP0SRSC4_SRS13        0
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    int32_t CP0_HWREna;
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    target_ulong CP0_BadVAddr;
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    int32_t CP0_Count;
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    target_ulong CP0_EntryHi;
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    int32_t CP0_Compare;
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    int32_t CP0_Status;
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#define CP0St_CU3   31
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#define CP0St_CU2   30
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#define CP0St_CU1   29
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#define CP0St_CU0   28
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#define CP0St_RP    27
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#define CP0St_FR    26
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#define CP0St_RE    25
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#define CP0St_MX    24
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#define CP0St_PX    23
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#define CP0St_BEV   22
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#define CP0St_TS    21
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#define CP0St_SR    20
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#define CP0St_NMI   19
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#define CP0St_IM    8
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#define CP0St_KX    7
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#define CP0St_SX    6
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#define CP0St_UX    5
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#define CP0St_KSU   3
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#define CP0St_ERL   2
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#define CP0St_EXL   1
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#define CP0St_IE    0
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    int32_t CP0_IntCtl;
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#define CP0IntCtl_IPTI 29
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#define CP0IntCtl_IPPC1 26
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#define CP0IntCtl_VS 5
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    int32_t CP0_SRSCtl;
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#define CP0SRSCtl_HSS 26
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#define CP0SRSCtl_EICSS 18
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#define CP0SRSCtl_ESS 12
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#define CP0SRSCtl_PSS 6
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#define CP0SRSCtl_CSS 0
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    int32_t CP0_SRSMap;
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#define CP0SRSMap_SSV7 28
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#define CP0SRSMap_SSV6 24
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#define CP0SRSMap_SSV5 20
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#define CP0SRSMap_SSV4 16
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#define CP0SRSMap_SSV3 12
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#define CP0SRSMap_SSV2 8
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#define CP0SRSMap_SSV1 4
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#define CP0SRSMap_SSV0 0
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    int32_t CP0_Cause;
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#define CP0Ca_BD   31
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#define CP0Ca_TI   30
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#define CP0Ca_CE   28
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#define CP0Ca_DC   27
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#define CP0Ca_PCI  26
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#define CP0Ca_IV   23
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#define CP0Ca_WP   22
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#define CP0Ca_IP    8
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#define CP0Ca_IP_mask 0x0000FF00
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#define CP0Ca_EC    2
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    target_ulong CP0_EPC;
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    int32_t CP0_PRid;
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    int32_t CP0_EBase;
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    int32_t CP0_Config0;
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#define CP0C0_M    31
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#define CP0C0_K23  28
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#define CP0C0_KU   25
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#define CP0C0_MDU  20
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#define CP0C0_MM   17
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#define CP0C0_BM   16
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#define CP0C0_BE   15
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#define CP0C0_AT   13
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#define CP0C0_AR   10
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#define CP0C0_MT   7
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#define CP0C0_VI   3
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#define CP0C0_K0   0
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    int32_t CP0_Config1;
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#define CP0C1_M    31
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#define CP0C1_MMU  25
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#define CP0C1_IS   22
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#define CP0C1_IL   19
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#define CP0C1_IA   16
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#define CP0C1_DS   13
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#define CP0C1_DL   10
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#define CP0C1_DA   7
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#define CP0C1_C2   6
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#define CP0C1_MD   5
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#define CP0C1_PC   4
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#define CP0C1_WR   3
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#define CP0C1_CA   2
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#define CP0C1_EP   1
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#define CP0C1_FP   0
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    int32_t CP0_Config2;
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#define CP0C2_M    31
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#define CP0C2_TU   28
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#define CP0C2_TS   24
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#define CP0C2_TL   20
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#define CP0C2_TA   16
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#define CP0C2_SU   12
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#define CP0C2_SS   8
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#define CP0C2_SL   4
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#define CP0C2_SA   0
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    int32_t CP0_Config3;
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#define CP0C3_M    31
366
#define CP0C3_ISA_ON_EXC 16
367
#define CP0C3_DSPP 10
368
#define CP0C3_LPA  7
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#define CP0C3_VEIC 6
370
#define CP0C3_VInt 5
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#define CP0C3_SP   4
372
#define CP0C3_MT   2
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#define CP0C3_SM   1
374
#define CP0C3_TL   0
375
    int32_t CP0_Config6;
376
    int32_t CP0_Config7;
377
    /* XXX: Maybe make LLAddr per-TC? */
378
    target_ulong lladdr;
379
    target_ulong llval;
380
    target_ulong llnewval;
381
    target_ulong llreg;
382
    target_ulong CP0_LLAddr_rw_bitmask;
383
    int CP0_LLAddr_shift;
384
    target_ulong CP0_WatchLo[8];
385
    int32_t CP0_WatchHi[8];
386
    target_ulong CP0_XContext;
387
    int32_t CP0_Framemask;
388
    int32_t CP0_Debug;
389
#define CP0DB_DBD  31
390
#define CP0DB_DM   30
391
#define CP0DB_LSNM 28
392
#define CP0DB_Doze 27
393
#define CP0DB_Halt 26
394
#define CP0DB_CNT  25
395
#define CP0DB_IBEP 24
396
#define CP0DB_DBEP 21
397
#define CP0DB_IEXI 20
398
#define CP0DB_VER  15
399
#define CP0DB_DEC  10
400
#define CP0DB_SSt  8
401
#define CP0DB_DINT 5
402
#define CP0DB_DIB  4
403
#define CP0DB_DDBS 3
404
#define CP0DB_DDBL 2
405
#define CP0DB_DBp  1
406
#define CP0DB_DSS  0
407
    target_ulong CP0_DEPC;
408
    int32_t CP0_Performance0;
409
    int32_t CP0_TagLo;
410
    int32_t CP0_DataLo;
411
    int32_t CP0_TagHi;
412
    int32_t CP0_DataHi;
413
    target_ulong CP0_ErrorEPC;
414
    int32_t CP0_DESAVE;
415
    /* We waste some space so we can handle shadow registers like TCs. */
416
    TCState tcs[MIPS_SHADOW_SET_MAX];
417
    CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
418
    /* Qemu */
419
    int error_code;
420
    uint32_t hflags;    /* CPU State */
421
    /* TMASK defines different execution modes */
422
#define MIPS_HFLAG_TMASK  0x007FF
423
#define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
424
    /* The KSU flags must be the lowest bits in hflags. The flag order
425
       must be the same as defined for CP0 Status. This allows to use
426
       the bits as the value of mmu_idx. */
427
#define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
428
#define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
429
#define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
430
#define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
431
#define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
432
#define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
433
#define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
434
#define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
435
#define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
436
    /* True if the MIPS IV COP1X instructions can be used.  This also
437
       controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
438
       and RSQRT.D.  */
439
#define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
440
#define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
441
#define MIPS_HFLAG_UX     0x00200 /* 64-bit user mode                   */
442
#define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
443
#define MIPS_HFLAG_M16_SHIFT 10
444
    /* If translation is interrupted between the branch instruction and
445
     * the delay slot, record what type of branch it is so that we can
446
     * resume translation properly.  It might be possible to reduce
447
     * this from three bits to two.  */
448
#define MIPS_HFLAG_BMASK_BASE  0x03800
449
#define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
450
#define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
451
#define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
452
#define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
453
    /* Extra flags about the current pending branch.  */
454
#define MIPS_HFLAG_BMASK_EXT 0x3C000
455
#define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
456
#define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
457
#define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
458
#define MIPS_HFLAG_BX     0x20000 /* branch exchanges execution mode    */
459
#define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
460
    target_ulong btarget;        /* Jump / branch target               */
461
    target_ulong bcond;          /* Branch condition (if needed)       */
462

    
463
    int SYNCI_Step; /* Address step size for SYNCI */
464
    int CCRes; /* Cycle count resolution/divisor */
465
    uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
466
    uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
467
    int insn_flags; /* Supported instruction set */
468

    
469
    target_ulong tls_value; /* For usermode emulation */
470

    
471
    CPU_COMMON
472

    
473
    CPUMIPSMVPContext *mvp;
474
#if !defined(CONFIG_USER_ONLY)
475
    CPUMIPSTLBContext *tlb;
476
#endif
477

    
478
    const mips_def_t *cpu_model;
479
    void *irq[8];
480
    struct QEMUTimer *timer; /* Internal timer */
481
};
482

    
483
#if !defined(CONFIG_USER_ONLY)
484
int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
485
                        target_ulong address, int rw, int access_type);
486
int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
487
                           target_ulong address, int rw, int access_type);
488
int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
489
                     target_ulong address, int rw, int access_type);
490
void r4k_helper_tlbwi (void);
491
void r4k_helper_tlbwr (void);
492
void r4k_helper_tlbp (void);
493
void r4k_helper_tlbr (void);
494

    
495
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
496
                          int unused, int size);
497
#endif
498

    
499
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
500

    
501
#define cpu_init cpu_mips_init
502
#define cpu_exec cpu_mips_exec
503
#define cpu_gen_code cpu_mips_gen_code
504
#define cpu_signal_handler cpu_mips_signal_handler
505
#define cpu_list mips_cpu_list
506

    
507
#define CPU_SAVE_VERSION 3
508

    
509
/* MMU modes definitions. We carefully match the indices with our
510
   hflags layout. */
511
#define MMU_MODE0_SUFFIX _kernel
512
#define MMU_MODE1_SUFFIX _super
513
#define MMU_MODE2_SUFFIX _user
514
#define MMU_USER_IDX 2
515
static inline int cpu_mmu_index (CPUState *env)
516
{
517
    return env->hflags & MIPS_HFLAG_KSU;
518
}
519

    
520
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
521
{
522
    if (newsp)
523
        env->active_tc.gpr[29] = newsp;
524
    env->active_tc.gpr[7] = 0;
525
    env->active_tc.gpr[2] = 0;
526
}
527

    
528
#include "cpu-all.h"
529

    
530
/* Memory access type :
531
 * may be needed for precise access rights control and precise exceptions.
532
 */
533
enum {
534
    /* 1 bit to define user level / supervisor access */
535
    ACCESS_USER  = 0x00,
536
    ACCESS_SUPER = 0x01,
537
    /* 1 bit to indicate direction */
538
    ACCESS_STORE = 0x02,
539
    /* Type of instruction that generated the access */
540
    ACCESS_CODE  = 0x10, /* Code fetch access                */
541
    ACCESS_INT   = 0x20, /* Integer load/store access        */
542
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
543
};
544

    
545
/* Exceptions */
546
enum {
547
    EXCP_NONE          = -1,
548
    EXCP_RESET         = 0,
549
    EXCP_SRESET,
550
    EXCP_DSS,
551
    EXCP_DINT,
552
    EXCP_DDBL,
553
    EXCP_DDBS,
554
    EXCP_NMI,
555
    EXCP_MCHECK,
556
    EXCP_EXT_INTERRUPT, /* 8 */
557
    EXCP_DFWATCH,
558
    EXCP_DIB,
559
    EXCP_IWATCH,
560
    EXCP_AdEL,
561
    EXCP_AdES,
562
    EXCP_TLBF,
563
    EXCP_IBE,
564
    EXCP_DBp, /* 16 */
565
    EXCP_SYSCALL,
566
    EXCP_BREAK,
567
    EXCP_CpU,
568
    EXCP_RI,
569
    EXCP_OVERFLOW,
570
    EXCP_TRAP,
571
    EXCP_FPE,
572
    EXCP_DWATCH, /* 24 */
573
    EXCP_LTLBL,
574
    EXCP_TLBL,
575
    EXCP_TLBS,
576
    EXCP_DBE,
577
    EXCP_THREAD,
578
    EXCP_MDMX,
579
    EXCP_C2E,
580
    EXCP_CACHE, /* 32 */
581

    
582
    EXCP_LAST = EXCP_CACHE,
583
};
584
/* Dummy exception for conditional stores.  */
585
#define EXCP_SC 0x100
586

    
587
int cpu_mips_exec(CPUMIPSState *s);
588
CPUMIPSState *cpu_mips_init(const char *cpu_model);
589
//~ uint32_t cpu_mips_get_clock (void);
590
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
591

    
592
/* mips_timer.c */
593
uint32_t cpu_mips_get_random (CPUState *env);
594
uint32_t cpu_mips_get_count (CPUState *env);
595
void cpu_mips_store_count (CPUState *env, uint32_t value);
596
void cpu_mips_store_compare (CPUState *env, uint32_t value);
597
void cpu_mips_start_count(CPUState *env);
598
void cpu_mips_stop_count(CPUState *env);
599

    
600
/* mips_int.c */
601
void cpu_mips_update_irq (CPUState *env);
602

    
603
/* helper.c */
604
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
605
                               int mmu_idx, int is_softmmu);
606
#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
607
void do_interrupt (CPUState *env);
608
#if !defined(CONFIG_USER_ONLY)
609
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
610
target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,
611
                                               int rw);
612
#endif
613

    
614
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
615
                                        target_ulong *cs_base, int *flags)
616
{
617
    *pc = env->active_tc.PC;
618
    *cs_base = 0;
619
    *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
620
}
621

    
622
static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
623
{
624
    env->tls_value = newtls;
625
}
626

    
627
#endif /* !defined (__MIPS_CPU_H__) */