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/*
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 * GUSEMU32 - bus interface part
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 *
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 * Copyright (C) 2000-2007 Tibor "TS" Schütz
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * TODO: check mixer: see 7.20 of sdk for panning pos (applies to all gus models?)?
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 */
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29 47b43a1f Paolo Bonzini
#include "gustate.h"
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#include "gusemu.h"
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#define GUSregb(position) (*            (gusptr+(position)))
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#define GUSregw(position) (*(GUSword *) (gusptr+(position)))
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#define GUSregd(position) (*(GUSdword *)(gusptr+(position)))
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/* size given in bytes */
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unsigned int gus_read(GUSEmuState * state, int port, int size)
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{
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    int             value_read = 0;
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    GUSbyte        *gusptr;
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    gusptr = state->gusdatapos;
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    GUSregd(portaccesses)++;
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    switch (port & 0xff0f)
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    {
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        /* MixerCtrlReg (read not supported on GUS classic) */
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        /* case 0x200: return GUSregb(MixerCtrlReg2x0); */
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    case 0x206:                          /* IRQstatReg / SB2x6IRQ */
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        /* adlib/sb bits set in port handlers */
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        /* timer/voice bits set in gus_irqgen() */
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        /* dma bit set in gus_dma_transferdata */
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        /* midi not implemented yet */
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        return GUSregb(IRQStatReg2x6);
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    /* case 0x308:                       */ /* AdLib388 */
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    case 0x208:
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        if (GUSregb(GUS45TimerCtrl) & 1)
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            return GUSregb(TimerStatus2x8);
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        return GUSregb(AdLibStatus2x8);  /* AdLibStatus */
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    case 0x309:                          /* AdLib389 */
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    case 0x209:
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        return GUSregb(AdLibData2x9);    /* AdLibData */
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    case 0x20A:
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        return GUSregb(AdLibCommand2xA); /* AdLib2x8_2xA */
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#if 0
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    case 0x20B:                          /* GUS hidden registers (read not supported on GUS classic) */
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        switch (GUSregb(RegCtrl_2xF) & 0x07)
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        {
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        case 0:                                 /* IRQ/DMA select */
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            if (GUSregb(MixerCtrlReg2x0) & 0x40)
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                return GUSregb(IRQ_2xB);        /* control register select bit */
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            else
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                return GUSregb(DMA_2xB);
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            /* case 1-5:                        */ /* general purpose emulation regs  */
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            /*  return ...                      */ /* + status reset reg (write only) */
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        case 6:
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            return GUSregb(Jumper_2xB);         /* Joystick/MIDI enable (JumperReg) */
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        default:;
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        }
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        break;
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#endif
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    case 0x20C:                          /* SB2xCd */
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        value_read = GUSregb(SB2xCd);
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        if (GUSregb(StatRead_2xF) & 0x20)
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            GUSregb(SB2xCd) ^= 0x80; /* toggle MSB on read */
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        return value_read;
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        /* case 0x20D:                   */ /* SB2xD is write only -> 2xE writes to it*/
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    case 0x20E:
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        if (GUSregb(RegCtrl_2xF) & 0x80) /* 2xE read IRQ enabled? */
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        {
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            GUSregb(StatRead_2xF) |= 0x80;
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            GUS_irqrequest(state, state->gusirq, 1);
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        }
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        return GUSregb(SB2xE);           /* SB2xE */
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    case 0x20F:                          /* StatRead_2xF */
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        /*set/clear fixed bits */
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        /*value_read = (GUSregb(StatRead_2xF) & 0xf9)|1; */ /*(LSB not set on GUS classic!)*/
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        value_read = (GUSregb(StatRead_2xF) & 0xf9);
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        if (GUSregb(MixerCtrlReg2x0) & 0x08)
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            value_read |= 2;    /* DMA/IRQ enabled flag */
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        return value_read;
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    /* case 0x300:                      */ /* MIDI (not implemented) */
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    /* case 0x301:                      */ /* MIDI (not implemented) */
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    case 0x302:
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        return GUSregb(VoiceSelReg3x2); /* VoiceSelReg */
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    case 0x303:
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        return GUSregb(FunkSelReg3x3);  /* FunkSelReg */
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    case 0x304:                         /* DataRegLoByte3x4 + DataRegWord3x4 */
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    case 0x305:                         /* DataRegHiByte3x5 */
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        switch (GUSregb(FunkSelReg3x3))
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        {
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    /* common functions */
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        case 0x41:                      /* DramDMAContrReg */
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            value_read = GUSregb(GUS41DMACtrl); /* &0xfb */
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            GUSregb(GUS41DMACtrl) &= 0xbb;
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            if (state->gusdma >= 4)
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                value_read |= 0x04;
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            if (GUSregb(IRQStatReg2x6) & 0x80)
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            {
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                value_read |= 0x40;
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                GUSregb(IRQStatReg2x6) &= 0x7f;
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                if (!GUSregb(IRQStatReg2x6))
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                    GUS_irqclear(state, state->gusirq);
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            }
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            return (GUSbyte) value_read;
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            /* DramDMAmemPosReg */
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            /* case 0x42: value_read=GUSregw(GUS42DMAStart); break;*/
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            /* 43h+44h write only */
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        case 0x45:
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            return GUSregb(GUS45TimerCtrl);         /* TimerCtrlReg */
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            /* 46h+47h write only */
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            /* 48h: samp freq - write only */
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        case 0x49:
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            return GUSregb(GUS49SampCtrl) & 0xbf;   /* SampCtrlReg */
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        /* case 4bh:                                */ /* joystick trim not supported */
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        /* case 0x4c: return GUSregb(GUS4cReset);   */ /* GUSreset: write only*/
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    /* voice specific functions */
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        case 0x80:
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        case 0x81:
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        case 0x82:
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        case 0x83:
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        case 0x84:
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        case 0x85:
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        case 0x86:
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        case 0x87:
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        case 0x88:
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        case 0x89:
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        case 0x8a:
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        case 0x8b:
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        case 0x8c:
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        case 0x8d:
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            {
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                int             offset = 2 * (GUSregb(FunkSelReg3x3) & 0x0f);
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                offset += ((int) GUSregb(VoiceSelReg3x2) & 0x1f) << 5; /* = Voice*32 + Funktion*2 */
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                value_read = GUSregw(offset);
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            }
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            break;
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    /* voice unspecific functions */
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        case 0x8e:                                  /* NumVoice */
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            return GUSregb(NumVoices);
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        case 0x8f:                                  /* irqstatreg */
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            /* (pseudo IRQ-FIFO is processed during a gus_write(0x3X3,0x8f)) */
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            return GUSregb(SynVoiceIRQ8f);
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        default:
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            return 0xffff;
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        }
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        if (size == 1)
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        {
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            if ((port & 0xff0f) == 0x305)
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                value_read = value_read >> 8;
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            value_read &= 0xff;
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        }
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        return (GUSword) value_read;
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    /* case 0x306:                                  */ /* Mixer/Version info */
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        /*  return 0xff; */ /* Pre 3.6 boards, ICS mixer NOT present */
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    case 0x307:                                     /* DRAMaccess */
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        {
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            GUSbyte        *adr;
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            adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);
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            return *adr;
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        }
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    default:;
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    }
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    return 0xffff;
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}
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void gus_write(GUSEmuState * state, int port, int size, unsigned int data)
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{
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    GUSbyte        *gusptr;
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    gusptr = state->gusdatapos;
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    GUSregd(portaccesses)++;
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    switch (port & 0xff0f)
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    {
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    case 0x200:                 /* MixerCtrlReg */
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        GUSregb(MixerCtrlReg2x0) = (GUSbyte) data;
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        break;
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    case 0x206:                 /* IRQstatReg / SB2x6IRQ */
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        if (GUSregb(GUS45TimerCtrl) & 0x20) /* SB IRQ enabled? -> set 2x6IRQ bit */
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        {
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            GUSregb(TimerStatus2x8) |= 0x08;
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            GUSregb(IRQStatReg2x6) = 0x10;
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            GUS_irqrequest(state, state->gusirq, 1);
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        }
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        break;
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    case 0x308:                /* AdLib 388h */
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    case 0x208:                /* AdLibCommandReg */
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        GUSregb(AdLibCommand2xA) = (GUSbyte) data;
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        break;
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    case 0x309:                /* AdLib 389h */
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    case 0x209:                /* AdLibDataReg */
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        if ((GUSregb(AdLibCommand2xA) == 0x04) && (!(GUSregb(GUS45TimerCtrl) & 1))) /* GUS auto timer mode enabled? */
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        {
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            if (data & 0x80)
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                GUSregb(TimerStatus2x8) &= 0x1f; /* AdLib IRQ reset? -> clear maskable adl. timer int regs */
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            else
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                GUSregb(TimerDataReg2x9) = (GUSbyte) data;
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        }
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        else
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        {
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            GUSregb(AdLibData2x9) = (GUSbyte) data;
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            if (GUSregb(GUS45TimerCtrl) & 0x02)
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            {
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                GUSregb(TimerStatus2x8) |= 0x01;
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                GUSregb(IRQStatReg2x6) = 0x10;
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                GUS_irqrequest(state, state->gusirq, 1);
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            }
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        }
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        break;
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    case 0x20A:
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        GUSregb(AdLibStatus2x8) = (GUSbyte) data;
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        break;                 /* AdLibStatus2x8 */
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    case 0x20B:                /* GUS hidden registers */
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        switch (GUSregb(RegCtrl_2xF) & 0x7)
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        {
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        case 0:
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            if (GUSregb(MixerCtrlReg2x0) & 0x40)
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                GUSregb(IRQ_2xB) = (GUSbyte) data; /* control register select bit */
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            else
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                GUSregb(DMA_2xB) = (GUSbyte) data;
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            break;
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            /* case 1-4: general purpose emulation regs */
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        case 5:                                    /* clear stat reg 2xF */
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            GUSregb(StatRead_2xF) = 0; /* ToDo: is this identical with GUS classic? */
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            if (!GUSregb(IRQStatReg2x6))
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                GUS_irqclear(state, state->gusirq);
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            break;
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        case 6:                                    /* Jumper reg (Joystick/MIDI enable) */
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            GUSregb(Jumper_2xB) = (GUSbyte) data;
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            break;
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        default:;
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        }
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        break;
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    case 0x20C:                /* SB2xCd */
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        if (GUSregb(GUS45TimerCtrl) & 0x20)
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        {
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            GUSregb(TimerStatus2x8) |= 0x10; /* SB IRQ enabled? -> set 2xCIRQ bit */
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            GUSregb(IRQStatReg2x6) = 0x10;
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            GUS_irqrequest(state, state->gusirq, 1);
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        }
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    case 0x20D:                /* SB2xCd no IRQ */
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        GUSregb(SB2xCd) = (GUSbyte) data;
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        break;
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    case 0x20E:                /* SB2xE */
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        GUSregb(SB2xE) = (GUSbyte) data;
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        break;
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    case 0x20F:
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        GUSregb(RegCtrl_2xF) = (GUSbyte) data;
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        break;                 /* CtrlReg2xF */
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    case 0x302:                /* VoiceSelReg */
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        GUSregb(VoiceSelReg3x2) = (GUSbyte) data;
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        break;
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    case 0x303:                /* FunkSelReg */
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        GUSregb(FunkSelReg3x3) = (GUSbyte) data;
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        if ((GUSbyte) data == 0x8f) /* set irqstatreg, get voicereg and clear IRQ */
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        {
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            int             voice;
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            if (GUSregd(voicewavetableirq)) /* WavetableIRQ */
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            {
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                for (voice = 0; voice < 31; voice++)
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                {
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                    if (GUSregd(voicewavetableirq) & (1 << voice))
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                    {
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                        GUSregd(voicewavetableirq) ^= (1 << voice); /* clear IRQ bit */
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                        GUSregb(voice << 5) &= 0x7f; /* clear voice reg irq bit */
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                        if (!GUSregd(voicewavetableirq))
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                            GUSregb(IRQStatReg2x6) &= 0xdf;
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                        if (!GUSregb(IRQStatReg2x6))
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                            GUS_irqclear(state, state->gusirq);
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                        GUSregb(SynVoiceIRQ8f) = voice | 0x60; /* (bit==0 => IRQ wartend) */
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                        return;
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                    }
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                }
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            }
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            else if (GUSregd(voicevolrampirq)) /* VolRamp IRQ */
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            {
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                for (voice = 0; voice < 31; voice++)
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                {
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                    if (GUSregd(voicevolrampirq) & (1 << voice))
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                    {
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                        GUSregd(voicevolrampirq) ^= (1 << voice); /* clear IRQ bit */
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                        GUSregb((voice << 5) + VSRVolRampControl) &= 0x7f; /* clear voice volume reg irq bit */
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                        if (!GUSregd(voicevolrampirq))
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                            GUSregb(IRQStatReg2x6) &= 0xbf;
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                        if (!GUSregb(IRQStatReg2x6))
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                            GUS_irqclear(state, state->gusirq);
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                        GUSregb(SynVoiceIRQ8f) = voice | 0x80; /* (bit==0 => IRQ wartend) */
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                        return;
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                    }
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                }
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            }
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            GUSregb(SynVoiceIRQ8f) = 0xe8; /* kein IRQ wartet */
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        }
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        break;
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    case 0x304:
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    case 0x305:
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        {
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            GUSword         writedata = (GUSword) data;
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            GUSword         readmask = 0x0000;
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            if (size == 1)
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            {
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                readmask = 0xff00;
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                writedata &= 0xff;
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                if ((port & 0xff0f) == 0x305)
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                {
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                    writedata = (GUSword) (writedata << 8);
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                    readmask = 0x00ff;
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                }
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            }
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            switch (GUSregb(FunkSelReg3x3))
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            {
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                /* voice specific functions */
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            case 0x00:
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            case 0x01:
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            case 0x02:
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            case 0x03:
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            case 0x04:
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            case 0x05:
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            case 0x06:
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            case 0x07:
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            case 0x08:
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            case 0x09:
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            case 0x0a:
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            case 0x0b:
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            case 0x0c:
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            case 0x0d:
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                {
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                    int             offset;
351 423d65f4 balrog
                    if (!(GUSregb(GUS4cReset) & 0x01))
352 423d65f4 balrog
                        break;  /* reset flag active? */
353 423d65f4 balrog
                    offset = 2 * (GUSregb(FunkSelReg3x3) & 0x0f);
354 423d65f4 balrog
                    offset += (GUSregb(VoiceSelReg3x2) & 0x1f) << 5; /*  = Voice*32 + Funktion*2 */
355 423d65f4 balrog
                    GUSregw(offset) = (GUSword) ((GUSregw(offset) & readmask) | writedata);
356 423d65f4 balrog
                }
357 423d65f4 balrog
                break;
358 423d65f4 balrog
                /* voice unspecific functions */
359 423d65f4 balrog
            case 0x0e:         /* NumVoices */
360 423d65f4 balrog
                GUSregb(NumVoices) = (GUSbyte) data;
361 423d65f4 balrog
                break;
362 423d65f4 balrog
            /* case 0x0f:      */ /* read only */
363 423d65f4 balrog
                /* common functions */
364 423d65f4 balrog
            case 0x41:         /* DramDMAContrReg */
365 423d65f4 balrog
                GUSregb(GUS41DMACtrl) = (GUSbyte) data;
366 423d65f4 balrog
                if (data & 0x01)
367 423d65f4 balrog
                    GUS_dmarequest(state);
368 423d65f4 balrog
                break;
369 423d65f4 balrog
            case 0x42:         /* DramDMAmemPosReg */
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                GUSregw(GUS42DMAStart) = (GUSregw(GUS42DMAStart) & readmask) | writedata;
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                GUSregb(GUS50DMAHigh) &= 0xf; /* compatibility stuff... */
372 423d65f4 balrog
                break;
373 423d65f4 balrog
            case 0x43:         /* DRAMaddrLo */
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                GUSregd(GUSDRAMPOS24bit) =
375 423d65f4 balrog
                    (GUSregd(GUSDRAMPOS24bit) & (readmask | 0xff0000)) | writedata;
376 423d65f4 balrog
                break;
377 423d65f4 balrog
            case 0x44:         /* DRAMaddrHi */
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                GUSregd(GUSDRAMPOS24bit) =
379 423d65f4 balrog
                    (GUSregd(GUSDRAMPOS24bit) & 0xffff) | ((data & 0x0f) << 16);
380 423d65f4 balrog
                break;
381 423d65f4 balrog
            case 0x45:         /* TCtrlReg */
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                GUSregb(GUS45TimerCtrl) = (GUSbyte) data;
383 423d65f4 balrog
                if (!(data & 0x20))
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                    GUSregb(TimerStatus2x8) &= 0xe7;    /* sb IRQ dis? -> clear 2x8/2xC sb IRQ flags */
385 423d65f4 balrog
                if (!(data & 0x02))
386 423d65f4 balrog
                    GUSregb(TimerStatus2x8) &= 0xfe;    /* adlib data IRQ dis? -> clear 2x8 adlib IRQ flag */
387 423d65f4 balrog
                if (!(GUSregb(TimerStatus2x8) & 0x19))
388 423d65f4 balrog
                    GUSregb(IRQStatReg2x6) &= 0xef;     /* 0xe6; $$clear IRQ if both IRQ bits are inactive or cleared */
389 423d65f4 balrog
                /* catch up delayed timer IRQs: */
390 423d65f4 balrog
                if ((GUSregw(TimerIRQs) > 1) && (GUSregb(TimerDataReg2x9) & 3))
391 423d65f4 balrog
                {
392 423d65f4 balrog
                    if (GUSregb(TimerDataReg2x9) & 1)   /* start timer 1 (80us decrement rate) */
393 423d65f4 balrog
                    {
394 423d65f4 balrog
                        if (!(GUSregb(TimerDataReg2x9) & 0x40))
395 423d65f4 balrog
                            GUSregb(TimerStatus2x8) |= 0xc0;    /* maskable bits */
396 423d65f4 balrog
                        if (data & 4) /* timer1 irq enable */
397 423d65f4 balrog
                        {
398 423d65f4 balrog
                            GUSregb(TimerStatus2x8) |= 4;       /* nonmaskable bit */
399 423d65f4 balrog
                            GUSregb(IRQStatReg2x6) |= 4;        /* timer 1 irq pending */
400 423d65f4 balrog
                        }
401 423d65f4 balrog
                    }
402 423d65f4 balrog
                    if (GUSregb(TimerDataReg2x9) & 2)   /* start timer 2 (320us decrement rate) */
403 423d65f4 balrog
                    {
404 423d65f4 balrog
                        if (!(GUSregb(TimerDataReg2x9) & 0x20))
405 423d65f4 balrog
                            GUSregb(TimerStatus2x8) |= 0xa0;    /* maskable bits */
406 423d65f4 balrog
                        if (data & 8) /* timer2 irq enable */
407 423d65f4 balrog
                        {
408 423d65f4 balrog
                            GUSregb(TimerStatus2x8) |= 2;       /* nonmaskable bit */
409 423d65f4 balrog
                            GUSregb(IRQStatReg2x6) |= 8;        /* timer 2 irq pending */
410 423d65f4 balrog
                        }
411 423d65f4 balrog
                    }
412 423d65f4 balrog
                    GUSregw(TimerIRQs)--;
413 423d65f4 balrog
                    if (GUSregw(BusyTimerIRQs) > 1)
414 423d65f4 balrog
                        GUSregw(BusyTimerIRQs)--;
415 423d65f4 balrog
                    else
416 423d65f4 balrog
                        GUSregw(BusyTimerIRQs) =
417 423d65f4 balrog
                            GUS_irqrequest(state, state->gusirq, GUSregw(TimerIRQs));
418 423d65f4 balrog
                }
419 423d65f4 balrog
                else
420 423d65f4 balrog
                    GUSregw(TimerIRQs) = 0;
421 423d65f4 balrog
422 423d65f4 balrog
                if (!(data & 0x04))
423 423d65f4 balrog
                {
424 423d65f4 balrog
                    GUSregb(TimerStatus2x8) &= 0xfb; /* clear non-maskable timer1 bit */
425 423d65f4 balrog
                    GUSregb(IRQStatReg2x6)  &= 0xfb;
426 423d65f4 balrog
                }
427 423d65f4 balrog
                if (!(data & 0x08))
428 423d65f4 balrog
                {
429 423d65f4 balrog
                    GUSregb(TimerStatus2x8) &= 0xfd; /* clear non-maskable timer2 bit */
430 423d65f4 balrog
                    GUSregb(IRQStatReg2x6)  &= 0xf7;
431 423d65f4 balrog
                }
432 423d65f4 balrog
                if (!GUSregb(IRQStatReg2x6))
433 423d65f4 balrog
                    GUS_irqclear(state, state->gusirq);
434 423d65f4 balrog
                break;
435 423d65f4 balrog
            case 0x46:          /* Counter1 */
436 423d65f4 balrog
                GUSregb(GUS46Counter1) = (GUSbyte) data;
437 423d65f4 balrog
                break;
438 423d65f4 balrog
            case 0x47:          /* Counter2 */
439 423d65f4 balrog
                GUSregb(GUS47Counter2) = (GUSbyte) data;
440 423d65f4 balrog
                break;
441 423d65f4 balrog
            /* case 0x48:       */ /* sampling freq reg not emulated (same as interwave) */
442 423d65f4 balrog
            case 0x49:          /* SampCtrlReg */
443 423d65f4 balrog
                GUSregb(GUS49SampCtrl) = (GUSbyte) data;
444 423d65f4 balrog
                break;
445 423d65f4 balrog
            /* case 0x4b:       */ /* joystick trim not emulated */
446 423d65f4 balrog
            case 0x4c:          /* GUSreset */
447 423d65f4 balrog
                GUSregb(GUS4cReset) = (GUSbyte) data;
448 423d65f4 balrog
                if (!(GUSregb(GUS4cReset) & 1)) /* reset... */
449 423d65f4 balrog
                {
450 423d65f4 balrog
                    GUSregd(voicewavetableirq) = 0;
451 423d65f4 balrog
                    GUSregd(voicevolrampirq) = 0;
452 423d65f4 balrog
                    GUSregw(TimerIRQs) = 0;
453 423d65f4 balrog
                    GUSregw(BusyTimerIRQs) = 0;
454 423d65f4 balrog
                    GUSregb(NumVoices) = 0xcd;
455 423d65f4 balrog
                    GUSregb(IRQStatReg2x6) = 0;
456 423d65f4 balrog
                    GUSregb(TimerStatus2x8) = 0;
457 423d65f4 balrog
                    GUSregb(AdLibData2x9) = 0;
458 423d65f4 balrog
                    GUSregb(TimerDataReg2x9) = 0;
459 423d65f4 balrog
                    GUSregb(GUS41DMACtrl) = 0;
460 423d65f4 balrog
                    GUSregb(GUS45TimerCtrl) = 0;
461 423d65f4 balrog
                    GUSregb(GUS49SampCtrl) = 0;
462 423d65f4 balrog
                    GUSregb(GUS4cReset) &= 0xf9; /* clear IRQ and DAC enable bits */
463 423d65f4 balrog
                    GUS_irqclear(state, state->gusirq);
464 423d65f4 balrog
                }
465 423d65f4 balrog
                /* IRQ enable bit checked elsewhere */
466 423d65f4 balrog
                /* EnableDAC bit may be used by external callers */
467 423d65f4 balrog
                break;
468 423d65f4 balrog
            }
469 423d65f4 balrog
        }
470 423d65f4 balrog
        break;
471 423d65f4 balrog
    case 0x307:                /* DRAMaccess */
472 423d65f4 balrog
        {
473 423d65f4 balrog
            GUSbyte        *adr;
474 423d65f4 balrog
            adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);
475 423d65f4 balrog
            *adr = (GUSbyte) data;
476 423d65f4 balrog
        }
477 423d65f4 balrog
        break;
478 423d65f4 balrog
    }
479 423d65f4 balrog
}
480 423d65f4 balrog
481 423d65f4 balrog
/* Attention when breaking up a single DMA transfer to multiple ones:
482 423d65f4 balrog
 * it may lead to multiple terminal count interrupts and broken transfers:
483 423d65f4 balrog
 *
484 423d65f4 balrog
 * 1. Whenever you transfer a piece of data, the gusemu callback is invoked
485 423d65f4 balrog
 * 2. The callback may generate a TC irq (if the register was set up to do so)
486 423d65f4 balrog
 * 3. The irq may result in the program using the GUS to reprogram the GUS
487 423d65f4 balrog
 *
488 423d65f4 balrog
 * Some programs also decide to upload by just checking if TC occurs
489 423d65f4 balrog
 * (via interrupt or a cleared GUS dma flag)
490 423d65f4 balrog
 * and then start the next transfer, without checking DMA state
491 423d65f4 balrog
 *
492 423d65f4 balrog
 * Thus: Always make sure to set the TC flag correctly!
493 423d65f4 balrog
 *
494 423d65f4 balrog
 * Note that the genuine GUS had a granularity of 16 bytes/words for low/high DMA
495 423d65f4 balrog
 * while later cards had atomic granularity provided by an additional GUS50DMAHigh register
496 423d65f4 balrog
 * GUSemu also uses this register to support byte-granular transfers for better compatibility
497 423d65f4 balrog
 * with emulators other than GUSemu32
498 423d65f4 balrog
 */
499 423d65f4 balrog
500 423d65f4 balrog
void gus_dma_transferdata(GUSEmuState * state, char *dma_addr, unsigned int count, int TC)
501 423d65f4 balrog
{
502 423d65f4 balrog
    /* this function gets called by the callback function as soon as a DMA transfer is about to start
503 423d65f4 balrog
     * dma_addr is a translated address within accessible memory, not the physical one,
504 423d65f4 balrog
     * count is (real dma count register)+1
505 66a0a2cb Dong Xu Wang
     * note that the amount of bytes transferred is fully determined by values in the DMA registers
506 423d65f4 balrog
     * do not forget to update DMA states after transferring the entire block:
507 423d65f4 balrog
     * DREQ cleared & TC asserted after the _whole_ transfer */
508 423d65f4 balrog
509 423d65f4 balrog
    char           *srcaddr;
510 423d65f4 balrog
    char           *destaddr;
511 423d65f4 balrog
    char            msbmask = 0;
512 423d65f4 balrog
    GUSbyte        *gusptr;
513 423d65f4 balrog
    gusptr = state->gusdatapos;
514 423d65f4 balrog
515 423d65f4 balrog
    srcaddr = dma_addr; /* system memory address */
516 423d65f4 balrog
    {
517 423d65f4 balrog
        int             offset = (GUSregw(GUS42DMAStart) << 4) + (GUSregb(GUS50DMAHigh) & 0xf);
518 423d65f4 balrog
        if (state->gusdma >= 4)
519 423d65f4 balrog
            offset = (offset & 0xc0000) + (2 * (offset & 0x1fff0)); /* 16 bit address translation */
520 66a0a2cb Dong Xu Wang
        destaddr = (char *) state->himemaddr + offset; /* wavetable RAM address */
521 423d65f4 balrog
    }
522 423d65f4 balrog
523 423d65f4 balrog
    GUSregw(GUS42DMAStart) += (GUSword)  (count >> 4);                           /* ToDo: add 16bit GUS page limit? */
524 423d65f4 balrog
    GUSregb(GUS50DMAHigh)   = (GUSbyte) ((count + GUSregb(GUS50DMAHigh)) & 0xf); /* ToDo: add 16bit GUS page limit? */
525 423d65f4 balrog
526 423d65f4 balrog
    if (GUSregb(GUS41DMACtrl) & 0x02)   /* direction, 0 := sysram->gusram */
527 423d65f4 balrog
    {
528 423d65f4 balrog
        char           *tmpaddr = destaddr;
529 423d65f4 balrog
        destaddr = srcaddr;
530 423d65f4 balrog
        srcaddr = tmpaddr;
531 423d65f4 balrog
    }
532 423d65f4 balrog
533 423d65f4 balrog
    if ((GUSregb(GUS41DMACtrl) & 0x80) && (!(GUSregb(GUS41DMACtrl) & 0x02)))
534 423d65f4 balrog
        msbmask = (const char) 0x80;    /* invert MSB */
535 423d65f4 balrog
    for (; count > 0; count--)
536 423d65f4 balrog
    {
537 423d65f4 balrog
        if (GUSregb(GUS41DMACtrl) & 0x40)
538 423d65f4 balrog
            *(destaddr++) = *(srcaddr++);               /* 16 bit lobyte */
539 423d65f4 balrog
        else
540 423d65f4 balrog
            *(destaddr++) = (msbmask ^ (*(srcaddr++))); /* 8 bit */
541 423d65f4 balrog
        if (state->gusdma >= 4)
542 423d65f4 balrog
            *(destaddr++) = (msbmask ^ (*(srcaddr++))); /* 16 bit hibyte */
543 423d65f4 balrog
    }
544 423d65f4 balrog
545 423d65f4 balrog
    if (TC)
546 423d65f4 balrog
    {
547 423d65f4 balrog
        (GUSregb(GUS41DMACtrl)) &= 0xfe;        /* clear DMA request bit */
548 423d65f4 balrog
        if (GUSregb(GUS41DMACtrl) & 0x20)       /* DMA terminal count IRQ */
549 423d65f4 balrog
        {
550 423d65f4 balrog
            GUSregb(IRQStatReg2x6) |= 0x80;
551 423d65f4 balrog
            GUS_irqrequest(state, state->gusirq, 1);
552 423d65f4 balrog
        }
553 423d65f4 balrog
    }
554 423d65f4 balrog
}