root / hw / misc / imx_ccm.c @ a8aec295
History | View | Annotate | Download (8.1 kB)
1 | bcc181b0 | Peter Chubb | /*
|
---|---|---|---|
2 | bcc181b0 | Peter Chubb | * IMX31 Clock Control Module
|
3 | bcc181b0 | Peter Chubb | *
|
4 | bcc181b0 | Peter Chubb | * Copyright (C) 2012 NICTA
|
5 | bcc181b0 | Peter Chubb | *
|
6 | bcc181b0 | Peter Chubb | * This work is licensed under the terms of the GNU GPL, version 2 or later.
|
7 | bcc181b0 | Peter Chubb | * See the COPYING file in the top-level directory.
|
8 | bcc181b0 | Peter Chubb | *
|
9 | bcc181b0 | Peter Chubb | * To get the timer frequencies right, we need to emulate at least part of
|
10 | bcc181b0 | Peter Chubb | * the CCM.
|
11 | bcc181b0 | Peter Chubb | */
|
12 | bcc181b0 | Peter Chubb | |
13 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
14 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
15 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
16 | 0d09e41a | Paolo Bonzini | #include "hw/arm/imx.h" |
17 | bcc181b0 | Peter Chubb | |
18 | bcc181b0 | Peter Chubb | #define CKIH_FREQ 26000000 /* 26MHz crystal input */ |
19 | bcc181b0 | Peter Chubb | #define CKIL_FREQ 32768 /* nominal 32khz clock */ |
20 | bcc181b0 | Peter Chubb | |
21 | bcc181b0 | Peter Chubb | |
22 | bcc181b0 | Peter Chubb | //#define DEBUG_CCM 1
|
23 | bcc181b0 | Peter Chubb | #ifdef DEBUG_CCM
|
24 | bcc181b0 | Peter Chubb | #define DPRINTF(fmt, args...) \
|
25 | bcc181b0 | Peter Chubb | do { printf("imx_ccm: " fmt , ##args); } while (0) |
26 | bcc181b0 | Peter Chubb | #else
|
27 | bcc181b0 | Peter Chubb | #define DPRINTF(fmt, args...) do {} while (0) |
28 | bcc181b0 | Peter Chubb | #endif
|
29 | bcc181b0 | Peter Chubb | |
30 | bcc181b0 | Peter Chubb | static int imx_ccm_post_load(void *opaque, int version_id); |
31 | bcc181b0 | Peter Chubb | |
32 | bcc181b0 | Peter Chubb | typedef struct { |
33 | bcc181b0 | Peter Chubb | SysBusDevice busdev; |
34 | bcc181b0 | Peter Chubb | MemoryRegion iomem; |
35 | bcc181b0 | Peter Chubb | |
36 | bcc181b0 | Peter Chubb | uint32_t ccmr; |
37 | bcc181b0 | Peter Chubb | uint32_t pdr0; |
38 | bcc181b0 | Peter Chubb | uint32_t pdr1; |
39 | bcc181b0 | Peter Chubb | uint32_t mpctl; |
40 | bcc181b0 | Peter Chubb | uint32_t spctl; |
41 | bcc181b0 | Peter Chubb | uint32_t cgr[3];
|
42 | bcc181b0 | Peter Chubb | uint32_t pmcr0; |
43 | bcc181b0 | Peter Chubb | uint32_t pmcr1; |
44 | bcc181b0 | Peter Chubb | |
45 | bcc181b0 | Peter Chubb | /* Frequencies precalculated on register changes */
|
46 | bcc181b0 | Peter Chubb | uint32_t pll_refclk_freq; |
47 | bcc181b0 | Peter Chubb | uint32_t mcu_clk_freq; |
48 | bcc181b0 | Peter Chubb | uint32_t hsp_clk_freq; |
49 | bcc181b0 | Peter Chubb | uint32_t ipg_clk_freq; |
50 | bcc181b0 | Peter Chubb | } IMXCCMState; |
51 | bcc181b0 | Peter Chubb | |
52 | bcc181b0 | Peter Chubb | static const VMStateDescription vmstate_imx_ccm = { |
53 | bcc181b0 | Peter Chubb | .name = "imx-ccm",
|
54 | bcc181b0 | Peter Chubb | .version_id = 1,
|
55 | bcc181b0 | Peter Chubb | .minimum_version_id = 1,
|
56 | bcc181b0 | Peter Chubb | .minimum_version_id_old = 1,
|
57 | bcc181b0 | Peter Chubb | .fields = (VMStateField[]) { |
58 | bcc181b0 | Peter Chubb | VMSTATE_UINT32(ccmr, IMXCCMState), |
59 | bcc181b0 | Peter Chubb | VMSTATE_UINT32(pdr0, IMXCCMState), |
60 | bcc181b0 | Peter Chubb | VMSTATE_UINT32(pdr1, IMXCCMState), |
61 | bcc181b0 | Peter Chubb | VMSTATE_UINT32(mpctl, IMXCCMState), |
62 | bcc181b0 | Peter Chubb | VMSTATE_UINT32(spctl, IMXCCMState), |
63 | bcc181b0 | Peter Chubb | VMSTATE_UINT32_ARRAY(cgr, IMXCCMState, 3),
|
64 | bcc181b0 | Peter Chubb | VMSTATE_UINT32(pmcr0, IMXCCMState), |
65 | bcc181b0 | Peter Chubb | VMSTATE_UINT32(pmcr1, IMXCCMState), |
66 | bcc181b0 | Peter Chubb | VMSTATE_UINT32(pll_refclk_freq, IMXCCMState), |
67 | bcc181b0 | Peter Chubb | }, |
68 | bcc181b0 | Peter Chubb | .post_load = imx_ccm_post_load, |
69 | bcc181b0 | Peter Chubb | }; |
70 | bcc181b0 | Peter Chubb | |
71 | bcc181b0 | Peter Chubb | /* CCMR */
|
72 | bcc181b0 | Peter Chubb | #define CCMR_FPME (1<<0) |
73 | bcc181b0 | Peter Chubb | #define CCMR_MPE (1<<3) |
74 | bcc181b0 | Peter Chubb | #define CCMR_MDS (1<<7) |
75 | bcc181b0 | Peter Chubb | #define CCMR_FPMF (1<<26) |
76 | bcc181b0 | Peter Chubb | #define CCMR_PRCS (3<<1) |
77 | bcc181b0 | Peter Chubb | |
78 | bcc181b0 | Peter Chubb | /* PDR0 */
|
79 | bcc181b0 | Peter Chubb | #define PDR0_MCU_PODF_SHIFT (0) |
80 | bcc181b0 | Peter Chubb | #define PDR0_MCU_PODF_MASK (0x7) |
81 | bcc181b0 | Peter Chubb | #define PDR0_MAX_PODF_SHIFT (3) |
82 | bcc181b0 | Peter Chubb | #define PDR0_MAX_PODF_MASK (0x7) |
83 | bcc181b0 | Peter Chubb | #define PDR0_IPG_PODF_SHIFT (6) |
84 | bcc181b0 | Peter Chubb | #define PDR0_IPG_PODF_MASK (0x3) |
85 | bcc181b0 | Peter Chubb | #define PDR0_NFC_PODF_SHIFT (8) |
86 | bcc181b0 | Peter Chubb | #define PDR0_NFC_PODF_MASK (0x7) |
87 | bcc181b0 | Peter Chubb | #define PDR0_HSP_PODF_SHIFT (11) |
88 | bcc181b0 | Peter Chubb | #define PDR0_HSP_PODF_MASK (0x7) |
89 | bcc181b0 | Peter Chubb | #define PDR0_PER_PODF_SHIFT (16) |
90 | bcc181b0 | Peter Chubb | #define PDR0_PER_PODF_MASK (0x1f) |
91 | bcc181b0 | Peter Chubb | #define PDR0_CSI_PODF_SHIFT (23) |
92 | bcc181b0 | Peter Chubb | #define PDR0_CSI_PODF_MASK (0x1ff) |
93 | bcc181b0 | Peter Chubb | |
94 | bcc181b0 | Peter Chubb | #define EXTRACT(value, name) (((value) >> PDR0_##name##_PODF_SHIFT) \ |
95 | bcc181b0 | Peter Chubb | & PDR0_##name##_PODF_MASK) |
96 | bcc181b0 | Peter Chubb | #define INSERT(value, name) (((value) & PDR0_##name##_PODF_MASK) << \ |
97 | bcc181b0 | Peter Chubb | PDR0_##name##_PODF_SHIFT) |
98 | bcc181b0 | Peter Chubb | /* PLL control registers */
|
99 | bcc181b0 | Peter Chubb | #define PD(v) (((v) >> 26) & 0xf) |
100 | bcc181b0 | Peter Chubb | #define MFD(v) (((v) >> 16) & 0x3ff) |
101 | bcc181b0 | Peter Chubb | #define MFI(v) (((v) >> 10) & 0xf); |
102 | bcc181b0 | Peter Chubb | #define MFN(v) ((v) & 0x3ff) |
103 | bcc181b0 | Peter Chubb | |
104 | bcc181b0 | Peter Chubb | #define PLL_PD(x) (((x) & 0xf) << 26) |
105 | bcc181b0 | Peter Chubb | #define PLL_MFD(x) (((x) & 0x3ff) << 16) |
106 | bcc181b0 | Peter Chubb | #define PLL_MFI(x) (((x) & 0xf) << 10) |
107 | bcc181b0 | Peter Chubb | #define PLL_MFN(x) (((x) & 0x3ff) << 0) |
108 | bcc181b0 | Peter Chubb | |
109 | bcc181b0 | Peter Chubb | uint32_t imx_clock_frequency(DeviceState *dev, IMXClk clock) |
110 | bcc181b0 | Peter Chubb | { |
111 | bcc181b0 | Peter Chubb | IMXCCMState *s = container_of(dev, IMXCCMState, busdev.qdev); |
112 | bcc181b0 | Peter Chubb | |
113 | bcc181b0 | Peter Chubb | switch (clock) {
|
114 | bcc181b0 | Peter Chubb | case NOCLK:
|
115 | bcc181b0 | Peter Chubb | return 0; |
116 | bcc181b0 | Peter Chubb | case MCU:
|
117 | bcc181b0 | Peter Chubb | return s->mcu_clk_freq;
|
118 | bcc181b0 | Peter Chubb | case HSP:
|
119 | bcc181b0 | Peter Chubb | return s->hsp_clk_freq;
|
120 | bcc181b0 | Peter Chubb | case IPG:
|
121 | bcc181b0 | Peter Chubb | return s->ipg_clk_freq;
|
122 | bcc181b0 | Peter Chubb | case CLK_32k:
|
123 | bcc181b0 | Peter Chubb | return CKIL_FREQ;
|
124 | bcc181b0 | Peter Chubb | } |
125 | bcc181b0 | Peter Chubb | return 0; |
126 | bcc181b0 | Peter Chubb | } |
127 | bcc181b0 | Peter Chubb | |
128 | bcc181b0 | Peter Chubb | /*
|
129 | bcc181b0 | Peter Chubb | * Calculate PLL output frequency
|
130 | bcc181b0 | Peter Chubb | */
|
131 | bcc181b0 | Peter Chubb | static uint32_t calc_pll(uint32_t pllreg, uint32_t base_freq)
|
132 | bcc181b0 | Peter Chubb | { |
133 | bcc181b0 | Peter Chubb | int32_t mfn = MFN(pllreg); /* Numerator */
|
134 | bcc181b0 | Peter Chubb | uint32_t mfi = MFI(pllreg); /* Integer part */
|
135 | bcc181b0 | Peter Chubb | uint32_t mfd = 1 + MFD(pllreg); /* Denominator */ |
136 | bcc181b0 | Peter Chubb | uint32_t pd = 1 + PD(pllreg); /* Pre-divider */ |
137 | bcc181b0 | Peter Chubb | |
138 | bcc181b0 | Peter Chubb | if (mfi < 5) { |
139 | bcc181b0 | Peter Chubb | mfi = 5;
|
140 | bcc181b0 | Peter Chubb | } |
141 | bcc181b0 | Peter Chubb | /* mfn is 10-bit signed twos-complement */
|
142 | bcc181b0 | Peter Chubb | mfn <<= 32 - 10; |
143 | bcc181b0 | Peter Chubb | mfn >>= 32 - 10; |
144 | bcc181b0 | Peter Chubb | |
145 | bcc181b0 | Peter Chubb | return ((2 * (base_freq >> 10) * (mfi * mfd + mfn)) / |
146 | bcc181b0 | Peter Chubb | (mfd * pd)) << 10;
|
147 | bcc181b0 | Peter Chubb | } |
148 | bcc181b0 | Peter Chubb | |
149 | bcc181b0 | Peter Chubb | static void update_clocks(IMXCCMState *s) |
150 | bcc181b0 | Peter Chubb | { |
151 | bcc181b0 | Peter Chubb | /*
|
152 | bcc181b0 | Peter Chubb | * If we ever emulate more clocks, this should switch to a data-driven
|
153 | bcc181b0 | Peter Chubb | * approach
|
154 | bcc181b0 | Peter Chubb | */
|
155 | bcc181b0 | Peter Chubb | |
156 | f3c8fac2 | Stefan Weil | if ((s->ccmr & CCMR_PRCS) == 2) { |
157 | bcc181b0 | Peter Chubb | s->pll_refclk_freq = CKIL_FREQ * 1024;
|
158 | bcc181b0 | Peter Chubb | } else {
|
159 | bcc181b0 | Peter Chubb | s->pll_refclk_freq = CKIH_FREQ; |
160 | bcc181b0 | Peter Chubb | } |
161 | bcc181b0 | Peter Chubb | |
162 | bcc181b0 | Peter Chubb | /* ipg_clk_arm aka MCU clock */
|
163 | bcc181b0 | Peter Chubb | if ((s->ccmr & CCMR_MDS) || !(s->ccmr & CCMR_MPE)) {
|
164 | bcc181b0 | Peter Chubb | s->mcu_clk_freq = s->pll_refclk_freq; |
165 | bcc181b0 | Peter Chubb | } else {
|
166 | bcc181b0 | Peter Chubb | s->mcu_clk_freq = calc_pll(s->mpctl, s->pll_refclk_freq); |
167 | bcc181b0 | Peter Chubb | } |
168 | bcc181b0 | Peter Chubb | |
169 | bcc181b0 | Peter Chubb | /* High-speed clock */
|
170 | bcc181b0 | Peter Chubb | s->hsp_clk_freq = s->mcu_clk_freq / (1 + EXTRACT(s->pdr0, HSP));
|
171 | bcc181b0 | Peter Chubb | s->ipg_clk_freq = s->hsp_clk_freq / (1 + EXTRACT(s->pdr0, IPG));
|
172 | bcc181b0 | Peter Chubb | |
173 | bcc181b0 | Peter Chubb | DPRINTF("Clocks: mcu %uMHz, HSP %uMHz, IPG %uHz\n",
|
174 | bcc181b0 | Peter Chubb | s->mcu_clk_freq / 1000000,
|
175 | bcc181b0 | Peter Chubb | s->hsp_clk_freq / 1000000,
|
176 | bcc181b0 | Peter Chubb | s->ipg_clk_freq); |
177 | bcc181b0 | Peter Chubb | } |
178 | bcc181b0 | Peter Chubb | |
179 | bcc181b0 | Peter Chubb | static void imx_ccm_reset(DeviceState *dev) |
180 | bcc181b0 | Peter Chubb | { |
181 | bcc181b0 | Peter Chubb | IMXCCMState *s = container_of(dev, IMXCCMState, busdev.qdev); |
182 | bcc181b0 | Peter Chubb | |
183 | bcc181b0 | Peter Chubb | s->ccmr = 0x074b0b7b;
|
184 | bcc181b0 | Peter Chubb | s->pdr0 = 0xff870b48;
|
185 | bcc181b0 | Peter Chubb | s->pdr1 = 0x49fcfe7f;
|
186 | bcc181b0 | Peter Chubb | s->mpctl = PLL_PD(1) | PLL_MFD(0) | PLL_MFI(6) | PLL_MFN(0); |
187 | bcc181b0 | Peter Chubb | s->cgr[0] = s->cgr[1] = s->cgr[2] = 0xffffffff; |
188 | bcc181b0 | Peter Chubb | s->spctl = PLL_PD(1) | PLL_MFD(4) | PLL_MFI(0xc) | PLL_MFN(1); |
189 | bcc181b0 | Peter Chubb | s->pmcr0 = 0x80209828;
|
190 | bcc181b0 | Peter Chubb | |
191 | bcc181b0 | Peter Chubb | update_clocks(s); |
192 | bcc181b0 | Peter Chubb | } |
193 | bcc181b0 | Peter Chubb | |
194 | a8170e5e | Avi Kivity | static uint64_t imx_ccm_read(void *opaque, hwaddr offset, |
195 | bcc181b0 | Peter Chubb | unsigned size)
|
196 | bcc181b0 | Peter Chubb | { |
197 | bcc181b0 | Peter Chubb | IMXCCMState *s = (IMXCCMState *)opaque; |
198 | bcc181b0 | Peter Chubb | |
199 | bcc181b0 | Peter Chubb | DPRINTF("read(offset=%x)", offset >> 2); |
200 | bcc181b0 | Peter Chubb | switch (offset >> 2) { |
201 | bcc181b0 | Peter Chubb | case 0: /* CCMR */ |
202 | bcc181b0 | Peter Chubb | DPRINTF(" ccmr = 0x%x\n", s->ccmr);
|
203 | bcc181b0 | Peter Chubb | return s->ccmr;
|
204 | bcc181b0 | Peter Chubb | case 1: |
205 | bcc181b0 | Peter Chubb | DPRINTF(" pdr0 = 0x%x\n", s->pdr0);
|
206 | bcc181b0 | Peter Chubb | return s->pdr0;
|
207 | bcc181b0 | Peter Chubb | case 2: |
208 | bcc181b0 | Peter Chubb | DPRINTF(" pdr1 = 0x%x\n", s->pdr1);
|
209 | bcc181b0 | Peter Chubb | return s->pdr1;
|
210 | bcc181b0 | Peter Chubb | case 4: |
211 | bcc181b0 | Peter Chubb | DPRINTF(" mpctl = 0x%x\n", s->mpctl);
|
212 | bcc181b0 | Peter Chubb | return s->mpctl;
|
213 | bcc181b0 | Peter Chubb | case 6: |
214 | bcc181b0 | Peter Chubb | DPRINTF(" spctl = 0x%x\n", s->spctl);
|
215 | bcc181b0 | Peter Chubb | return s->spctl;
|
216 | bcc181b0 | Peter Chubb | case 8: |
217 | bcc181b0 | Peter Chubb | DPRINTF(" cgr0 = 0x%x\n", s->cgr[0]); |
218 | bcc181b0 | Peter Chubb | return s->cgr[0]; |
219 | bcc181b0 | Peter Chubb | case 9: |
220 | bcc181b0 | Peter Chubb | DPRINTF(" cgr1 = 0x%x\n", s->cgr[1]); |
221 | bcc181b0 | Peter Chubb | return s->cgr[1]; |
222 | bcc181b0 | Peter Chubb | case 10: |
223 | bcc181b0 | Peter Chubb | DPRINTF(" cgr2 = 0x%x\n", s->cgr[2]); |
224 | bcc181b0 | Peter Chubb | return s->cgr[2]; |
225 | bcc181b0 | Peter Chubb | case 18: /* LTR1 */ |
226 | bcc181b0 | Peter Chubb | return 0x00004040; |
227 | bcc181b0 | Peter Chubb | case 23: |
228 | bcc181b0 | Peter Chubb | DPRINTF(" pcmr0 = 0x%x\n", s->pmcr0);
|
229 | bcc181b0 | Peter Chubb | return s->pmcr0;
|
230 | bcc181b0 | Peter Chubb | } |
231 | bcc181b0 | Peter Chubb | DPRINTF(" return 0\n");
|
232 | bcc181b0 | Peter Chubb | return 0; |
233 | bcc181b0 | Peter Chubb | } |
234 | bcc181b0 | Peter Chubb | |
235 | a8170e5e | Avi Kivity | static void imx_ccm_write(void *opaque, hwaddr offset, |
236 | bcc181b0 | Peter Chubb | uint64_t value, unsigned size)
|
237 | bcc181b0 | Peter Chubb | { |
238 | bcc181b0 | Peter Chubb | IMXCCMState *s = (IMXCCMState *)opaque; |
239 | bcc181b0 | Peter Chubb | |
240 | bcc181b0 | Peter Chubb | DPRINTF("write(offset=%x, value = %x)\n",
|
241 | bcc181b0 | Peter Chubb | offset >> 2, (unsigned int)value); |
242 | bcc181b0 | Peter Chubb | switch (offset >> 2) { |
243 | bcc181b0 | Peter Chubb | case 0: |
244 | bcc181b0 | Peter Chubb | s->ccmr = CCMR_FPMF | (value & 0x3b6fdfff);
|
245 | bcc181b0 | Peter Chubb | break;
|
246 | bcc181b0 | Peter Chubb | case 1: |
247 | bcc181b0 | Peter Chubb | s->pdr0 = value & 0xff9f3fff;
|
248 | bcc181b0 | Peter Chubb | break;
|
249 | bcc181b0 | Peter Chubb | case 2: |
250 | bcc181b0 | Peter Chubb | s->pdr1 = value; |
251 | bcc181b0 | Peter Chubb | break;
|
252 | bcc181b0 | Peter Chubb | case 4: |
253 | bcc181b0 | Peter Chubb | s->mpctl = value & 0xbfff3fff;
|
254 | bcc181b0 | Peter Chubb | break;
|
255 | bcc181b0 | Peter Chubb | case 6: |
256 | bcc181b0 | Peter Chubb | s->spctl = value & 0xbfff3fff;
|
257 | bcc181b0 | Peter Chubb | break;
|
258 | bcc181b0 | Peter Chubb | case 8: |
259 | bcc181b0 | Peter Chubb | s->cgr[0] = value;
|
260 | bcc181b0 | Peter Chubb | return;
|
261 | bcc181b0 | Peter Chubb | case 9: |
262 | bcc181b0 | Peter Chubb | s->cgr[1] = value;
|
263 | bcc181b0 | Peter Chubb | return;
|
264 | bcc181b0 | Peter Chubb | case 10: |
265 | bcc181b0 | Peter Chubb | s->cgr[2] = value;
|
266 | bcc181b0 | Peter Chubb | return;
|
267 | bcc181b0 | Peter Chubb | |
268 | bcc181b0 | Peter Chubb | default:
|
269 | bcc181b0 | Peter Chubb | return;
|
270 | bcc181b0 | Peter Chubb | } |
271 | bcc181b0 | Peter Chubb | update_clocks(s); |
272 | bcc181b0 | Peter Chubb | } |
273 | bcc181b0 | Peter Chubb | |
274 | bcc181b0 | Peter Chubb | static const struct MemoryRegionOps imx_ccm_ops = { |
275 | bcc181b0 | Peter Chubb | .read = imx_ccm_read, |
276 | bcc181b0 | Peter Chubb | .write = imx_ccm_write, |
277 | bcc181b0 | Peter Chubb | .endianness = DEVICE_NATIVE_ENDIAN, |
278 | bcc181b0 | Peter Chubb | }; |
279 | bcc181b0 | Peter Chubb | |
280 | bcc181b0 | Peter Chubb | static int imx_ccm_init(SysBusDevice *dev) |
281 | bcc181b0 | Peter Chubb | { |
282 | bcc181b0 | Peter Chubb | IMXCCMState *s = FROM_SYSBUS(typeof(*s), dev); |
283 | bcc181b0 | Peter Chubb | |
284 | bcc181b0 | Peter Chubb | memory_region_init_io(&s->iomem, &imx_ccm_ops, s, "imx_ccm", 0x1000); |
285 | bcc181b0 | Peter Chubb | sysbus_init_mmio(dev, &s->iomem); |
286 | bcc181b0 | Peter Chubb | |
287 | bcc181b0 | Peter Chubb | return 0; |
288 | bcc181b0 | Peter Chubb | } |
289 | bcc181b0 | Peter Chubb | |
290 | bcc181b0 | Peter Chubb | static int imx_ccm_post_load(void *opaque, int version_id) |
291 | bcc181b0 | Peter Chubb | { |
292 | bcc181b0 | Peter Chubb | IMXCCMState *s = (IMXCCMState *)opaque; |
293 | bcc181b0 | Peter Chubb | |
294 | bcc181b0 | Peter Chubb | update_clocks(s); |
295 | bcc181b0 | Peter Chubb | return 0; |
296 | bcc181b0 | Peter Chubb | } |
297 | bcc181b0 | Peter Chubb | |
298 | bcc181b0 | Peter Chubb | static void imx_ccm_class_init(ObjectClass *klass, void *data) |
299 | bcc181b0 | Peter Chubb | { |
300 | bcc181b0 | Peter Chubb | DeviceClass *dc = DEVICE_CLASS(klass); |
301 | bcc181b0 | Peter Chubb | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
302 | bcc181b0 | Peter Chubb | |
303 | bcc181b0 | Peter Chubb | sbc->init = imx_ccm_init; |
304 | bcc181b0 | Peter Chubb | dc->reset = imx_ccm_reset; |
305 | bcc181b0 | Peter Chubb | dc->vmsd = &vmstate_imx_ccm; |
306 | bcc181b0 | Peter Chubb | dc->desc = "i.MX Clock Control Module";
|
307 | bcc181b0 | Peter Chubb | } |
308 | bcc181b0 | Peter Chubb | |
309 | 8c43a6f0 | Andreas Färber | static const TypeInfo imx_ccm_info = { |
310 | bcc181b0 | Peter Chubb | .name = "imx_ccm",
|
311 | bcc181b0 | Peter Chubb | .parent = TYPE_SYS_BUS_DEVICE, |
312 | bcc181b0 | Peter Chubb | .instance_size = sizeof(IMXCCMState),
|
313 | bcc181b0 | Peter Chubb | .class_init = imx_ccm_class_init, |
314 | bcc181b0 | Peter Chubb | }; |
315 | bcc181b0 | Peter Chubb | |
316 | bcc181b0 | Peter Chubb | static void imx_ccm_register_types(void) |
317 | bcc181b0 | Peter Chubb | { |
318 | bcc181b0 | Peter Chubb | type_register_static(&imx_ccm_info); |
319 | bcc181b0 | Peter Chubb | } |
320 | bcc181b0 | Peter Chubb | |
321 | bcc181b0 | Peter Chubb | type_init(imx_ccm_register_types) |