root / hw / misc / lm32_sys.c @ a8aec295
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1 | f19410ca | Michael Walle | /*
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2 | f19410ca | Michael Walle | * QEMU model of the LatticeMico32 system control block.
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3 | f19410ca | Michael Walle | *
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4 | f19410ca | Michael Walle | * Copyright (c) 2010 Michael Walle <michael@walle.cc>
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5 | f19410ca | Michael Walle | *
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6 | f19410ca | Michael Walle | * This library is free software; you can redistribute it and/or
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7 | f19410ca | Michael Walle | * modify it under the terms of the GNU Lesser General Public
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8 | f19410ca | Michael Walle | * License as published by the Free Software Foundation; either
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9 | f19410ca | Michael Walle | * version 2 of the License, or (at your option) any later version.
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10 | f19410ca | Michael Walle | *
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11 | f19410ca | Michael Walle | * This library is distributed in the hope that it will be useful,
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12 | f19410ca | Michael Walle | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | f19410ca | Michael Walle | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | f19410ca | Michael Walle | * Lesser General Public License for more details.
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15 | f19410ca | Michael Walle | *
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16 | f19410ca | Michael Walle | * You should have received a copy of the GNU Lesser General Public
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17 | f19410ca | Michael Walle | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | f19410ca | Michael Walle | */
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19 | f19410ca | Michael Walle | |
20 | f19410ca | Michael Walle | /*
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21 | f19410ca | Michael Walle | * This model is mainly intended for testing purposes and doesn't fit to any
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22 | f19410ca | Michael Walle | * real hardware. On the one hand it provides a control register (R_CTRL) on
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23 | f19410ca | Michael Walle | * the other hand it supports the lm32 tests.
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24 | f19410ca | Michael Walle | *
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25 | f19410ca | Michael Walle | * A write to the control register causes a system shutdown.
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26 | f19410ca | Michael Walle | * Tests first write the pointer to a test name to the test name register
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27 | f19410ca | Michael Walle | * (R_TESTNAME) and then write a zero to the pass/fail register (R_PASSFAIL) if
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28 | f19410ca | Michael Walle | * the test is passed or any non-zero value to it if the test is failed.
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29 | f19410ca | Michael Walle | */
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30 | f19410ca | Michael Walle | |
31 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
32 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
33 | f19410ca | Michael Walle | #include "trace.h" |
34 | 1de7afc9 | Paolo Bonzini | #include "qemu/log.h" |
35 | 1de7afc9 | Paolo Bonzini | #include "qemu/error-report.h" |
36 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
37 | f19410ca | Michael Walle | |
38 | f19410ca | Michael Walle | enum {
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39 | f19410ca | Michael Walle | R_CTRL = 0,
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40 | f19410ca | Michael Walle | R_PASSFAIL, |
41 | f19410ca | Michael Walle | R_TESTNAME, |
42 | f19410ca | Michael Walle | R_MAX |
43 | f19410ca | Michael Walle | }; |
44 | f19410ca | Michael Walle | |
45 | f19410ca | Michael Walle | #define MAX_TESTNAME_LEN 16 |
46 | f19410ca | Michael Walle | |
47 | f19410ca | Michael Walle | struct LM32SysState {
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48 | f19410ca | Michael Walle | SysBusDevice busdev; |
49 | 0aa27efa | Benoît Canet | MemoryRegion iomem; |
50 | f19410ca | Michael Walle | uint32_t base; |
51 | f19410ca | Michael Walle | uint32_t regs[R_MAX]; |
52 | f19410ca | Michael Walle | uint8_t testname[MAX_TESTNAME_LEN]; |
53 | f19410ca | Michael Walle | }; |
54 | f19410ca | Michael Walle | typedef struct LM32SysState LM32SysState; |
55 | f19410ca | Michael Walle | |
56 | f19410ca | Michael Walle | static void copy_testname(LM32SysState *s) |
57 | f19410ca | Michael Walle | { |
58 | f19410ca | Michael Walle | cpu_physical_memory_read(s->regs[R_TESTNAME], s->testname, |
59 | f19410ca | Michael Walle | MAX_TESTNAME_LEN); |
60 | f19410ca | Michael Walle | s->testname[MAX_TESTNAME_LEN - 1] = '\0'; |
61 | f19410ca | Michael Walle | } |
62 | f19410ca | Michael Walle | |
63 | a8170e5e | Avi Kivity | static void sys_write(void *opaque, hwaddr addr, |
64 | 0aa27efa | Benoît Canet | uint64_t value, unsigned size)
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65 | f19410ca | Michael Walle | { |
66 | f19410ca | Michael Walle | LM32SysState *s = opaque; |
67 | f19410ca | Michael Walle | char *testname;
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68 | f19410ca | Michael Walle | |
69 | f19410ca | Michael Walle | trace_lm32_sys_memory_write(addr, value); |
70 | f19410ca | Michael Walle | |
71 | f19410ca | Michael Walle | addr >>= 2;
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72 | f19410ca | Michael Walle | switch (addr) {
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73 | f19410ca | Michael Walle | case R_CTRL:
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74 | f19410ca | Michael Walle | qemu_system_shutdown_request(); |
75 | f19410ca | Michael Walle | break;
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76 | f19410ca | Michael Walle | case R_PASSFAIL:
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77 | f19410ca | Michael Walle | s->regs[addr] = value; |
78 | f19410ca | Michael Walle | testname = (char *)s->testname;
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79 | f19410ca | Michael Walle | qemu_log("TC %-16s %s\n", testname, (value) ? "FAILED" : "OK"); |
80 | f19410ca | Michael Walle | break;
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81 | f19410ca | Michael Walle | case R_TESTNAME:
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82 | f19410ca | Michael Walle | s->regs[addr] = value; |
83 | f19410ca | Michael Walle | copy_testname(s); |
84 | f19410ca | Michael Walle | break;
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85 | f19410ca | Michael Walle | |
86 | f19410ca | Michael Walle | default:
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87 | dd3d6775 | Markus Armbruster | error_report("lm32_sys: write access to unknown register 0x"
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88 | f19410ca | Michael Walle | TARGET_FMT_plx, addr << 2);
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89 | f19410ca | Michael Walle | break;
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90 | f19410ca | Michael Walle | } |
91 | f19410ca | Michael Walle | } |
92 | f19410ca | Michael Walle | |
93 | a8170e5e | Avi Kivity | static bool sys_ops_accepts(void *opaque, hwaddr addr, |
94 | 0aa27efa | Benoît Canet | unsigned size, bool is_write) |
95 | 0aa27efa | Benoît Canet | { |
96 | 0aa27efa | Benoît Canet | return is_write && size == 4; |
97 | 0aa27efa | Benoît Canet | } |
98 | f19410ca | Michael Walle | |
99 | 0aa27efa | Benoît Canet | static const MemoryRegionOps sys_ops = { |
100 | 0aa27efa | Benoît Canet | .write = sys_write, |
101 | 0aa27efa | Benoît Canet | .valid.accepts = sys_ops_accepts, |
102 | 0aa27efa | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
103 | f19410ca | Michael Walle | }; |
104 | f19410ca | Michael Walle | |
105 | f19410ca | Michael Walle | static void sys_reset(DeviceState *d) |
106 | f19410ca | Michael Walle | { |
107 | f19410ca | Michael Walle | LM32SysState *s = container_of(d, LM32SysState, busdev.qdev); |
108 | f19410ca | Michael Walle | int i;
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109 | f19410ca | Michael Walle | |
110 | f19410ca | Michael Walle | for (i = 0; i < R_MAX; i++) { |
111 | f19410ca | Michael Walle | s->regs[i] = 0;
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112 | f19410ca | Michael Walle | } |
113 | f19410ca | Michael Walle | memset(s->testname, 0, MAX_TESTNAME_LEN);
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114 | f19410ca | Michael Walle | } |
115 | f19410ca | Michael Walle | |
116 | f19410ca | Michael Walle | static int lm32_sys_init(SysBusDevice *dev) |
117 | f19410ca | Michael Walle | { |
118 | f19410ca | Michael Walle | LM32SysState *s = FROM_SYSBUS(typeof(*s), dev); |
119 | f19410ca | Michael Walle | |
120 | 0aa27efa | Benoît Canet | memory_region_init_io(&s->iomem, &sys_ops , s, "sys", R_MAX * 4); |
121 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->iomem); |
122 | f19410ca | Michael Walle | |
123 | f19410ca | Michael Walle | /* Note: This device is not created in the board initialization,
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124 | f19410ca | Michael Walle | * instead it has to be added with the -device parameter. Therefore,
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125 | f19410ca | Michael Walle | * the device maps itself. */
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126 | f19410ca | Michael Walle | sysbus_mmio_map(dev, 0, s->base);
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127 | f19410ca | Michael Walle | |
128 | f19410ca | Michael Walle | return 0; |
129 | f19410ca | Michael Walle | } |
130 | f19410ca | Michael Walle | |
131 | f19410ca | Michael Walle | static const VMStateDescription vmstate_lm32_sys = { |
132 | f19410ca | Michael Walle | .name = "lm32-sys",
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133 | f19410ca | Michael Walle | .version_id = 1,
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134 | f19410ca | Michael Walle | .minimum_version_id = 1,
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135 | f19410ca | Michael Walle | .minimum_version_id_old = 1,
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136 | f19410ca | Michael Walle | .fields = (VMStateField[]) { |
137 | f19410ca | Michael Walle | VMSTATE_UINT32_ARRAY(regs, LM32SysState, R_MAX), |
138 | f19410ca | Michael Walle | VMSTATE_BUFFER(testname, LM32SysState), |
139 | f19410ca | Michael Walle | VMSTATE_END_OF_LIST() |
140 | f19410ca | Michael Walle | } |
141 | f19410ca | Michael Walle | }; |
142 | f19410ca | Michael Walle | |
143 | 999e12bb | Anthony Liguori | static Property lm32_sys_properties[] = {
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144 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT32("base", LM32SysState, base, 0xffff0000), |
145 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
146 | 999e12bb | Anthony Liguori | }; |
147 | 999e12bb | Anthony Liguori | |
148 | 999e12bb | Anthony Liguori | static void lm32_sys_class_init(ObjectClass *klass, void *data) |
149 | 999e12bb | Anthony Liguori | { |
150 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
151 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
152 | 999e12bb | Anthony Liguori | |
153 | 999e12bb | Anthony Liguori | k->init = lm32_sys_init; |
154 | 39bffca2 | Anthony Liguori | dc->reset = sys_reset; |
155 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_lm32_sys; |
156 | 39bffca2 | Anthony Liguori | dc->props = lm32_sys_properties; |
157 | 999e12bb | Anthony Liguori | } |
158 | 999e12bb | Anthony Liguori | |
159 | 8c43a6f0 | Andreas Färber | static const TypeInfo lm32_sys_info = { |
160 | 39bffca2 | Anthony Liguori | .name = "lm32-sys",
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161 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
162 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(LM32SysState),
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163 | 39bffca2 | Anthony Liguori | .class_init = lm32_sys_class_init, |
164 | f19410ca | Michael Walle | }; |
165 | f19410ca | Michael Walle | |
166 | 83f7d43a | Andreas Färber | static void lm32_sys_register_types(void) |
167 | f19410ca | Michael Walle | { |
168 | 39bffca2 | Anthony Liguori | type_register_static(&lm32_sys_info); |
169 | f19410ca | Michael Walle | } |
170 | f19410ca | Michael Walle | |
171 | 83f7d43a | Andreas Färber | type_init(lm32_sys_register_types) |