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Makefile.objs 206 Bytes
omap_spi.c 10.3 kB
pl022.c 8.5 kB
ssi.c 4.1 kB
xilinx_spi.c 9.5 kB
xilinx_spips.c 23.3 kB

Latest revisions

# Date Author Comment
fef7fbc9 06/07/2013 03:55 pm Andreas Färber

qdev: Drop FROM_QBUS() macro

Use QOM cast macros I2C_BUS(), SSI_BUS(), PCI_BUS() instead.

Signed-off-by: Andreas Färber <>

a66418f6 06/03/2013 07:17 pm Peter Crosthwaite

xilinx_spips: lqspi: Push more data to tx-fifo

Do 16 words per fifo flush. Increases performance and decreases
debug verbosity. This data depth has no real hardware analogue,
so just go with something that has reasonable performance.

Signed-off-by: Peter Crosthwaite <>...

b0b7ae62 06/03/2013 07:17 pm Peter Crosthwaite

xilinx_spips: lqspi: Fix byte/misaligned access

The LQSPI bus attachment supports byte/halfword and misaligned
accesses. Fixed. Refactored the LQSPI cache to be byte-wise
instead of word wise accordingly.

Signed-off-by: Peter Crosthwaite <>...

15408b42 06/03/2013 07:17 pm Peter Crosthwaite

xilinx_spips: lqspi: Dont touch config register

The LQSPI mode is supposed to work via the automatic CS mode feature
rather than manipulate CS lines itself. Now that auto CS is implemented
remove LQSPIs CS mode override logic. There is still a need to
manipulate the U_PAGE bit in LQSPI config register to implement...

2133a5f6 06/03/2013 07:17 pm Peter Crosthwaite

xilinx_spips: Fix CTRL register RW bits

The CTRL register was RAZ/WI on some of the RW bits. Even though the
function behind these bits is invalid in QEMU, they should still be
guest accessible. Fix.

Signed-off-by: Peter Crosthwaite <>...

9151da25 06/03/2013 07:17 pm Peter Crosthwaite

xilinx_spips: Fix striping behaviour

The QSPI controller was using byte-wide stripes when striping across
the two flashes in dual parallel mode. The real hardware however uses
individual bit striping. QEMU misbehaves in the (corner) case where
data is written/read in dual-parallel mode and read/written back in...

c37fc509 06/03/2013 07:17 pm Peter Crosthwaite

xilinx_spips: Debug msgs for Snoop state

This is worth keeping track of when debugging the device model.

Signed-off-by: Peter Crosthwaite <>
Reviewed-by: Peter Maydell <>
Reviewed-by: Edgar E. Iglesias <>...

4a5b6fa8 06/03/2013 07:17 pm Peter Crosthwaite

xilinx_spips: Multiple debug verbosity levels

The debug printfs on every SPI operation is extremely verbose. Add
a second level of debug for this.

Signed-off-by: Peter Crosthwaite <>
Reviewed-by: Peter Maydell <>...

e100f3be 06/03/2013 07:17 pm Peter Crosthwaite

xilinx_spips: Add automatic start support

SPI has a mode where it automatically starts based on tx fifo
occupancy. Implemented.

Signed-off-by: Peter Crosthwaite <>
Reviewed-by: Peter Maydell <>
Reviewed-by: Edgar E. Iglesias <>...

c4f08ffe 06/03/2013 07:17 pm Peter Crosthwaite

xilinx_spips: Implement automatic CS

Implement the automatic CS control feature. If the MANUAL_CS bit is
cleared then the chip select stay de-asserted as long as the tx FIFO
is empty.

Signed-off-by: Peter Crosthwaite <>
Reviewed-by: Peter Maydell <>...

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