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/*
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* Copyright (C) 2006 InnoTek Systemberatung GmbH
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*
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* This file is part of VirtualBox Open Source Edition (OSE), as
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* available from http://www.virtualbox.org. This file is free software;
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* you can redistribute it and/or modify it under the terms of the GNU
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* General Public License as published by the Free Software Foundation,
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* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
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* distribution. VirtualBox OSE is distributed in the hope that it will
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* be useful, but WITHOUT ANY WARRANTY of any kind.
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*
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* If you received this file as part of a commercial VirtualBox
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* distribution, then only the terms of your commercial VirtualBox
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* license agreement apply instead of the previous paragraph.
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*/
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#include "hw.h" |
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#include "audiodev.h" |
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#include "audio/audio.h" |
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#include "pci.h" |
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enum {
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AC97_Reset = 0x00,
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AC97_Master_Volume_Mute = 0x02,
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AC97_Headphone_Volume_Mute = 0x04,
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AC97_Master_Volume_Mono_Mute = 0x06,
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AC97_Master_Tone_RL = 0x08,
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AC97_PC_BEEP_Volume_Mute = 0x0A,
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AC97_Phone_Volume_Mute = 0x0C,
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AC97_Mic_Volume_Mute = 0x0E,
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AC97_Line_In_Volume_Mute = 0x10,
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AC97_CD_Volume_Mute = 0x12,
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AC97_Video_Volume_Mute = 0x14,
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AC97_Aux_Volume_Mute = 0x16,
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AC97_PCM_Out_Volume_Mute = 0x18,
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AC97_Record_Select = 0x1A,
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AC97_Record_Gain_Mute = 0x1C,
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AC97_Record_Gain_Mic_Mute = 0x1E,
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AC97_General_Purpose = 0x20,
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AC97_3D_Control = 0x22,
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AC97_AC_97_RESERVED = 0x24,
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AC97_Powerdown_Ctrl_Stat = 0x26,
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AC97_Extended_Audio_ID = 0x28,
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AC97_Extended_Audio_Ctrl_Stat = 0x2A,
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AC97_PCM_Front_DAC_Rate = 0x2C,
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AC97_PCM_Surround_DAC_Rate = 0x2E,
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AC97_PCM_LFE_DAC_Rate = 0x30,
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AC97_PCM_LR_ADC_Rate = 0x32,
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AC97_MIC_ADC_Rate = 0x34,
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AC97_6Ch_Vol_C_LFE_Mute = 0x36,
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AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
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AC97_Vendor_Reserved = 0x58,
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AC97_Vendor_ID1 = 0x7c,
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AC97_Vendor_ID2 = 0x7e
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}; |
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#define SOFT_VOLUME
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#define SR_FIFOE 16 /* rwc */ |
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#define SR_BCIS 8 /* rwc */ |
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#define SR_LVBCI 4 /* rwc */ |
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#define SR_CELV 2 /* ro */ |
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#define SR_DCH 1 /* ro */ |
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#define SR_VALID_MASK ((1 << 5) - 1) |
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#define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
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#define SR_RO_MASK (SR_DCH | SR_CELV)
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#define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
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|
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#define CR_IOCE 16 /* rw */ |
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#define CR_FEIE 8 /* rw */ |
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#define CR_LVBIE 4 /* rw */ |
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#define CR_RR 2 /* rw */ |
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#define CR_RPBM 1 /* rw */ |
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#define CR_VALID_MASK ((1 << 5) - 1) |
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#define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
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#define GC_WR 4 /* rw */ |
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#define GC_CR 2 /* rw */ |
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#define GC_VALID_MASK ((1 << 6) - 1) |
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|
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#define GS_MD3 (1<<17) /* rw */ |
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#define GS_AD3 (1<<16) /* rw */ |
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#define GS_RCS (1<<15) /* rwc */ |
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#define GS_B3S12 (1<<14) /* ro */ |
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#define GS_B2S12 (1<<13) /* ro */ |
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#define GS_B1S12 (1<<12) /* ro */ |
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#define GS_S1R1 (1<<11) /* rwc */ |
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#define GS_S0R1 (1<<10) /* rwc */ |
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#define GS_S1CR (1<<9) /* ro */ |
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#define GS_S0CR (1<<8) /* ro */ |
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#define GS_MINT (1<<7) /* ro */ |
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#define GS_POINT (1<<6) /* ro */ |
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#define GS_PIINT (1<<5) /* ro */ |
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#define GS_RSRVD ((1<<4)|(1<<3)) |
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#define GS_MOINT (1<<2) /* ro */ |
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#define GS_MIINT (1<<1) /* ro */ |
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#define GS_GSCI 1 /* rwc */ |
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#define GS_RO_MASK (GS_B3S12| \
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GS_B2S12| \ |
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GS_B1S12| \ |
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GS_S1CR| \ |
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GS_S0CR| \ |
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GS_MINT| \ |
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GS_POINT| \ |
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GS_PIINT| \ |
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GS_RSRVD| \ |
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GS_MOINT| \ |
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GS_MIINT) |
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#define GS_VALID_MASK ((1 << 18) - 1) |
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#define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)
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#define BD_IOC (1<<31) |
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#define BD_BUP (1<<30) |
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#define EACS_VRA 1 |
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#define EACS_VRM 8 |
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#define VOL_MASK 0x1f |
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#define MUTE_SHIFT 15 |
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#define REC_MASK 7 |
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enum {
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REC_MIC = 0,
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REC_CD, |
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REC_VIDEO, |
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REC_AUX, |
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REC_LINE_IN, |
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REC_STEREO_MIX, |
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REC_MONO_MIX, |
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REC_PHONE |
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}; |
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typedef struct BD { |
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uint32_t addr; |
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uint32_t ctl_len; |
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} BD; |
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typedef struct AC97BusMasterRegs { |
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uint32_t bdbar; /* rw 0 */
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uint8_t civ; /* ro 0 */
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uint8_t lvi; /* rw 0 */
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uint16_t sr; /* rw 1 */
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uint16_t picb; /* ro 0 */
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uint8_t piv; /* ro 0 */
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uint8_t cr; /* rw 0 */
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unsigned int bd_valid; |
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BD bd; |
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} AC97BusMasterRegs; |
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typedef struct AC97LinkState { |
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PCIDevice dev; |
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QEMUSoundCard card; |
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uint32_t glob_cnt; |
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uint32_t glob_sta; |
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uint32_t cas; |
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uint32_t last_samp; |
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AC97BusMasterRegs bm_regs[3];
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uint8_t mixer_data[256];
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SWVoiceIn *voice_pi; |
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SWVoiceOut *voice_po; |
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SWVoiceIn *voice_mc; |
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int invalid_freq[3]; |
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uint8_t silence[128];
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uint32_t base[2];
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int bup_flag;
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} AC97LinkState; |
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enum {
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BUP_SET = 1,
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BUP_LAST = 2
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}; |
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#ifdef DEBUG_AC97
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#define dolog(...) AUD_log ("ac97", __VA_ARGS__) |
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#else
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#define dolog(...)
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#endif
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#define MKREGS(prefix, start) \
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enum { \
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prefix ## _BDBAR = start, \ |
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prefix ## _CIV = start + 4, \ |
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prefix ## _LVI = start + 5, \ |
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prefix ## _SR = start + 6, \ |
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prefix ## _PICB = start + 8, \ |
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prefix ## _PIV = start + 10, \ |
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prefix ## _CR = start + 11 \ |
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} |
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enum {
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PI_INDEX = 0,
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PO_INDEX, |
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MC_INDEX, |
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LAST_INDEX |
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}; |
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MKREGS (PI, PI_INDEX * 16);
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MKREGS (PO, PO_INDEX * 16);
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MKREGS (MC, MC_INDEX * 16);
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enum {
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GLOB_CNT = 0x2c,
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GLOB_STA = 0x30,
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CAS = 0x34
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}; |
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#define GET_BM(index) (((index) >> 4) & 3) |
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static void po_callback (void *opaque, int free); |
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static void pi_callback (void *opaque, int avail); |
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static void mc_callback (void *opaque, int avail); |
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static void warm_reset (AC97LinkState *s) |
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{
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(void) s;
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} |
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static void cold_reset (AC97LinkState * s) |
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{
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(void) s;
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} |
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static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r) |
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{
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uint8_t b[8];
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cpu_physical_memory_read (r->bdbar + r->civ * 8, b, 8); |
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r->bd_valid = 1;
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r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3; |
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r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]);
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r->picb = r->bd.ctl_len & 0xffff;
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dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
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r->civ, r->bd.addr, r->bd.ctl_len >> 16,
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r->bd.ctl_len & 0xffff,
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(r->bd.ctl_len & 0xffff) << 1); |
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} |
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static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr) |
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{
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int event = 0; |
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int level = 0; |
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uint32_t new_mask = new_sr & SR_INT_MASK; |
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uint32_t old_mask = r->sr & SR_INT_MASK; |
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uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT};
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if (new_mask ^ old_mask) {
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/** @todo is IRQ deasserted when only one of status bits is cleared? */
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if (!new_mask) {
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event = 1;
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level = 0;
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} |
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else {
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if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) {
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event = 1;
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level = 1;
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} |
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if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) {
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event = 1;
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level = 1;
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} |
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} |
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} |
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r->sr = new_sr; |
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dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n",
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r->sr & SR_BCIS, r->sr & SR_LVBCI, |
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r->sr, |
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event, level); |
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if (!event)
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return;
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|
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if (level) {
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s->glob_sta |= masks[r - s->bm_regs]; |
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dolog ("set irq level=1\n");
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qemu_set_irq (s->dev.irq[0], 1); |
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} |
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else {
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s->glob_sta &= ~masks[r - s->bm_regs]; |
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dolog ("set irq level=0\n");
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qemu_set_irq (s->dev.irq[0], 0); |
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} |
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} |
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static void voice_set_active (AC97LinkState *s, int bm_index, int on) |
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{
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switch (bm_index) {
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case PI_INDEX:
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AUD_set_active_in (s->voice_pi, on); |
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break;
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|
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case PO_INDEX:
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AUD_set_active_out (s->voice_po, on); |
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break;
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|
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case MC_INDEX:
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AUD_set_active_in (s->voice_mc, on); |
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break;
|
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|
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default:
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AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index); |
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break;
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} |
| 304 |
} |
| 305 |
|
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static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r) |
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{
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dolog ("reset_bm_regs\n");
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r->bdbar = 0;
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r->civ = 0;
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r->lvi = 0;
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/** todo do we need to do that? */
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update_sr (s, r, SR_DCH); |
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r->picb = 0;
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r->piv = 0;
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r->cr = r->cr & CR_DONT_CLEAR_MASK; |
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r->bd_valid = 0;
|
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|
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voice_set_active (s, r - s->bm_regs, 0);
|
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memset (s->silence, 0, sizeof (s->silence)); |
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} |
| 322 |
|
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static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v) |
| 324 |
{
|
| 325 |
if (i + 2 > sizeof (s->mixer_data)) { |
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dolog ("mixer_store: index %d out of bounds %zd\n",
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| 327 |
i, sizeof (s->mixer_data));
|
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return;
|
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} |
| 330 |
|
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s->mixer_data[i + 0] = v & 0xff; |
| 332 |
s->mixer_data[i + 1] = v >> 8; |
| 333 |
} |
| 334 |
|
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static uint16_t mixer_load (AC97LinkState *s, uint32_t i)
|
| 336 |
{
|
| 337 |
uint16_t val = 0xffff;
|
| 338 |
|
| 339 |
if (i + 2 > sizeof (s->mixer_data)) { |
| 340 |
dolog ("mixer_store: index %d out of bounds %zd\n",
|
| 341 |
i, sizeof (s->mixer_data));
|
| 342 |
} |
| 343 |
else {
|
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val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8); |
| 345 |
} |
| 346 |
|
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return val;
|
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} |
| 349 |
|
| 350 |
static void open_voice (AC97LinkState *s, int index, int freq) |
| 351 |
{
|
| 352 |
struct audsettings as;
|
| 353 |
|
| 354 |
as.freq = freq; |
| 355 |
as.nchannels = 2;
|
| 356 |
as.fmt = AUD_FMT_S16; |
| 357 |
as.endianness = 0;
|
| 358 |
|
| 359 |
if (freq > 0) { |
| 360 |
s->invalid_freq[index] = 0;
|
| 361 |
switch (index) {
|
| 362 |
case PI_INDEX:
|
| 363 |
s->voice_pi = AUD_open_in ( |
| 364 |
&s->card, |
| 365 |
s->voice_pi, |
| 366 |
"ac97.pi",
|
| 367 |
s, |
| 368 |
pi_callback, |
| 369 |
&as |
| 370 |
); |
| 371 |
break;
|
| 372 |
|
| 373 |
case PO_INDEX:
|
| 374 |
s->voice_po = AUD_open_out ( |
| 375 |
&s->card, |
| 376 |
s->voice_po, |
| 377 |
"ac97.po",
|
| 378 |
s, |
| 379 |
po_callback, |
| 380 |
&as |
| 381 |
); |
| 382 |
break;
|
| 383 |
|
| 384 |
case MC_INDEX:
|
| 385 |
s->voice_mc = AUD_open_in ( |
| 386 |
&s->card, |
| 387 |
s->voice_mc, |
| 388 |
"ac97.mc",
|
| 389 |
s, |
| 390 |
mc_callback, |
| 391 |
&as |
| 392 |
); |
| 393 |
break;
|
| 394 |
} |
| 395 |
} |
| 396 |
else {
|
| 397 |
s->invalid_freq[index] = freq; |
| 398 |
switch (index) {
|
| 399 |
case PI_INDEX:
|
| 400 |
AUD_close_in (&s->card, s->voice_pi); |
| 401 |
s->voice_pi = NULL;
|
| 402 |
break;
|
| 403 |
|
| 404 |
case PO_INDEX:
|
| 405 |
AUD_close_out (&s->card, s->voice_po); |
| 406 |
s->voice_po = NULL;
|
| 407 |
break;
|
| 408 |
|
| 409 |
case MC_INDEX:
|
| 410 |
AUD_close_in (&s->card, s->voice_mc); |
| 411 |
s->voice_mc = NULL;
|
| 412 |
break;
|
| 413 |
} |
| 414 |
} |
| 415 |
} |
| 416 |
|
| 417 |
static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX]) |
| 418 |
{
|
| 419 |
uint16_t freq; |
| 420 |
|
| 421 |
freq = mixer_load (s, AC97_PCM_LR_ADC_Rate); |
| 422 |
open_voice (s, PI_INDEX, freq); |
| 423 |
AUD_set_active_in (s->voice_pi, active[PI_INDEX]); |
| 424 |
|
| 425 |
freq = mixer_load (s, AC97_PCM_Front_DAC_Rate); |
| 426 |
open_voice (s, PO_INDEX, freq); |
| 427 |
AUD_set_active_out (s->voice_po, active[PO_INDEX]); |
| 428 |
|
| 429 |
freq = mixer_load (s, AC97_MIC_ADC_Rate); |
| 430 |
open_voice (s, MC_INDEX, freq); |
| 431 |
AUD_set_active_in (s->voice_mc, active[MC_INDEX]); |
| 432 |
} |
| 433 |
|
| 434 |
#ifdef USE_MIXER
|
| 435 |
static void set_volume (AC97LinkState *s, int index, |
| 436 |
audmixerctl_t mt, uint32_t val) |
| 437 |
{
|
| 438 |
int mute = (val >> MUTE_SHIFT) & 1; |
| 439 |
uint8_t rvol = VOL_MASK - (val & VOL_MASK); |
| 440 |
uint8_t lvol = VOL_MASK - ((val >> 8) & VOL_MASK);
|
| 441 |
rvol = 255 * rvol / VOL_MASK;
|
| 442 |
lvol = 255 * lvol / VOL_MASK;
|
| 443 |
|
| 444 |
#ifdef SOFT_VOLUME
|
| 445 |
if (index == AC97_Master_Volume_Mute) {
|
| 446 |
AUD_set_volume_out (s->voice_po, mute, lvol, rvol); |
| 447 |
} |
| 448 |
else {
|
| 449 |
AUD_set_volume (mt, &mute, &lvol, &rvol); |
| 450 |
} |
| 451 |
#else
|
| 452 |
AUD_set_volume (mt, &mute, &lvol, &rvol); |
| 453 |
#endif
|
| 454 |
|
| 455 |
rvol = VOL_MASK - ((VOL_MASK * rvol) / 255);
|
| 456 |
lvol = VOL_MASK - ((VOL_MASK * lvol) / 255);
|
| 457 |
mixer_store (s, index, val); |
| 458 |
} |
| 459 |
|
| 460 |
static audrecsource_t ac97_to_aud_record_source (uint8_t i)
|
| 461 |
{
|
| 462 |
switch (i) {
|
| 463 |
case REC_MIC:
|
| 464 |
return AUD_REC_MIC;
|
| 465 |
|
| 466 |
case REC_CD:
|
| 467 |
return AUD_REC_CD;
|
| 468 |
|
| 469 |
case REC_VIDEO:
|
| 470 |
return AUD_REC_VIDEO;
|
| 471 |
|
| 472 |
case REC_AUX:
|
| 473 |
return AUD_REC_AUX;
|
| 474 |
|
| 475 |
case REC_LINE_IN:
|
| 476 |
return AUD_REC_LINE_IN;
|
| 477 |
|
| 478 |
case REC_PHONE:
|
| 479 |
return AUD_REC_PHONE;
|
| 480 |
|
| 481 |
default:
|
| 482 |
dolog ("Unknown record source %d, using MIC\n", i);
|
| 483 |
return AUD_REC_MIC;
|
| 484 |
} |
| 485 |
} |
| 486 |
|
| 487 |
static uint8_t aud_to_ac97_record_source (audrecsource_t rs)
|
| 488 |
{
|
| 489 |
switch (rs) {
|
| 490 |
case AUD_REC_MIC:
|
| 491 |
return REC_MIC;
|
| 492 |
|
| 493 |
case AUD_REC_CD:
|
| 494 |
return REC_CD;
|
| 495 |
|
| 496 |
case AUD_REC_VIDEO:
|
| 497 |
return REC_VIDEO;
|
| 498 |
|
| 499 |
case AUD_REC_AUX:
|
| 500 |
return REC_AUX;
|
| 501 |
|
| 502 |
case AUD_REC_LINE_IN:
|
| 503 |
return REC_LINE_IN;
|
| 504 |
|
| 505 |
case AUD_REC_PHONE:
|
| 506 |
return REC_PHONE;
|
| 507 |
|
| 508 |
default:
|
| 509 |
dolog ("Unknown audio recording source %d using MIC\n", rs);
|
| 510 |
return REC_MIC;
|
| 511 |
} |
| 512 |
} |
| 513 |
|
| 514 |
static void record_select (AC97LinkState *s, uint32_t val) |
| 515 |
{
|
| 516 |
uint8_t rs = val & REC_MASK; |
| 517 |
uint8_t ls = (val >> 8) & REC_MASK;
|
| 518 |
audrecsource_t ars = ac97_to_aud_record_source (rs); |
| 519 |
audrecsource_t als = ac97_to_aud_record_source (ls); |
| 520 |
AUD_set_record_source (&als, &ars); |
| 521 |
rs = aud_to_ac97_record_source (ars); |
| 522 |
ls = aud_to_ac97_record_source (als); |
| 523 |
mixer_store (s, AC97_Record_Select, rs | (ls << 8));
|
| 524 |
} |
| 525 |
#endif
|
| 526 |
|
| 527 |
static void mixer_reset (AC97LinkState *s) |
| 528 |
{
|
| 529 |
uint8_t active[LAST_INDEX]; |
| 530 |
|
| 531 |
dolog ("mixer_reset\n");
|
| 532 |
memset (s->mixer_data, 0, sizeof (s->mixer_data)); |
| 533 |
memset (active, 0, sizeof (active)); |
| 534 |
mixer_store (s, AC97_Reset , 0x0000); /* 6940 */ |
| 535 |
mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x8000);
|
| 536 |
mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000);
|
| 537 |
|
| 538 |
mixer_store (s, AC97_Phone_Volume_Mute , 0x8008);
|
| 539 |
mixer_store (s, AC97_Mic_Volume_Mute , 0x8008);
|
| 540 |
mixer_store (s, AC97_CD_Volume_Mute , 0x8808);
|
| 541 |
mixer_store (s, AC97_Aux_Volume_Mute , 0x8808);
|
| 542 |
mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x8000);
|
| 543 |
mixer_store (s, AC97_General_Purpose , 0x0000);
|
| 544 |
mixer_store (s, AC97_3D_Control , 0x0000);
|
| 545 |
mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f);
|
| 546 |
|
| 547 |
/*
|
| 548 |
* Sigmatel 9700 (STAC9700)
|
| 549 |
*/
|
| 550 |
mixer_store (s, AC97_Vendor_ID1 , 0x8384);
|
| 551 |
mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */ |
| 552 |
|
| 553 |
mixer_store (s, AC97_Extended_Audio_ID , 0x0809);
|
| 554 |
mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
|
| 555 |
mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80);
|
| 556 |
mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80);
|
| 557 |
mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80);
|
| 558 |
mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80);
|
| 559 |
mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80);
|
| 560 |
|
| 561 |
#ifdef USE_MIXER
|
| 562 |
record_select (s, 0);
|
| 563 |
set_volume (s, AC97_Master_Volume_Mute, AUD_MIXER_VOLUME , 0x8000);
|
| 564 |
set_volume (s, AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM , 0x8808);
|
| 565 |
set_volume (s, AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN, 0x8808);
|
| 566 |
#endif
|
| 567 |
reset_voices (s, active); |
| 568 |
} |
| 569 |
|
| 570 |
/**
|
| 571 |
* Native audio mixer
|
| 572 |
* I/O Reads
|
| 573 |
*/
|
| 574 |
static uint32_t nam_readb (void *opaque, uint32_t addr) |
| 575 |
{
|
| 576 |
AC97LinkState *s = opaque; |
| 577 |
dolog ("U nam readb %#x\n", addr);
|
| 578 |
s->cas = 0;
|
| 579 |
return ~0U; |
| 580 |
} |
| 581 |
|
| 582 |
static uint32_t nam_readw (void *opaque, uint32_t addr) |
| 583 |
{
|
| 584 |
AC97LinkState *s = opaque; |
| 585 |
uint32_t val = ~0U;
|
| 586 |
uint32_t index = addr - s->base[0];
|
| 587 |
s->cas = 0;
|
| 588 |
val = mixer_load (s, index); |
| 589 |
return val;
|
| 590 |
} |
| 591 |
|
| 592 |
static uint32_t nam_readl (void *opaque, uint32_t addr) |
| 593 |
{
|
| 594 |
AC97LinkState *s = opaque; |
| 595 |
dolog ("U nam readl %#x\n", addr);
|
| 596 |
s->cas = 0;
|
| 597 |
return ~0U; |
| 598 |
} |
| 599 |
|
| 600 |
/**
|
| 601 |
* Native audio mixer
|
| 602 |
* I/O Writes
|
| 603 |
*/
|
| 604 |
static void nam_writeb (void *opaque, uint32_t addr, uint32_t val) |
| 605 |
{
|
| 606 |
AC97LinkState *s = opaque; |
| 607 |
dolog ("U nam writeb %#x <- %#x\n", addr, val);
|
| 608 |
s->cas = 0;
|
| 609 |
} |
| 610 |
|
| 611 |
static void nam_writew (void *opaque, uint32_t addr, uint32_t val) |
| 612 |
{
|
| 613 |
AC97LinkState *s = opaque; |
| 614 |
uint32_t index = addr - s->base[0];
|
| 615 |
s->cas = 0;
|
| 616 |
switch (index) {
|
| 617 |
case AC97_Reset:
|
| 618 |
mixer_reset (s); |
| 619 |
break;
|
| 620 |
case AC97_Powerdown_Ctrl_Stat:
|
| 621 |
val &= ~0xf;
|
| 622 |
val |= mixer_load (s, index) & 0xf;
|
| 623 |
mixer_store (s, index, val); |
| 624 |
break;
|
| 625 |
#ifdef USE_MIXER
|
| 626 |
case AC97_Master_Volume_Mute:
|
| 627 |
set_volume (s, index, AUD_MIXER_VOLUME, val); |
| 628 |
break;
|
| 629 |
case AC97_PCM_Out_Volume_Mute:
|
| 630 |
set_volume (s, index, AUD_MIXER_PCM, val); |
| 631 |
break;
|
| 632 |
case AC97_Line_In_Volume_Mute:
|
| 633 |
set_volume (s, index, AUD_MIXER_LINE_IN, val); |
| 634 |
break;
|
| 635 |
case AC97_Record_Select:
|
| 636 |
record_select (s, val); |
| 637 |
break;
|
| 638 |
#endif
|
| 639 |
case AC97_Vendor_ID1:
|
| 640 |
case AC97_Vendor_ID2:
|
| 641 |
dolog ("Attempt to write vendor ID to %#x\n", val);
|
| 642 |
break;
|
| 643 |
case AC97_Extended_Audio_ID:
|
| 644 |
dolog ("Attempt to write extended audio ID to %#x\n", val);
|
| 645 |
break;
|
| 646 |
case AC97_Extended_Audio_Ctrl_Stat:
|
| 647 |
if (!(val & EACS_VRA)) {
|
| 648 |
mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80);
|
| 649 |
mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80);
|
| 650 |
open_voice (s, PI_INDEX, 48000);
|
| 651 |
open_voice (s, PO_INDEX, 48000);
|
| 652 |
} |
| 653 |
if (!(val & EACS_VRM)) {
|
| 654 |
mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80);
|
| 655 |
open_voice (s, MC_INDEX, 48000);
|
| 656 |
} |
| 657 |
dolog ("Setting extended audio control to %#x\n", val);
|
| 658 |
mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val); |
| 659 |
break;
|
| 660 |
case AC97_PCM_Front_DAC_Rate:
|
| 661 |
if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
|
| 662 |
mixer_store (s, index, val); |
| 663 |
dolog ("Set front DAC rate to %d\n", val);
|
| 664 |
open_voice (s, PO_INDEX, val); |
| 665 |
} |
| 666 |
else {
|
| 667 |
dolog ("Attempt to set front DAC rate to %d, "
|
| 668 |
"but VRA is not set\n",
|
| 669 |
val); |
| 670 |
} |
| 671 |
break;
|
| 672 |
case AC97_MIC_ADC_Rate:
|
| 673 |
if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) {
|
| 674 |
mixer_store (s, index, val); |
| 675 |
dolog ("Set MIC ADC rate to %d\n", val);
|
| 676 |
open_voice (s, MC_INDEX, val); |
| 677 |
} |
| 678 |
else {
|
| 679 |
dolog ("Attempt to set MIC ADC rate to %d, "
|
| 680 |
"but VRM is not set\n",
|
| 681 |
val); |
| 682 |
} |
| 683 |
break;
|
| 684 |
case AC97_PCM_LR_ADC_Rate:
|
| 685 |
if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
|
| 686 |
mixer_store (s, index, val); |
| 687 |
dolog ("Set front LR ADC rate to %d\n", val);
|
| 688 |
open_voice (s, PI_INDEX, val); |
| 689 |
} |
| 690 |
else {
|
| 691 |
dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n",
|
| 692 |
val); |
| 693 |
} |
| 694 |
break;
|
| 695 |
default:
|
| 696 |
dolog ("U nam writew %#x <- %#x\n", addr, val);
|
| 697 |
mixer_store (s, index, val); |
| 698 |
break;
|
| 699 |
} |
| 700 |
} |
| 701 |
|
| 702 |
static void nam_writel (void *opaque, uint32_t addr, uint32_t val) |
| 703 |
{
|
| 704 |
AC97LinkState *s = opaque; |
| 705 |
dolog ("U nam writel %#x <- %#x\n", addr, val);
|
| 706 |
s->cas = 0;
|
| 707 |
} |
| 708 |
|
| 709 |
/**
|
| 710 |
* Native audio bus master
|
| 711 |
* I/O Reads
|
| 712 |
*/
|
| 713 |
static uint32_t nabm_readb (void *opaque, uint32_t addr) |
| 714 |
{
|
| 715 |
AC97LinkState *s = opaque; |
| 716 |
AC97BusMasterRegs *r = NULL;
|
| 717 |
uint32_t index = addr - s->base[1];
|
| 718 |
uint32_t val = ~0U;
|
| 719 |
|
| 720 |
switch (index) {
|
| 721 |
case CAS:
|
| 722 |
dolog ("CAS %d\n", s->cas);
|
| 723 |
val = s->cas; |
| 724 |
s->cas = 1;
|
| 725 |
break;
|
| 726 |
case PI_CIV:
|
| 727 |
case PO_CIV:
|
| 728 |
case MC_CIV:
|
| 729 |
r = &s->bm_regs[GET_BM (index)]; |
| 730 |
val = r->civ; |
| 731 |
dolog ("CIV[%d] -> %#x\n", GET_BM (index), val);
|
| 732 |
break;
|
| 733 |
case PI_LVI:
|
| 734 |
case PO_LVI:
|
| 735 |
case MC_LVI:
|
| 736 |
r = &s->bm_regs[GET_BM (index)]; |
| 737 |
val = r->lvi; |
| 738 |
dolog ("LVI[%d] -> %#x\n", GET_BM (index), val);
|
| 739 |
break;
|
| 740 |
case PI_PIV:
|
| 741 |
case PO_PIV:
|
| 742 |
case MC_PIV:
|
| 743 |
r = &s->bm_regs[GET_BM (index)]; |
| 744 |
val = r->piv; |
| 745 |
dolog ("PIV[%d] -> %#x\n", GET_BM (index), val);
|
| 746 |
break;
|
| 747 |
case PI_CR:
|
| 748 |
case PO_CR:
|
| 749 |
case MC_CR:
|
| 750 |
r = &s->bm_regs[GET_BM (index)]; |
| 751 |
val = r->cr; |
| 752 |
dolog ("CR[%d] -> %#x\n", GET_BM (index), val);
|
| 753 |
break;
|
| 754 |
case PI_SR:
|
| 755 |
case PO_SR:
|
| 756 |
case MC_SR:
|
| 757 |
r = &s->bm_regs[GET_BM (index)]; |
| 758 |
val = r->sr & 0xff;
|
| 759 |
dolog ("SRb[%d] -> %#x\n", GET_BM (index), val);
|
| 760 |
break;
|
| 761 |
default:
|
| 762 |
dolog ("U nabm readb %#x -> %#x\n", addr, val);
|
| 763 |
break;
|
| 764 |
} |
| 765 |
return val;
|
| 766 |
} |
| 767 |
|
| 768 |
static uint32_t nabm_readw (void *opaque, uint32_t addr) |
| 769 |
{
|
| 770 |
AC97LinkState *s = opaque; |
| 771 |
AC97BusMasterRegs *r = NULL;
|
| 772 |
uint32_t index = addr - s->base[1];
|
| 773 |
uint32_t val = ~0U;
|
| 774 |
|
| 775 |
switch (index) {
|
| 776 |
case PI_SR:
|
| 777 |
case PO_SR:
|
| 778 |
case MC_SR:
|
| 779 |
r = &s->bm_regs[GET_BM (index)]; |
| 780 |
val = r->sr; |
| 781 |
dolog ("SR[%d] -> %#x\n", GET_BM (index), val);
|
| 782 |
break;
|
| 783 |
case PI_PICB:
|
| 784 |
case PO_PICB:
|
| 785 |
case MC_PICB:
|
| 786 |
r = &s->bm_regs[GET_BM (index)]; |
| 787 |
val = r->picb; |
| 788 |
dolog ("PICB[%d] -> %#x\n", GET_BM (index), val);
|
| 789 |
break;
|
| 790 |
default:
|
| 791 |
dolog ("U nabm readw %#x -> %#x\n", addr, val);
|
| 792 |
break;
|
| 793 |
} |
| 794 |
return val;
|
| 795 |
} |
| 796 |
|
| 797 |
static uint32_t nabm_readl (void *opaque, uint32_t addr) |
| 798 |
{
|
| 799 |
AC97LinkState *s = opaque; |
| 800 |
AC97BusMasterRegs *r = NULL;
|
| 801 |
uint32_t index = addr - s->base[1];
|
| 802 |
uint32_t val = ~0U;
|
| 803 |
|
| 804 |
switch (index) {
|
| 805 |
case PI_BDBAR:
|
| 806 |
case PO_BDBAR:
|
| 807 |
case MC_BDBAR:
|
| 808 |
r = &s->bm_regs[GET_BM (index)]; |
| 809 |
val = r->bdbar; |
| 810 |
dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val);
|
| 811 |
break;
|
| 812 |
case PI_CIV:
|
| 813 |
case PO_CIV:
|
| 814 |
case MC_CIV:
|
| 815 |
r = &s->bm_regs[GET_BM (index)]; |
| 816 |
val = r->civ | (r->lvi << 8) | (r->sr << 16); |
| 817 |
dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index),
|
| 818 |
r->civ, r->lvi, r->sr); |
| 819 |
break;
|
| 820 |
case PI_PICB:
|
| 821 |
case PO_PICB:
|
| 822 |
case MC_PICB:
|
| 823 |
r = &s->bm_regs[GET_BM (index)]; |
| 824 |
val = r->picb | (r->piv << 16) | (r->cr << 24); |
| 825 |
dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index),
|
| 826 |
val, r->picb, r->piv, r->cr); |
| 827 |
break;
|
| 828 |
case GLOB_CNT:
|
| 829 |
val = s->glob_cnt; |
| 830 |
dolog ("glob_cnt -> %#x\n", val);
|
| 831 |
break;
|
| 832 |
case GLOB_STA:
|
| 833 |
val = s->glob_sta | GS_S0CR; |
| 834 |
dolog ("glob_sta -> %#x\n", val);
|
| 835 |
break;
|
| 836 |
default:
|
| 837 |
dolog ("U nabm readl %#x -> %#x\n", addr, val);
|
| 838 |
break;
|
| 839 |
} |
| 840 |
return val;
|
| 841 |
} |
| 842 |
|
| 843 |
/**
|
| 844 |
* Native audio bus master
|
| 845 |
* I/O Writes
|
| 846 |
*/
|
| 847 |
static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val) |
| 848 |
{
|
| 849 |
AC97LinkState *s = opaque; |
| 850 |
AC97BusMasterRegs *r = NULL;
|
| 851 |
uint32_t index = addr - s->base[1];
|
| 852 |
switch (index) {
|
| 853 |
case PI_LVI:
|
| 854 |
case PO_LVI:
|
| 855 |
case MC_LVI:
|
| 856 |
r = &s->bm_regs[GET_BM (index)]; |
| 857 |
if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) {
|
| 858 |
r->sr &= ~(SR_DCH | SR_CELV); |
| 859 |
r->civ = r->piv; |
| 860 |
r->piv = (r->piv + 1) % 32; |
| 861 |
fetch_bd (s, r); |
| 862 |
} |
| 863 |
r->lvi = val % 32;
|
| 864 |
dolog ("LVI[%d] <- %#x\n", GET_BM (index), val);
|
| 865 |
break;
|
| 866 |
case PI_CR:
|
| 867 |
case PO_CR:
|
| 868 |
case MC_CR:
|
| 869 |
r = &s->bm_regs[GET_BM (index)]; |
| 870 |
if (val & CR_RR) {
|
| 871 |
reset_bm_regs (s, r); |
| 872 |
} |
| 873 |
else {
|
| 874 |
r->cr = val & CR_VALID_MASK; |
| 875 |
if (!(r->cr & CR_RPBM)) {
|
| 876 |
voice_set_active (s, r - s->bm_regs, 0);
|
| 877 |
r->sr |= SR_DCH; |
| 878 |
} |
| 879 |
else {
|
| 880 |
r->civ = r->piv; |
| 881 |
r->piv = (r->piv + 1) % 32; |
| 882 |
fetch_bd (s, r); |
| 883 |
r->sr &= ~SR_DCH; |
| 884 |
voice_set_active (s, r - s->bm_regs, 1);
|
| 885 |
} |
| 886 |
} |
| 887 |
dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr);
|
| 888 |
break;
|
| 889 |
case PI_SR:
|
| 890 |
case PO_SR:
|
| 891 |
case MC_SR:
|
| 892 |
r = &s->bm_regs[GET_BM (index)]; |
| 893 |
r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK); |
| 894 |
update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK)); |
| 895 |
dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
|
| 896 |
break;
|
| 897 |
default:
|
| 898 |
dolog ("U nabm writeb %#x <- %#x\n", addr, val);
|
| 899 |
break;
|
| 900 |
} |
| 901 |
} |
| 902 |
|
| 903 |
static void nabm_writew (void *opaque, uint32_t addr, uint32_t val) |
| 904 |
{
|
| 905 |
AC97LinkState *s = opaque; |
| 906 |
AC97BusMasterRegs *r = NULL;
|
| 907 |
uint32_t index = addr - s->base[1];
|
| 908 |
switch (index) {
|
| 909 |
case PI_SR:
|
| 910 |
case PO_SR:
|
| 911 |
case MC_SR:
|
| 912 |
r = &s->bm_regs[GET_BM (index)]; |
| 913 |
r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK); |
| 914 |
update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK)); |
| 915 |
dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
|
| 916 |
break;
|
| 917 |
default:
|
| 918 |
dolog ("U nabm writew %#x <- %#x\n", addr, val);
|
| 919 |
break;
|
| 920 |
} |
| 921 |
} |
| 922 |
|
| 923 |
static void nabm_writel (void *opaque, uint32_t addr, uint32_t val) |
| 924 |
{
|
| 925 |
AC97LinkState *s = opaque; |
| 926 |
AC97BusMasterRegs *r = NULL;
|
| 927 |
uint32_t index = addr - s->base[1];
|
| 928 |
switch (index) {
|
| 929 |
case PI_BDBAR:
|
| 930 |
case PO_BDBAR:
|
| 931 |
case MC_BDBAR:
|
| 932 |
r = &s->bm_regs[GET_BM (index)]; |
| 933 |
r->bdbar = val & ~3;
|
| 934 |
dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n",
|
| 935 |
GET_BM (index), val, r->bdbar); |
| 936 |
break;
|
| 937 |
case GLOB_CNT:
|
| 938 |
if (val & GC_WR)
|
| 939 |
warm_reset (s); |
| 940 |
if (val & GC_CR)
|
| 941 |
cold_reset (s); |
| 942 |
if (!(val & (GC_WR | GC_CR)))
|
| 943 |
s->glob_cnt = val & GC_VALID_MASK; |
| 944 |
dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt);
|
| 945 |
break;
|
| 946 |
case GLOB_STA:
|
| 947 |
s->glob_sta &= ~(val & GS_WCLEAR_MASK); |
| 948 |
s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK; |
| 949 |
dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta);
|
| 950 |
break;
|
| 951 |
default:
|
| 952 |
dolog ("U nabm writel %#x <- %#x\n", addr, val);
|
| 953 |
break;
|
| 954 |
} |
| 955 |
} |
| 956 |
|
| 957 |
static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r, |
| 958 |
int max, int *stop) |
| 959 |
{
|
| 960 |
uint8_t tmpbuf[4096];
|
| 961 |
uint32_t addr = r->bd.addr; |
| 962 |
uint32_t temp = r->picb << 1;
|
| 963 |
uint32_t written = 0;
|
| 964 |
int to_copy = 0; |
| 965 |
temp = audio_MIN (temp, max); |
| 966 |
|
| 967 |
if (!temp) {
|
| 968 |
*stop = 1;
|
| 969 |
return 0; |
| 970 |
} |
| 971 |
|
| 972 |
while (temp) {
|
| 973 |
int copied;
|
| 974 |
to_copy = audio_MIN (temp, sizeof (tmpbuf));
|
| 975 |
cpu_physical_memory_read (addr, tmpbuf, to_copy); |
| 976 |
copied = AUD_write (s->voice_po, tmpbuf, to_copy); |
| 977 |
dolog ("write_audio max=%x to_copy=%x copied=%x\n",
|
| 978 |
max, to_copy, copied); |
| 979 |
if (!copied) {
|
| 980 |
*stop = 1;
|
| 981 |
break;
|
| 982 |
} |
| 983 |
temp -= copied; |
| 984 |
addr += copied; |
| 985 |
written += copied; |
| 986 |
} |
| 987 |
|
| 988 |
if (!temp) {
|
| 989 |
if (to_copy < 4) { |
| 990 |
dolog ("whoops\n");
|
| 991 |
s->last_samp = 0;
|
| 992 |
} |
| 993 |
else {
|
| 994 |
s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4];
|
| 995 |
} |
| 996 |
} |
| 997 |
|
| 998 |
r->bd.addr = addr; |
| 999 |
return written;
|
| 1000 |
} |
| 1001 |
|
| 1002 |
static void write_bup (AC97LinkState *s, int elapsed) |
| 1003 |
{
|
| 1004 |
int written = 0; |
| 1005 |
|
| 1006 |
dolog ("write_bup\n");
|
| 1007 |
if (!(s->bup_flag & BUP_SET)) {
|
| 1008 |
if (s->bup_flag & BUP_LAST) {
|
| 1009 |
int i;
|
| 1010 |
uint8_t *p = s->silence; |
| 1011 |
for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) { |
| 1012 |
*(uint32_t *) p = s->last_samp; |
| 1013 |
} |
| 1014 |
} |
| 1015 |
else {
|
| 1016 |
memset (s->silence, 0, sizeof (s->silence)); |
| 1017 |
} |
| 1018 |
s->bup_flag |= BUP_SET; |
| 1019 |
} |
| 1020 |
|
| 1021 |
while (elapsed) {
|
| 1022 |
int temp = audio_MIN (elapsed, sizeof (s->silence)); |
| 1023 |
while (temp) {
|
| 1024 |
int copied = AUD_write (s->voice_po, s->silence, temp);
|
| 1025 |
if (!copied)
|
| 1026 |
return;
|
| 1027 |
temp -= copied; |
| 1028 |
elapsed -= copied; |
| 1029 |
written += copied; |
| 1030 |
} |
| 1031 |
} |
| 1032 |
} |
| 1033 |
|
| 1034 |
static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r, |
| 1035 |
int max, int *stop) |
| 1036 |
{
|
| 1037 |
uint8_t tmpbuf[4096];
|
| 1038 |
uint32_t addr = r->bd.addr; |
| 1039 |
uint32_t temp = r->picb << 1;
|
| 1040 |
uint32_t nread = 0;
|
| 1041 |
int to_copy = 0; |
| 1042 |
SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi; |
| 1043 |
|
| 1044 |
temp = audio_MIN (temp, max); |
| 1045 |
|
| 1046 |
if (!temp) {
|
| 1047 |
*stop = 1;
|
| 1048 |
return 0; |
| 1049 |
} |
| 1050 |
|
| 1051 |
while (temp) {
|
| 1052 |
int acquired;
|
| 1053 |
to_copy = audio_MIN (temp, sizeof (tmpbuf));
|
| 1054 |
acquired = AUD_read (voice, tmpbuf, to_copy); |
| 1055 |
if (!acquired) {
|
| 1056 |
*stop = 1;
|
| 1057 |
break;
|
| 1058 |
} |
| 1059 |
cpu_physical_memory_write (addr, tmpbuf, acquired); |
| 1060 |
temp -= acquired; |
| 1061 |
addr += acquired; |
| 1062 |
nread += acquired; |
| 1063 |
} |
| 1064 |
|
| 1065 |
r->bd.addr = addr; |
| 1066 |
return nread;
|
| 1067 |
} |
| 1068 |
|
| 1069 |
static void transfer_audio (AC97LinkState *s, int index, int elapsed) |
| 1070 |
{
|
| 1071 |
AC97BusMasterRegs *r = &s->bm_regs[index]; |
| 1072 |
int written = 0, stop = 0; |
| 1073 |
|
| 1074 |
if (s->invalid_freq[index]) {
|
| 1075 |
AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n", |
| 1076 |
index, s->invalid_freq[index]); |
| 1077 |
return;
|
| 1078 |
} |
| 1079 |
|
| 1080 |
if (r->sr & SR_DCH) {
|
| 1081 |
if (r->cr & CR_RPBM) {
|
| 1082 |
switch (index) {
|
| 1083 |
case PO_INDEX:
|
| 1084 |
write_bup (s, elapsed); |
| 1085 |
break;
|
| 1086 |
} |
| 1087 |
} |
| 1088 |
return;
|
| 1089 |
} |
| 1090 |
|
| 1091 |
while ((elapsed >> 1) && !stop) { |
| 1092 |
int temp;
|
| 1093 |
|
| 1094 |
if (!r->bd_valid) {
|
| 1095 |
dolog ("invalid bd\n");
|
| 1096 |
fetch_bd (s, r); |
| 1097 |
} |
| 1098 |
|
| 1099 |
if (!r->picb) {
|
| 1100 |
dolog ("fresh bd %d is empty %#x %#x\n",
|
| 1101 |
r->civ, r->bd.addr, r->bd.ctl_len); |
| 1102 |
if (r->civ == r->lvi) {
|
| 1103 |
r->sr |= SR_DCH; /* CELV? */
|
| 1104 |
s->bup_flag = 0;
|
| 1105 |
break;
|
| 1106 |
} |
| 1107 |
r->sr &= ~SR_CELV; |
| 1108 |
r->civ = r->piv; |
| 1109 |
r->piv = (r->piv + 1) % 32; |
| 1110 |
fetch_bd (s, r); |
| 1111 |
return;
|
| 1112 |
} |
| 1113 |
|
| 1114 |
switch (index) {
|
| 1115 |
case PO_INDEX:
|
| 1116 |
temp = write_audio (s, r, elapsed, &stop); |
| 1117 |
written += temp; |
| 1118 |
elapsed -= temp; |
| 1119 |
r->picb -= (temp >> 1);
|
| 1120 |
break;
|
| 1121 |
|
| 1122 |
case PI_INDEX:
|
| 1123 |
case MC_INDEX:
|
| 1124 |
temp = read_audio (s, r, elapsed, &stop); |
| 1125 |
elapsed -= temp; |
| 1126 |
r->picb -= (temp >> 1);
|
| 1127 |
break;
|
| 1128 |
} |
| 1129 |
|
| 1130 |
if (!r->picb) {
|
| 1131 |
uint32_t new_sr = r->sr & ~SR_CELV; |
| 1132 |
|
| 1133 |
if (r->bd.ctl_len & BD_IOC) {
|
| 1134 |
new_sr |= SR_BCIS; |
| 1135 |
} |
| 1136 |
|
| 1137 |
if (r->civ == r->lvi) {
|
| 1138 |
dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi);
|
| 1139 |
|
| 1140 |
new_sr |= SR_LVBCI | SR_DCH | SR_CELV; |
| 1141 |
stop = 1;
|
| 1142 |
s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
|
| 1143 |
} |
| 1144 |
else {
|
| 1145 |
r->civ = r->piv; |
| 1146 |
r->piv = (r->piv + 1) % 32; |
| 1147 |
fetch_bd (s, r); |
| 1148 |
} |
| 1149 |
|
| 1150 |
update_sr (s, r, new_sr); |
| 1151 |
} |
| 1152 |
} |
| 1153 |
} |
| 1154 |
|
| 1155 |
static void pi_callback (void *opaque, int avail) |
| 1156 |
{
|
| 1157 |
transfer_audio (opaque, PI_INDEX, avail); |
| 1158 |
} |
| 1159 |
|
| 1160 |
static void mc_callback (void *opaque, int avail) |
| 1161 |
{
|
| 1162 |
transfer_audio (opaque, MC_INDEX, avail); |
| 1163 |
} |
| 1164 |
|
| 1165 |
static void po_callback (void *opaque, int free) |
| 1166 |
{
|
| 1167 |
transfer_audio (opaque, PO_INDEX, free); |
| 1168 |
} |
| 1169 |
|
| 1170 |
static const VMStateDescription vmstate_ac97_bm_regs = { |
| 1171 |
.name = "ac97_bm_regs",
|
| 1172 |
.version_id = 1,
|
| 1173 |
.minimum_version_id = 1,
|
| 1174 |
.minimum_version_id_old = 1,
|
| 1175 |
.fields = (VMStateField []) {
|
| 1176 |
VMSTATE_UINT32(bdbar, AC97BusMasterRegs), |
| 1177 |
VMSTATE_UINT8(civ, AC97BusMasterRegs), |
| 1178 |
VMSTATE_UINT8(lvi, AC97BusMasterRegs), |
| 1179 |
VMSTATE_UINT16(sr, AC97BusMasterRegs), |
| 1180 |
VMSTATE_UINT16(picb, AC97BusMasterRegs), |
| 1181 |
VMSTATE_UINT8(piv, AC97BusMasterRegs), |
| 1182 |
VMSTATE_UINT8(cr, AC97BusMasterRegs), |
| 1183 |
VMSTATE_UINT32(bd_valid, AC97BusMasterRegs), |
| 1184 |
VMSTATE_UINT32(bd.addr, AC97BusMasterRegs), |
| 1185 |
VMSTATE_UINT32(bd.ctl_len, AC97BusMasterRegs), |
| 1186 |
VMSTATE_END_OF_LIST() |
| 1187 |
} |
| 1188 |
}; |
| 1189 |
|
| 1190 |
static int ac97_post_load (void *opaque, int version_id) |
| 1191 |
{
|
| 1192 |
uint8_t active[LAST_INDEX]; |
| 1193 |
AC97LinkState *s = opaque; |
| 1194 |
|
| 1195 |
#ifdef USE_MIXER
|
| 1196 |
record_select (s, mixer_load (s, AC97_Record_Select)); |
| 1197 |
#define V_(a, b) set_volume (s, a, b, mixer_load (s, a))
|
| 1198 |
V_ (AC97_Master_Volume_Mute, AUD_MIXER_VOLUME); |
| 1199 |
V_ (AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM); |
| 1200 |
V_ (AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN); |
| 1201 |
#undef V_
|
| 1202 |
#endif
|
| 1203 |
active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM); |
| 1204 |
active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM); |
| 1205 |
active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM); |
| 1206 |
reset_voices (s, active); |
| 1207 |
|
| 1208 |
s->bup_flag = 0;
|
| 1209 |
s->last_samp = 0;
|
| 1210 |
return 0; |
| 1211 |
} |
| 1212 |
|
| 1213 |
static bool is_version_2 (void *opaque, int version_id) |
| 1214 |
{
|
| 1215 |
return version_id == 2; |
| 1216 |
} |
| 1217 |
|
| 1218 |
static const VMStateDescription vmstate_ac97 = { |
| 1219 |
.name = "ac97",
|
| 1220 |
.version_id = 3,
|
| 1221 |
.minimum_version_id = 2,
|
| 1222 |
.minimum_version_id_old = 2,
|
| 1223 |
.post_load = ac97_post_load, |
| 1224 |
.fields = (VMStateField []) {
|
| 1225 |
VMSTATE_PCI_DEVICE(dev, AC97LinkState), |
| 1226 |
VMSTATE_UINT32(glob_cnt, AC97LinkState), |
| 1227 |
VMSTATE_UINT32(glob_sta, AC97LinkState), |
| 1228 |
VMSTATE_UINT32(cas, AC97LinkState), |
| 1229 |
VMSTATE_STRUCT_ARRAY(bm_regs, AC97LinkState, 3, 1, |
| 1230 |
vmstate_ac97_bm_regs, AC97BusMasterRegs), |
| 1231 |
VMSTATE_BUFFER(mixer_data, AC97LinkState), |
| 1232 |
VMSTATE_UNUSED_TEST(is_version_2, 3),
|
| 1233 |
VMSTATE_END_OF_LIST() |
| 1234 |
} |
| 1235 |
}; |
| 1236 |
|
| 1237 |
static void ac97_map (PCIDevice *pci_dev, int region_num, |
| 1238 |
pcibus_t addr, pcibus_t size, int type)
|
| 1239 |
{
|
| 1240 |
AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, pci_dev); |
| 1241 |
PCIDevice *d = &s->dev; |
| 1242 |
|
| 1243 |
if (!region_num) {
|
| 1244 |
s->base[0] = addr;
|
| 1245 |
register_ioport_read (addr, 256 * 1, 1, nam_readb, d); |
| 1246 |
register_ioport_read (addr, 256 * 2, 2, nam_readw, d); |
| 1247 |
register_ioport_read (addr, 256 * 4, 4, nam_readl, d); |
| 1248 |
register_ioport_write (addr, 256 * 1, 1, nam_writeb, d); |
| 1249 |
register_ioport_write (addr, 256 * 2, 2, nam_writew, d); |
| 1250 |
register_ioport_write (addr, 256 * 4, 4, nam_writel, d); |
| 1251 |
} |
| 1252 |
else {
|
| 1253 |
s->base[1] = addr;
|
| 1254 |
register_ioport_read (addr, 64 * 1, 1, nabm_readb, d); |
| 1255 |
register_ioport_read (addr, 64 * 2, 2, nabm_readw, d); |
| 1256 |
register_ioport_read (addr, 64 * 4, 4, nabm_readl, d); |
| 1257 |
register_ioport_write (addr, 64 * 1, 1, nabm_writeb, d); |
| 1258 |
register_ioport_write (addr, 64 * 2, 2, nabm_writew, d); |
| 1259 |
register_ioport_write (addr, 64 * 4, 4, nabm_writel, d); |
| 1260 |
} |
| 1261 |
} |
| 1262 |
|
| 1263 |
static void ac97_on_reset (void *opaque) |
| 1264 |
{
|
| 1265 |
AC97LinkState *s = opaque; |
| 1266 |
|
| 1267 |
reset_bm_regs (s, &s->bm_regs[0]);
|
| 1268 |
reset_bm_regs (s, &s->bm_regs[1]);
|
| 1269 |
reset_bm_regs (s, &s->bm_regs[2]);
|
| 1270 |
|
| 1271 |
/*
|
| 1272 |
* Reset the mixer too. The Windows XP driver seems to rely on
|
| 1273 |
* this. At least it wants to read the vendor id before it resets
|
| 1274 |
* the codec manually.
|
| 1275 |
*/
|
| 1276 |
mixer_reset (s); |
| 1277 |
} |
| 1278 |
|
| 1279 |
static int ac97_initfn (PCIDevice *dev) |
| 1280 |
{
|
| 1281 |
AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev); |
| 1282 |
uint8_t *c = s->dev.config; |
| 1283 |
|
| 1284 |
pci_config_set_vendor_id (c, PCI_VENDOR_ID_INTEL); /* ro */
|
| 1285 |
pci_config_set_device_id (c, PCI_DEVICE_ID_INTEL_82801AA_5); /* ro */
|
| 1286 |
|
| 1287 |
c[0x04] = 0x00; /* pcicmd pci command rw, ro */ |
| 1288 |
c[0x05] = 0x00; |
| 1289 |
|
| 1290 |
c[0x06] = 0x80; /* pcists pci status rwc, ro */ |
| 1291 |
c[0x07] = 0x02; |
| 1292 |
|
| 1293 |
c[0x08] = 0x01; /* rid revision ro */ |
| 1294 |
c[0x09] = 0x00; /* pi programming interface ro */ |
| 1295 |
pci_config_set_class (c, PCI_CLASS_MULTIMEDIA_AUDIO); /* ro */
|
| 1296 |
c[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* headtyp header type ro */
|
| 1297 |
|
| 1298 |
c[0x10] = 0x01; /* nabmar native audio mixer base |
| 1299 |
address rw */
|
| 1300 |
c[0x11] = 0x00; |
| 1301 |
c[0x12] = 0x00; |
| 1302 |
c[0x13] = 0x00; |
| 1303 |
|
| 1304 |
c[0x14] = 0x01; /* nabmbar native audio bus mastering |
| 1305 |
base address rw */
|
| 1306 |
c[0x15] = 0x00; |
| 1307 |
c[0x16] = 0x00; |
| 1308 |
c[0x17] = 0x00; |
| 1309 |
|
| 1310 |
c[0x2c] = 0x86; /* svid subsystem vendor id rwo */ |
| 1311 |
c[0x2d] = 0x80; |
| 1312 |
|
| 1313 |
c[0x2e] = 0x00; /* sid subsystem id rwo */ |
| 1314 |
c[0x2f] = 0x00; |
| 1315 |
|
| 1316 |
c[0x3c] = 0x00; /* intr_ln interrupt line rw */ |
| 1317 |
c[0x3d] = 0x01; /* intr_pn interrupt pin ro */ |
| 1318 |
|
| 1319 |
pci_register_bar (&s->dev, 0, 256 * 4, PCI_BASE_ADDRESS_SPACE_IO, |
| 1320 |
ac97_map); |
| 1321 |
pci_register_bar (&s->dev, 1, 64 * 4, PCI_BASE_ADDRESS_SPACE_IO, ac97_map); |
| 1322 |
vmstate_register (0, &vmstate_ac97, s);
|
| 1323 |
qemu_register_reset (ac97_on_reset, s); |
| 1324 |
AUD_register_card ("ac97", &s->card);
|
| 1325 |
ac97_on_reset (s); |
| 1326 |
return 0; |
| 1327 |
} |
| 1328 |
|
| 1329 |
int ac97_init (PCIBus *bus)
|
| 1330 |
{
|
| 1331 |
pci_create_simple (bus, -1, "AC97"); |
| 1332 |
return 0; |
| 1333 |
} |
| 1334 |
|
| 1335 |
static PCIDeviceInfo ac97_info = {
|
| 1336 |
.qdev.name = "AC97",
|
| 1337 |
.qdev.desc = "Intel 82801AA AC97 Audio",
|
| 1338 |
.qdev.size = sizeof (AC97LinkState),
|
| 1339 |
.init = ac97_initfn, |
| 1340 |
}; |
| 1341 |
|
| 1342 |
static void ac97_register (void) |
| 1343 |
{
|
| 1344 |
pci_qdev_register (&ac97_info); |
| 1345 |
} |
| 1346 |
device_init (ac97_register); |
| 1347 |
|