root / tcg / tcg-op.h @ a9751609
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "tcg.h" |
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int gen_new_label(void); |
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static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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} |
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static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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} |
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static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = arg1; |
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} |
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static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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} |
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static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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} |
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static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = arg2; |
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} |
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static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = arg2; |
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} |
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static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = arg1; |
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*gen_opparam_ptr++ = arg2; |
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} |
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static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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} |
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static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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} |
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static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1, |
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TCGv_i32 arg2, TCGArg arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = arg3; |
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} |
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static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1, |
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TCGv_i64 arg2, TCGArg arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = arg3; |
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} |
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static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, |
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TCGv_ptr base, TCGArg offset) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(val); |
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*gen_opparam_ptr++ = GET_TCGV_PTR(base); |
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*gen_opparam_ptr++ = offset; |
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} |
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static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, |
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TCGv_ptr base, TCGArg offset) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(val); |
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*gen_opparam_ptr++ = GET_TCGV_PTR(base); |
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*gen_opparam_ptr++ = offset; |
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} |
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static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val, |
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TCGv_i32 addr, TCGArg mem_index) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(val); |
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*gen_opparam_ptr++ = GET_TCGV_I32(addr); |
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*gen_opparam_ptr++ = mem_index; |
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} |
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static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val, |
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TCGv_i64 addr, TCGArg mem_index) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(val); |
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*gen_opparam_ptr++ = GET_TCGV_I64(addr); |
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*gen_opparam_ptr++ = mem_index; |
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} |
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static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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} |
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static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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} |
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static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGArg arg3, TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = arg3; |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGArg arg3, TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = arg3; |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
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} |
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static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
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} |
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static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = arg5; |
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} |
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static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = arg5; |
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} |
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static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, |
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TCGv_i32 arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg6); |
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} |
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static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, |
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TCGv_i64 arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg6); |
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} |
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static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, |
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TCGv_i32 arg5, TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
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*gen_opparam_ptr++ = arg6; |
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} |
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static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, |
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TCGv_i64 arg5, TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
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*gen_opparam_ptr++ = arg6; |
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} |
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static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1, |
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TCGv_i32 arg2, TCGv_i32 arg3, |
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TCGv_i32 arg4, TCGArg arg5, TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = arg5; |
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*gen_opparam_ptr++ = arg6; |
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} |
321 |
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static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1, |
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TCGv_i64 arg2, TCGv_i64 arg3, |
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TCGv_i64 arg4, TCGArg arg5, TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = arg5; |
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*gen_opparam_ptr++ = arg6; |
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} |
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|
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static inline void gen_set_label(int n) |
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{ |
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tcg_gen_op1i(INDEX_op_set_label, n); |
338 |
} |
339 |
|
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static inline void tcg_gen_br(int label) |
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{ |
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tcg_gen_op1i(INDEX_op_br, label); |
343 |
} |
344 |
|
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static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
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{ |
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if (!TCGV_EQUAL_I32(ret, arg))
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tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
349 |
} |
350 |
|
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static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
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{ |
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tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
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} |
355 |
|
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/* helper calls */
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static inline void tcg_gen_helperN(void *func, int flags, int sizemask, |
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TCGArg ret, int nargs, TCGArg *args)
|
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{ |
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TCGv_ptr fn; |
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fn = tcg_const_ptr((tcg_target_long)func); |
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tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret, |
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nargs, args); |
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tcg_temp_free_ptr(fn); |
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} |
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|
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/* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
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reserved for helpers in tcg-runtime.c. These helpers are all const
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and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST |
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TCG_CALL_PURE. This may need to be adjusted if these functions
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start to be used with other helpers. */
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static inline void tcg_gen_helper32(void *func, TCGv_i32 ret, |
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TCGv_i32 a, TCGv_i32 b) |
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{ |
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TCGv_ptr fn; |
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TCGArg args[2];
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fn = tcg_const_ptr((tcg_target_long)func); |
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args[0] = GET_TCGV_I32(a);
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args[1] = GET_TCGV_I32(b);
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tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, |
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0, GET_TCGV_I32(ret), 2, args); |
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tcg_temp_free_ptr(fn); |
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} |
384 |
|
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static inline void tcg_gen_helper64(void *func, TCGv_i64 ret, |
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TCGv_i64 a, TCGv_i64 b) |
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{ |
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TCGv_ptr fn; |
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TCGArg args[2];
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fn = tcg_const_ptr((tcg_target_long)func); |
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args[0] = GET_TCGV_I64(a);
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args[1] = GET_TCGV_I64(b);
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tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, |
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7, GET_TCGV_I64(ret), 2, args); |
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tcg_temp_free_ptr(fn); |
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} |
397 |
|
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/* 32 bit ops */
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|
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static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
401 |
{ |
402 |
tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
403 |
} |
404 |
|
405 |
static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
406 |
{ |
407 |
tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
408 |
} |
409 |
|
410 |
static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
411 |
{ |
412 |
tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
413 |
} |
414 |
|
415 |
static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
416 |
{ |
417 |
tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
418 |
} |
419 |
|
420 |
static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
421 |
{ |
422 |
tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
423 |
} |
424 |
|
425 |
static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
426 |
{ |
427 |
tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
428 |
} |
429 |
|
430 |
static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
431 |
{ |
432 |
tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
433 |
} |
434 |
|
435 |
static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
436 |
{ |
437 |
tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
438 |
} |
439 |
|
440 |
static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
441 |
{ |
442 |
tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
443 |
} |
444 |
|
445 |
static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
446 |
{ |
447 |
/* some cases can be optimized here */
|
448 |
if (arg2 == 0) { |
449 |
tcg_gen_mov_i32(ret, arg1); |
450 |
} else {
|
451 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
452 |
tcg_gen_add_i32(ret, arg1, t0); |
453 |
tcg_temp_free_i32(t0); |
454 |
} |
455 |
} |
456 |
|
457 |
static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
458 |
{ |
459 |
tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
460 |
} |
461 |
|
462 |
static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) |
463 |
{ |
464 |
TCGv_i32 t0 = tcg_const_i32(arg1); |
465 |
tcg_gen_sub_i32(ret, t0, arg2); |
466 |
tcg_temp_free_i32(t0); |
467 |
} |
468 |
|
469 |
static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
470 |
{ |
471 |
/* some cases can be optimized here */
|
472 |
if (arg2 == 0) { |
473 |
tcg_gen_mov_i32(ret, arg1); |
474 |
} else {
|
475 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
476 |
tcg_gen_sub_i32(ret, arg1, t0); |
477 |
tcg_temp_free_i32(t0); |
478 |
} |
479 |
} |
480 |
|
481 |
static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
482 |
{ |
483 |
if (TCGV_EQUAL_I32(arg1, arg2)) {
|
484 |
tcg_gen_mov_i32(ret, arg1); |
485 |
} else {
|
486 |
tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); |
487 |
} |
488 |
} |
489 |
|
490 |
static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
491 |
{ |
492 |
/* some cases can be optimized here */
|
493 |
if (arg2 == 0) { |
494 |
tcg_gen_movi_i32(ret, 0);
|
495 |
} else if (arg2 == 0xffffffff) { |
496 |
tcg_gen_mov_i32(ret, arg1); |
497 |
} else {
|
498 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
499 |
tcg_gen_and_i32(ret, arg1, t0); |
500 |
tcg_temp_free_i32(t0); |
501 |
} |
502 |
} |
503 |
|
504 |
static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
505 |
{ |
506 |
if (TCGV_EQUAL_I32(arg1, arg2)) {
|
507 |
tcg_gen_mov_i32(ret, arg1); |
508 |
} else {
|
509 |
tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); |
510 |
} |
511 |
} |
512 |
|
513 |
static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
514 |
{ |
515 |
/* some cases can be optimized here */
|
516 |
if (arg2 == 0xffffffff) { |
517 |
tcg_gen_movi_i32(ret, 0xffffffff);
|
518 |
} else if (arg2 == 0) { |
519 |
tcg_gen_mov_i32(ret, arg1); |
520 |
} else {
|
521 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
522 |
tcg_gen_or_i32(ret, arg1, t0); |
523 |
tcg_temp_free_i32(t0); |
524 |
} |
525 |
} |
526 |
|
527 |
static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
528 |
{ |
529 |
if (TCGV_EQUAL_I32(arg1, arg2)) {
|
530 |
tcg_gen_movi_i32(ret, 0);
|
531 |
} else {
|
532 |
tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); |
533 |
} |
534 |
} |
535 |
|
536 |
static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
537 |
{ |
538 |
/* some cases can be optimized here */
|
539 |
if (arg2 == 0) { |
540 |
tcg_gen_mov_i32(ret, arg1); |
541 |
} else {
|
542 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
543 |
tcg_gen_xor_i32(ret, arg1, t0); |
544 |
tcg_temp_free_i32(t0); |
545 |
} |
546 |
} |
547 |
|
548 |
static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
549 |
{ |
550 |
tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
551 |
} |
552 |
|
553 |
static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
554 |
{ |
555 |
if (arg2 == 0) { |
556 |
tcg_gen_mov_i32(ret, arg1); |
557 |
} else {
|
558 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
559 |
tcg_gen_shl_i32(ret, arg1, t0); |
560 |
tcg_temp_free_i32(t0); |
561 |
} |
562 |
} |
563 |
|
564 |
static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
565 |
{ |
566 |
tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
567 |
} |
568 |
|
569 |
static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
570 |
{ |
571 |
if (arg2 == 0) { |
572 |
tcg_gen_mov_i32(ret, arg1); |
573 |
} else {
|
574 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
575 |
tcg_gen_shr_i32(ret, arg1, t0); |
576 |
tcg_temp_free_i32(t0); |
577 |
} |
578 |
} |
579 |
|
580 |
static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
581 |
{ |
582 |
tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
583 |
} |
584 |
|
585 |
static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
586 |
{ |
587 |
if (arg2 == 0) { |
588 |
tcg_gen_mov_i32(ret, arg1); |
589 |
} else {
|
590 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
591 |
tcg_gen_sar_i32(ret, arg1, t0); |
592 |
tcg_temp_free_i32(t0); |
593 |
} |
594 |
} |
595 |
|
596 |
static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2, |
597 |
int label_index)
|
598 |
{ |
599 |
tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
600 |
} |
601 |
|
602 |
static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2, |
603 |
int label_index)
|
604 |
{ |
605 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
606 |
tcg_gen_brcond_i32(cond, arg1, t0, label_index); |
607 |
tcg_temp_free_i32(t0); |
608 |
} |
609 |
|
610 |
static inline void tcg_gen_setcond_i32(int cond, TCGv_i32 ret, |
611 |
TCGv_i32 arg1, TCGv_i32 arg2) |
612 |
{ |
613 |
tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); |
614 |
} |
615 |
|
616 |
static inline void tcg_gen_setcondi_i32(int cond, TCGv_i32 ret, TCGv_i32 arg1, |
617 |
int32_t arg2) |
618 |
{ |
619 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
620 |
tcg_gen_setcond_i32(cond, ret, arg1, t0); |
621 |
tcg_temp_free_i32(t0); |
622 |
} |
623 |
|
624 |
static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
625 |
{ |
626 |
tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
627 |
} |
628 |
|
629 |
static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
630 |
{ |
631 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
632 |
tcg_gen_mul_i32(ret, arg1, t0); |
633 |
tcg_temp_free_i32(t0); |
634 |
} |
635 |
|
636 |
#ifdef TCG_TARGET_HAS_div_i32
|
637 |
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
638 |
{ |
639 |
tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); |
640 |
} |
641 |
|
642 |
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
643 |
{ |
644 |
tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); |
645 |
} |
646 |
|
647 |
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
648 |
{ |
649 |
tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); |
650 |
} |
651 |
|
652 |
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
653 |
{ |
654 |
tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); |
655 |
} |
656 |
#elif defined(TCG_TARGET_HAS_div2_i32)
|
657 |
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
658 |
{ |
659 |
TCGv_i32 t0; |
660 |
t0 = tcg_temp_new_i32(); |
661 |
tcg_gen_sari_i32(t0, arg1, 31);
|
662 |
tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
663 |
tcg_temp_free_i32(t0); |
664 |
} |
665 |
|
666 |
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
667 |
{ |
668 |
TCGv_i32 t0; |
669 |
t0 = tcg_temp_new_i32(); |
670 |
tcg_gen_sari_i32(t0, arg1, 31);
|
671 |
tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
672 |
tcg_temp_free_i32(t0); |
673 |
} |
674 |
|
675 |
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
676 |
{ |
677 |
TCGv_i32 t0; |
678 |
t0 = tcg_temp_new_i32(); |
679 |
tcg_gen_movi_i32(t0, 0);
|
680 |
tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
681 |
tcg_temp_free_i32(t0); |
682 |
} |
683 |
|
684 |
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
685 |
{ |
686 |
TCGv_i32 t0; |
687 |
t0 = tcg_temp_new_i32(); |
688 |
tcg_gen_movi_i32(t0, 0);
|
689 |
tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
690 |
tcg_temp_free_i32(t0); |
691 |
} |
692 |
#else
|
693 |
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
694 |
{ |
695 |
tcg_gen_helper32(tcg_helper_div_i32, ret, arg1, arg2); |
696 |
} |
697 |
|
698 |
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
699 |
{ |
700 |
tcg_gen_helper32(tcg_helper_rem_i32, ret, arg1, arg2); |
701 |
} |
702 |
|
703 |
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
704 |
{ |
705 |
tcg_gen_helper32(tcg_helper_divu_i32, ret, arg1, arg2); |
706 |
} |
707 |
|
708 |
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
709 |
{ |
710 |
tcg_gen_helper32(tcg_helper_remu_i32, ret, arg1, arg2); |
711 |
} |
712 |
#endif
|
713 |
|
714 |
#if TCG_TARGET_REG_BITS == 32 |
715 |
|
716 |
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
717 |
{ |
718 |
if (!TCGV_EQUAL_I64(ret, arg)) {
|
719 |
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
720 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
721 |
} |
722 |
} |
723 |
|
724 |
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
725 |
{ |
726 |
tcg_gen_movi_i32(TCGV_LOW(ret), arg); |
727 |
tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
|
728 |
} |
729 |
|
730 |
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
731 |
tcg_target_long offset) |
732 |
{ |
733 |
tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); |
734 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
735 |
} |
736 |
|
737 |
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
738 |
tcg_target_long offset) |
739 |
{ |
740 |
tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); |
741 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
|
742 |
} |
743 |
|
744 |
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
745 |
tcg_target_long offset) |
746 |
{ |
747 |
tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); |
748 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
749 |
} |
750 |
|
751 |
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
752 |
tcg_target_long offset) |
753 |
{ |
754 |
tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); |
755 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
756 |
} |
757 |
|
758 |
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
759 |
tcg_target_long offset) |
760 |
{ |
761 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
762 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
763 |
} |
764 |
|
765 |
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
766 |
tcg_target_long offset) |
767 |
{ |
768 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
769 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
770 |
} |
771 |
|
772 |
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
773 |
tcg_target_long offset) |
774 |
{ |
775 |
/* since arg2 and ret have different types, they cannot be the
|
776 |
same temporary */
|
777 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
778 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
779 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
|
780 |
#else
|
781 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
782 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
|
783 |
#endif
|
784 |
} |
785 |
|
786 |
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
787 |
tcg_target_long offset) |
788 |
{ |
789 |
tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
790 |
} |
791 |
|
792 |
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
793 |
tcg_target_long offset) |
794 |
{ |
795 |
tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
796 |
} |
797 |
|
798 |
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
799 |
tcg_target_long offset) |
800 |
{ |
801 |
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
802 |
} |
803 |
|
804 |
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
805 |
tcg_target_long offset) |
806 |
{ |
807 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
808 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
809 |
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
|
810 |
#else
|
811 |
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
812 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
|
813 |
#endif
|
814 |
} |
815 |
|
816 |
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
817 |
{ |
818 |
tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
819 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
820 |
TCGV_HIGH(arg2)); |
821 |
} |
822 |
|
823 |
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
824 |
{ |
825 |
tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
826 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
827 |
TCGV_HIGH(arg2)); |
828 |
} |
829 |
|
830 |
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
831 |
{ |
832 |
tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
833 |
tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
834 |
} |
835 |
|
836 |
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
837 |
{ |
838 |
tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
839 |
tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
840 |
} |
841 |
|
842 |
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
843 |
{ |
844 |
tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
845 |
tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
846 |
} |
847 |
|
848 |
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
849 |
{ |
850 |
tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
851 |
tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
852 |
} |
853 |
|
854 |
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
855 |
{ |
856 |
tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
857 |
tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
858 |
} |
859 |
|
860 |
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
861 |
{ |
862 |
tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
863 |
tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
864 |
} |
865 |
|
866 |
/* XXX: use generic code when basic block handling is OK or CPU
|
867 |
specific code (x86) */
|
868 |
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
869 |
{ |
870 |
tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2); |
871 |
} |
872 |
|
873 |
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
874 |
{ |
875 |
tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); |
876 |
} |
877 |
|
878 |
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
879 |
{ |
880 |
tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2); |
881 |
} |
882 |
|
883 |
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
884 |
{ |
885 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); |
886 |
} |
887 |
|
888 |
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
889 |
{ |
890 |
tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2); |
891 |
} |
892 |
|
893 |
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
894 |
{ |
895 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); |
896 |
} |
897 |
|
898 |
static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2, |
899 |
int label_index)
|
900 |
{ |
901 |
tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, |
902 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
903 |
TCGV_HIGH(arg2), cond, label_index); |
904 |
} |
905 |
|
906 |
static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret, |
907 |
TCGv_i64 arg1, TCGv_i64 arg2) |
908 |
{ |
909 |
tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), |
910 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), |
911 |
TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); |
912 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
913 |
} |
914 |
|
915 |
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
916 |
{ |
917 |
TCGv_i64 t0; |
918 |
TCGv_i32 t1; |
919 |
|
920 |
t0 = tcg_temp_new_i64(); |
921 |
t1 = tcg_temp_new_i32(); |
922 |
|
923 |
tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), |
924 |
TCGV_LOW(arg1), TCGV_LOW(arg2)); |
925 |
|
926 |
tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); |
927 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
928 |
tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); |
929 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
930 |
|
931 |
tcg_gen_mov_i64(ret, t0); |
932 |
tcg_temp_free_i64(t0); |
933 |
tcg_temp_free_i32(t1); |
934 |
} |
935 |
|
936 |
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
937 |
{ |
938 |
tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2); |
939 |
} |
940 |
|
941 |
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
942 |
{ |
943 |
tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2); |
944 |
} |
945 |
|
946 |
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
947 |
{ |
948 |
tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2); |
949 |
} |
950 |
|
951 |
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
952 |
{ |
953 |
tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2); |
954 |
} |
955 |
|
956 |
#else
|
957 |
|
958 |
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
959 |
{ |
960 |
if (!TCGV_EQUAL_I64(ret, arg))
|
961 |
tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
962 |
} |
963 |
|
964 |
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
965 |
{ |
966 |
tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
967 |
} |
968 |
|
969 |
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
970 |
tcg_target_long offset) |
971 |
{ |
972 |
tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
973 |
} |
974 |
|
975 |
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
976 |
tcg_target_long offset) |
977 |
{ |
978 |
tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
979 |
} |
980 |
|
981 |
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
982 |
tcg_target_long offset) |
983 |
{ |
984 |
tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
985 |
} |
986 |
|
987 |
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
988 |
tcg_target_long offset) |
989 |
{ |
990 |
tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
991 |
} |
992 |
|
993 |
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
994 |
tcg_target_long offset) |
995 |
{ |
996 |
tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
997 |
} |
998 |
|
999 |
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
1000 |
tcg_target_long offset) |
1001 |
{ |
1002 |
tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
1003 |
} |
1004 |
|
1005 |
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset) |
1006 |
{ |
1007 |
tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
1008 |
} |
1009 |
|
1010 |
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
1011 |
tcg_target_long offset) |
1012 |
{ |
1013 |
tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
1014 |
} |
1015 |
|
1016 |
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
1017 |
tcg_target_long offset) |
1018 |
{ |
1019 |
tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
1020 |
} |
1021 |
|
1022 |
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
1023 |
tcg_target_long offset) |
1024 |
{ |
1025 |
tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
1026 |
} |
1027 |
|
1028 |
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset) |
1029 |
{ |
1030 |
tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
1031 |
} |
1032 |
|
1033 |
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1034 |
{ |
1035 |
tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
1036 |
} |
1037 |
|
1038 |
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1039 |
{ |
1040 |
tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
1041 |
} |
1042 |
|
1043 |
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1044 |
{ |
1045 |
if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1046 |
tcg_gen_mov_i64(ret, arg1); |
1047 |
} else {
|
1048 |
tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); |
1049 |
} |
1050 |
} |
1051 |
|
1052 |
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1053 |
{ |
1054 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1055 |
tcg_gen_and_i64(ret, arg1, t0); |
1056 |
tcg_temp_free_i64(t0); |
1057 |
} |
1058 |
|
1059 |
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1060 |
{ |
1061 |
if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1062 |
tcg_gen_mov_i64(ret, arg1); |
1063 |
} else {
|
1064 |
tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); |
1065 |
} |
1066 |
} |
1067 |
|
1068 |
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1069 |
{ |
1070 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1071 |
tcg_gen_or_i64(ret, arg1, t0); |
1072 |
tcg_temp_free_i64(t0); |
1073 |
} |
1074 |
|
1075 |
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1076 |
{ |
1077 |
if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1078 |
tcg_gen_movi_i64(ret, 0);
|
1079 |
} else {
|
1080 |
tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); |
1081 |
} |
1082 |
} |
1083 |
|
1084 |
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1085 |
{ |
1086 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1087 |
tcg_gen_xor_i64(ret, arg1, t0); |
1088 |
tcg_temp_free_i64(t0); |
1089 |
} |
1090 |
|
1091 |
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1092 |
{ |
1093 |
tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
1094 |
} |
1095 |
|
1096 |
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1097 |
{ |
1098 |
if (arg2 == 0) { |
1099 |
tcg_gen_mov_i64(ret, arg1); |
1100 |
} else {
|
1101 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1102 |
tcg_gen_shl_i64(ret, arg1, t0); |
1103 |
tcg_temp_free_i64(t0); |
1104 |
} |
1105 |
} |
1106 |
|
1107 |
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1108 |
{ |
1109 |
tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
1110 |
} |
1111 |
|
1112 |
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1113 |
{ |
1114 |
if (arg2 == 0) { |
1115 |
tcg_gen_mov_i64(ret, arg1); |
1116 |
} else {
|
1117 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1118 |
tcg_gen_shr_i64(ret, arg1, t0); |
1119 |
tcg_temp_free_i64(t0); |
1120 |
} |
1121 |
} |
1122 |
|
1123 |
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1124 |
{ |
1125 |
tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
1126 |
} |
1127 |
|
1128 |
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1129 |
{ |
1130 |
if (arg2 == 0) { |
1131 |
tcg_gen_mov_i64(ret, arg1); |
1132 |
} else {
|
1133 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1134 |
tcg_gen_sar_i64(ret, arg1, t0); |
1135 |
tcg_temp_free_i64(t0); |
1136 |
} |
1137 |
} |
1138 |
|
1139 |
static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2, |
1140 |
int label_index)
|
1141 |
{ |
1142 |
tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
1143 |
} |
1144 |
|
1145 |
static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret, |
1146 |
TCGv_i64 arg1, TCGv_i64 arg2) |
1147 |
{ |
1148 |
tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); |
1149 |
} |
1150 |
|
1151 |
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1152 |
{ |
1153 |
tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
1154 |
} |
1155 |
|
1156 |
#ifdef TCG_TARGET_HAS_div_i64
|
1157 |
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1158 |
{ |
1159 |
tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); |
1160 |
} |
1161 |
|
1162 |
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1163 |
{ |
1164 |
tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); |
1165 |
} |
1166 |
|
1167 |
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1168 |
{ |
1169 |
tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); |
1170 |
} |
1171 |
|
1172 |
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1173 |
{ |
1174 |
tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); |
1175 |
} |
1176 |
#elif defined(TCG_TARGET_HAS_div2_i64)
|
1177 |
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1178 |
{ |
1179 |
TCGv_i64 t0; |
1180 |
t0 = tcg_temp_new_i64(); |
1181 |
tcg_gen_sari_i64(t0, arg1, 63);
|
1182 |
tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
1183 |
tcg_temp_free_i64(t0); |
1184 |
} |
1185 |
|
1186 |
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1187 |
{ |
1188 |
TCGv_i64 t0; |
1189 |
t0 = tcg_temp_new_i64(); |
1190 |
tcg_gen_sari_i64(t0, arg1, 63);
|
1191 |
tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
1192 |
tcg_temp_free_i64(t0); |
1193 |
} |
1194 |
|
1195 |
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1196 |
{ |
1197 |
TCGv_i64 t0; |
1198 |
t0 = tcg_temp_new_i64(); |
1199 |
tcg_gen_movi_i64(t0, 0);
|
1200 |
tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
1201 |
tcg_temp_free_i64(t0); |
1202 |
} |
1203 |
|
1204 |
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1205 |
{ |
1206 |
TCGv_i64 t0; |
1207 |
t0 = tcg_temp_new_i64(); |
1208 |
tcg_gen_movi_i64(t0, 0);
|
1209 |
tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
1210 |
tcg_temp_free_i64(t0); |
1211 |
} |
1212 |
#else
|
1213 |
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1214 |
{ |
1215 |
tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2); |
1216 |
} |
1217 |
|
1218 |
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1219 |
{ |
1220 |
tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2); |
1221 |
} |
1222 |
|
1223 |
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1224 |
{ |
1225 |
tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2); |
1226 |
} |
1227 |
|
1228 |
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1229 |
{ |
1230 |
tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2); |
1231 |
} |
1232 |
#endif
|
1233 |
|
1234 |
#endif
|
1235 |
|
1236 |
static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1237 |
{ |
1238 |
/* some cases can be optimized here */
|
1239 |
if (arg2 == 0) { |
1240 |
tcg_gen_mov_i64(ret, arg1); |
1241 |
} else {
|
1242 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1243 |
tcg_gen_add_i64(ret, arg1, t0); |
1244 |
tcg_temp_free_i64(t0); |
1245 |
} |
1246 |
} |
1247 |
|
1248 |
static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) |
1249 |
{ |
1250 |
TCGv_i64 t0 = tcg_const_i64(arg1); |
1251 |
tcg_gen_sub_i64(ret, t0, arg2); |
1252 |
tcg_temp_free_i64(t0); |
1253 |
} |
1254 |
|
1255 |
static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1256 |
{ |
1257 |
/* some cases can be optimized here */
|
1258 |
if (arg2 == 0) { |
1259 |
tcg_gen_mov_i64(ret, arg1); |
1260 |
} else {
|
1261 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1262 |
tcg_gen_sub_i64(ret, arg1, t0); |
1263 |
tcg_temp_free_i64(t0); |
1264 |
} |
1265 |
} |
1266 |
static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2, |
1267 |
int label_index)
|
1268 |
{ |
1269 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1270 |
tcg_gen_brcond_i64(cond, arg1, t0, label_index); |
1271 |
tcg_temp_free_i64(t0); |
1272 |
} |
1273 |
|
1274 |
static inline void tcg_gen_setcondi_i64(int cond, TCGv_i64 ret, TCGv_i64 arg1, |
1275 |
int64_t arg2) |
1276 |
{ |
1277 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1278 |
tcg_gen_setcond_i64(cond, ret, arg1, t0); |
1279 |
tcg_temp_free_i64(t0); |
1280 |
} |
1281 |
|
1282 |
static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1283 |
{ |
1284 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1285 |
tcg_gen_mul_i64(ret, arg1, t0); |
1286 |
tcg_temp_free_i64(t0); |
1287 |
} |
1288 |
|
1289 |
|
1290 |
/***************************************/
|
1291 |
/* optional operations */
|
1292 |
|
1293 |
static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) |
1294 |
{ |
1295 |
#ifdef TCG_TARGET_HAS_ext8s_i32
|
1296 |
tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); |
1297 |
#else
|
1298 |
tcg_gen_shli_i32(ret, arg, 24);
|
1299 |
tcg_gen_sari_i32(ret, ret, 24);
|
1300 |
#endif
|
1301 |
} |
1302 |
|
1303 |
static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) |
1304 |
{ |
1305 |
#ifdef TCG_TARGET_HAS_ext16s_i32
|
1306 |
tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); |
1307 |
#else
|
1308 |
tcg_gen_shli_i32(ret, arg, 16);
|
1309 |
tcg_gen_sari_i32(ret, ret, 16);
|
1310 |
#endif
|
1311 |
} |
1312 |
|
1313 |
static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) |
1314 |
{ |
1315 |
#ifdef TCG_TARGET_HAS_ext8u_i32
|
1316 |
tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); |
1317 |
#else
|
1318 |
tcg_gen_andi_i32(ret, arg, 0xffu);
|
1319 |
#endif
|
1320 |
} |
1321 |
|
1322 |
static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) |
1323 |
{ |
1324 |
#ifdef TCG_TARGET_HAS_ext16u_i32
|
1325 |
tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); |
1326 |
#else
|
1327 |
tcg_gen_andi_i32(ret, arg, 0xffffu);
|
1328 |
#endif
|
1329 |
} |
1330 |
|
1331 |
/* Note: we assume the two high bytes are set to zero */
|
1332 |
static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) |
1333 |
{ |
1334 |
#ifdef TCG_TARGET_HAS_bswap16_i32
|
1335 |
tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); |
1336 |
#else
|
1337 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
1338 |
|
1339 |
tcg_gen_ext8u_i32(t0, arg); |
1340 |
tcg_gen_shli_i32(t0, t0, 8);
|
1341 |
tcg_gen_shri_i32(ret, arg, 8);
|
1342 |
tcg_gen_or_i32(ret, ret, t0); |
1343 |
tcg_temp_free_i32(t0); |
1344 |
#endif
|
1345 |
} |
1346 |
|
1347 |
static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) |
1348 |
{ |
1349 |
#ifdef TCG_TARGET_HAS_bswap32_i32
|
1350 |
tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); |
1351 |
#else
|
1352 |
TCGv_i32 t0, t1; |
1353 |
t0 = tcg_temp_new_i32(); |
1354 |
t1 = tcg_temp_new_i32(); |
1355 |
|
1356 |
tcg_gen_shli_i32(t0, arg, 24);
|
1357 |
|
1358 |
tcg_gen_andi_i32(t1, arg, 0x0000ff00);
|
1359 |
tcg_gen_shli_i32(t1, t1, 8);
|
1360 |
tcg_gen_or_i32(t0, t0, t1); |
1361 |
|
1362 |
tcg_gen_shri_i32(t1, arg, 8);
|
1363 |
tcg_gen_andi_i32(t1, t1, 0x0000ff00);
|
1364 |
tcg_gen_or_i32(t0, t0, t1); |
1365 |
|
1366 |
tcg_gen_shri_i32(t1, arg, 24);
|
1367 |
tcg_gen_or_i32(ret, t0, t1); |
1368 |
tcg_temp_free_i32(t0); |
1369 |
tcg_temp_free_i32(t1); |
1370 |
#endif
|
1371 |
} |
1372 |
|
1373 |
#if TCG_TARGET_REG_BITS == 32 |
1374 |
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1375 |
{ |
1376 |
tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1377 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1378 |
} |
1379 |
|
1380 |
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1381 |
{ |
1382 |
tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1383 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1384 |
} |
1385 |
|
1386 |
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1387 |
{ |
1388 |
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1389 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1390 |
} |
1391 |
|
1392 |
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1393 |
{ |
1394 |
tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1395 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1396 |
} |
1397 |
|
1398 |
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1399 |
{ |
1400 |
tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1401 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1402 |
} |
1403 |
|
1404 |
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1405 |
{ |
1406 |
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1407 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1408 |
} |
1409 |
|
1410 |
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
1411 |
{ |
1412 |
tcg_gen_mov_i32(ret, TCGV_LOW(arg)); |
1413 |
} |
1414 |
|
1415 |
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1416 |
{ |
1417 |
tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1418 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1419 |
} |
1420 |
|
1421 |
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1422 |
{ |
1423 |
tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1424 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1425 |
} |
1426 |
|
1427 |
/* Note: we assume the six high bytes are set to zero */
|
1428 |
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
1429 |
{ |
1430 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
1431 |
tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1432 |
} |
1433 |
|
1434 |
/* Note: we assume the four high bytes are set to zero */
|
1435 |
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
1436 |
{ |
1437 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
1438 |
tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1439 |
} |
1440 |
|
1441 |
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
1442 |
{ |
1443 |
TCGv_i32 t0, t1; |
1444 |
t0 = tcg_temp_new_i32(); |
1445 |
t1 = tcg_temp_new_i32(); |
1446 |
|
1447 |
tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); |
1448 |
tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); |
1449 |
tcg_gen_mov_i32(TCGV_LOW(ret), t1); |
1450 |
tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
1451 |
tcg_temp_free_i32(t0); |
1452 |
tcg_temp_free_i32(t1); |
1453 |
} |
1454 |
#else
|
1455 |
|
1456 |
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1457 |
{ |
1458 |
#ifdef TCG_TARGET_HAS_ext8s_i64
|
1459 |
tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg); |
1460 |
#else
|
1461 |
tcg_gen_shli_i64(ret, arg, 56);
|
1462 |
tcg_gen_sari_i64(ret, ret, 56);
|
1463 |
#endif
|
1464 |
} |
1465 |
|
1466 |
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1467 |
{ |
1468 |
#ifdef TCG_TARGET_HAS_ext16s_i64
|
1469 |
tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg); |
1470 |
#else
|
1471 |
tcg_gen_shli_i64(ret, arg, 48);
|
1472 |
tcg_gen_sari_i64(ret, ret, 48);
|
1473 |
#endif
|
1474 |
} |
1475 |
|
1476 |
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1477 |
{ |
1478 |
#ifdef TCG_TARGET_HAS_ext32s_i64
|
1479 |
tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg); |
1480 |
#else
|
1481 |
tcg_gen_shli_i64(ret, arg, 32);
|
1482 |
tcg_gen_sari_i64(ret, ret, 32);
|
1483 |
#endif
|
1484 |
} |
1485 |
|
1486 |
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1487 |
{ |
1488 |
#ifdef TCG_TARGET_HAS_ext8u_i64
|
1489 |
tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg); |
1490 |
#else
|
1491 |
tcg_gen_andi_i64(ret, arg, 0xffu);
|
1492 |
#endif
|
1493 |
} |
1494 |
|
1495 |
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1496 |
{ |
1497 |
#ifdef TCG_TARGET_HAS_ext16u_i64
|
1498 |
tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg); |
1499 |
#else
|
1500 |
tcg_gen_andi_i64(ret, arg, 0xffffu);
|
1501 |
#endif
|
1502 |
} |
1503 |
|
1504 |
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1505 |
{ |
1506 |
#ifdef TCG_TARGET_HAS_ext32u_i64
|
1507 |
tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg); |
1508 |
#else
|
1509 |
tcg_gen_andi_i64(ret, arg, 0xffffffffu);
|
1510 |
#endif
|
1511 |
} |
1512 |
|
1513 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1514 |
registers. This will probably break MIPS64 targets. */
|
1515 |
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
1516 |
{ |
1517 |
tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); |
1518 |
} |
1519 |
|
1520 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1521 |
registers */
|
1522 |
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1523 |
{ |
1524 |
tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
1525 |
} |
1526 |
|
1527 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1528 |
registers */
|
1529 |
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1530 |
{ |
1531 |
tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
1532 |
} |
1533 |
|
1534 |
/* Note: we assume the six high bytes are set to zero */
|
1535 |
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
1536 |
{ |
1537 |
#ifdef TCG_TARGET_HAS_bswap16_i64
|
1538 |
tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg); |
1539 |
#else
|
1540 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1541 |
|
1542 |
tcg_gen_ext8u_i64(t0, arg); |
1543 |
tcg_gen_shli_i64(t0, t0, 8);
|
1544 |
tcg_gen_shri_i64(ret, arg, 8);
|
1545 |
tcg_gen_or_i64(ret, ret, t0); |
1546 |
tcg_temp_free_i64(t0); |
1547 |
#endif
|
1548 |
} |
1549 |
|
1550 |
/* Note: we assume the four high bytes are set to zero */
|
1551 |
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
1552 |
{ |
1553 |
#ifdef TCG_TARGET_HAS_bswap32_i64
|
1554 |
tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); |
1555 |
#else
|
1556 |
TCGv_i64 t0, t1; |
1557 |
t0 = tcg_temp_new_i64(); |
1558 |
t1 = tcg_temp_new_i64(); |
1559 |
|
1560 |
tcg_gen_shli_i64(t0, arg, 24);
|
1561 |
tcg_gen_ext32u_i64(t0, t0); |
1562 |
|
1563 |
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
1564 |
tcg_gen_shli_i64(t1, t1, 8);
|
1565 |
tcg_gen_or_i64(t0, t0, t1); |
1566 |
|
1567 |
tcg_gen_shri_i64(t1, arg, 8);
|
1568 |
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
1569 |
tcg_gen_or_i64(t0, t0, t1); |
1570 |
|
1571 |
tcg_gen_shri_i64(t1, arg, 24);
|
1572 |
tcg_gen_or_i64(ret, t0, t1); |
1573 |
tcg_temp_free_i64(t0); |
1574 |
tcg_temp_free_i64(t1); |
1575 |
#endif
|
1576 |
} |
1577 |
|
1578 |
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
1579 |
{ |
1580 |
#ifdef TCG_TARGET_HAS_bswap64_i64
|
1581 |
tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); |
1582 |
#else
|
1583 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1584 |
TCGv_i64 t1 = tcg_temp_new_i64(); |
1585 |
|
1586 |
tcg_gen_shli_i64(t0, arg, 56);
|
1587 |
|
1588 |
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
1589 |
tcg_gen_shli_i64(t1, t1, 40);
|
1590 |
tcg_gen_or_i64(t0, t0, t1); |
1591 |
|
1592 |
tcg_gen_andi_i64(t1, arg, 0x00ff0000);
|
1593 |
tcg_gen_shli_i64(t1, t1, 24);
|
1594 |
tcg_gen_or_i64(t0, t0, t1); |
1595 |
|
1596 |
tcg_gen_andi_i64(t1, arg, 0xff000000);
|
1597 |
tcg_gen_shli_i64(t1, t1, 8);
|
1598 |
tcg_gen_or_i64(t0, t0, t1); |
1599 |
|
1600 |
tcg_gen_shri_i64(t1, arg, 8);
|
1601 |
tcg_gen_andi_i64(t1, t1, 0xff000000);
|
1602 |
tcg_gen_or_i64(t0, t0, t1); |
1603 |
|
1604 |
tcg_gen_shri_i64(t1, arg, 24);
|
1605 |
tcg_gen_andi_i64(t1, t1, 0x00ff0000);
|
1606 |
tcg_gen_or_i64(t0, t0, t1); |
1607 |
|
1608 |
tcg_gen_shri_i64(t1, arg, 40);
|
1609 |
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
1610 |
tcg_gen_or_i64(t0, t0, t1); |
1611 |
|
1612 |
tcg_gen_shri_i64(t1, arg, 56);
|
1613 |
tcg_gen_or_i64(ret, t0, t1); |
1614 |
tcg_temp_free_i64(t0); |
1615 |
tcg_temp_free_i64(t1); |
1616 |
#endif
|
1617 |
} |
1618 |
|
1619 |
#endif
|
1620 |
|
1621 |
static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
1622 |
{ |
1623 |
#ifdef TCG_TARGET_HAS_neg_i32
|
1624 |
tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
1625 |
#else
|
1626 |
TCGv_i32 t0 = tcg_const_i32(0);
|
1627 |
tcg_gen_sub_i32(ret, t0, arg); |
1628 |
tcg_temp_free_i32(t0); |
1629 |
#endif
|
1630 |
} |
1631 |
|
1632 |
static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
1633 |
{ |
1634 |
#ifdef TCG_TARGET_HAS_neg_i64
|
1635 |
tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
1636 |
#else
|
1637 |
TCGv_i64 t0 = tcg_const_i64(0);
|
1638 |
tcg_gen_sub_i64(ret, t0, arg); |
1639 |
tcg_temp_free_i64(t0); |
1640 |
#endif
|
1641 |
} |
1642 |
|
1643 |
static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
1644 |
{ |
1645 |
#ifdef TCG_TARGET_HAS_not_i32
|
1646 |
tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); |
1647 |
#else
|
1648 |
tcg_gen_xori_i32(ret, arg, -1);
|
1649 |
#endif
|
1650 |
} |
1651 |
|
1652 |
static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) |
1653 |
{ |
1654 |
#ifdef TCG_TARGET_HAS_not_i64
|
1655 |
tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); |
1656 |
#else
|
1657 |
tcg_gen_xori_i64(ret, arg, -1);
|
1658 |
#endif
|
1659 |
} |
1660 |
|
1661 |
static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
1662 |
{ |
1663 |
tcg_gen_op1_i32(INDEX_op_discard, arg); |
1664 |
} |
1665 |
|
1666 |
#if TCG_TARGET_REG_BITS == 32 |
1667 |
static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
1668 |
{ |
1669 |
tcg_gen_discard_i32(TCGV_LOW(arg)); |
1670 |
tcg_gen_discard_i32(TCGV_HIGH(arg)); |
1671 |
} |
1672 |
#else
|
1673 |
static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
1674 |
{ |
1675 |
tcg_gen_op1_i64(INDEX_op_discard, arg); |
1676 |
} |
1677 |
#endif
|
1678 |
|
1679 |
static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) |
1680 |
{ |
1681 |
#if TCG_TARGET_REG_BITS == 32 |
1682 |
tcg_gen_mov_i32(TCGV_LOW(dest), low); |
1683 |
tcg_gen_mov_i32(TCGV_HIGH(dest), high); |
1684 |
#else
|
1685 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
1686 |
/* This extension is only needed for type correctness.
|
1687 |
We may be able to do better given target specific information. */
|
1688 |
tcg_gen_extu_i32_i64(tmp, high); |
1689 |
tcg_gen_shli_i64(tmp, tmp, 32);
|
1690 |
tcg_gen_extu_i32_i64(dest, low); |
1691 |
tcg_gen_or_i64(dest, dest, tmp); |
1692 |
tcg_temp_free_i64(tmp); |
1693 |
#endif
|
1694 |
} |
1695 |
|
1696 |
static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high) |
1697 |
{ |
1698 |
#if TCG_TARGET_REG_BITS == 32 |
1699 |
tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high)); |
1700 |
#else
|
1701 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
1702 |
tcg_gen_ext32u_i64(dest, low); |
1703 |
tcg_gen_shli_i64(tmp, high, 32);
|
1704 |
tcg_gen_or_i64(dest, dest, tmp); |
1705 |
tcg_temp_free_i64(tmp); |
1706 |
#endif
|
1707 |
} |
1708 |
|
1709 |
static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1710 |
{ |
1711 |
#ifdef TCG_TARGET_HAS_andc_i32
|
1712 |
tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); |
1713 |
#else
|
1714 |
TCGv_i32 t0; |
1715 |
t0 = tcg_temp_new_i32(); |
1716 |
tcg_gen_not_i32(t0, arg2); |
1717 |
tcg_gen_and_i32(ret, arg1, t0); |
1718 |
tcg_temp_free_i32(t0); |
1719 |
#endif
|
1720 |
} |
1721 |
|
1722 |
static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1723 |
{ |
1724 |
#ifdef TCG_TARGET_HAS_andc_i64
|
1725 |
tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); |
1726 |
#elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32 |
1727 |
tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1728 |
tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1729 |
#else
|
1730 |
TCGv_i64 t0; |
1731 |
t0 = tcg_temp_new_i64(); |
1732 |
tcg_gen_not_i64(t0, arg2); |
1733 |
tcg_gen_and_i64(ret, arg1, t0); |
1734 |
tcg_temp_free_i64(t0); |
1735 |
#endif
|
1736 |
} |
1737 |
|
1738 |
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1739 |
{ |
1740 |
tcg_gen_xor_i32(ret, arg1, arg2); |
1741 |
tcg_gen_not_i32(ret, ret); |
1742 |
} |
1743 |
|
1744 |
static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1745 |
{ |
1746 |
tcg_gen_xor_i64(ret, arg1, arg2); |
1747 |
tcg_gen_not_i64(ret, ret); |
1748 |
} |
1749 |
|
1750 |
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1751 |
{ |
1752 |
tcg_gen_and_i32(ret, arg1, arg2); |
1753 |
tcg_gen_not_i32(ret, ret); |
1754 |
} |
1755 |
|
1756 |
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1757 |
{ |
1758 |
tcg_gen_and_i64(ret, arg1, arg2); |
1759 |
tcg_gen_not_i64(ret, ret); |
1760 |
} |
1761 |
|
1762 |
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1763 |
{ |
1764 |
tcg_gen_or_i32(ret, arg1, arg2); |
1765 |
tcg_gen_not_i32(ret, ret); |
1766 |
} |
1767 |
|
1768 |
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1769 |
{ |
1770 |
tcg_gen_or_i64(ret, arg1, arg2); |
1771 |
tcg_gen_not_i64(ret, ret); |
1772 |
} |
1773 |
|
1774 |
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1775 |
{ |
1776 |
#ifdef TCG_TARGET_HAS_orc_i32
|
1777 |
tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2); |
1778 |
#else
|
1779 |
TCGv_i32 t0; |
1780 |
t0 = tcg_temp_new_i32(); |
1781 |
tcg_gen_not_i32(t0, arg2); |
1782 |
tcg_gen_or_i32(ret, arg1, t0); |
1783 |
tcg_temp_free_i32(t0); |
1784 |
#endif
|
1785 |
} |
1786 |
|
1787 |
static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1788 |
{ |
1789 |
#ifdef TCG_TARGET_HAS_orc_i64
|
1790 |
tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2); |
1791 |
#elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32 |
1792 |
tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1793 |
tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1794 |
#else
|
1795 |
TCGv_i64 t0; |
1796 |
t0 = tcg_temp_new_i64(); |
1797 |
tcg_gen_not_i64(t0, arg2); |
1798 |
tcg_gen_or_i64(ret, arg1, t0); |
1799 |
tcg_temp_free_i64(t0); |
1800 |
#endif
|
1801 |
} |
1802 |
|
1803 |
static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1804 |
{ |
1805 |
#ifdef TCG_TARGET_HAS_rot_i32
|
1806 |
tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); |
1807 |
#else
|
1808 |
TCGv_i32 t0, t1; |
1809 |
|
1810 |
t0 = tcg_temp_new_i32(); |
1811 |
t1 = tcg_temp_new_i32(); |
1812 |
tcg_gen_shl_i32(t0, arg1, arg2); |
1813 |
tcg_gen_subfi_i32(t1, 32, arg2);
|
1814 |
tcg_gen_shr_i32(t1, arg1, t1); |
1815 |
tcg_gen_or_i32(ret, t0, t1); |
1816 |
tcg_temp_free_i32(t0); |
1817 |
tcg_temp_free_i32(t1); |
1818 |
#endif
|
1819 |
} |
1820 |
|
1821 |
static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1822 |
{ |
1823 |
#ifdef TCG_TARGET_HAS_rot_i64
|
1824 |
tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); |
1825 |
#else
|
1826 |
TCGv_i64 t0, t1; |
1827 |
|
1828 |
t0 = tcg_temp_new_i64(); |
1829 |
t1 = tcg_temp_new_i64(); |
1830 |
tcg_gen_shl_i64(t0, arg1, arg2); |
1831 |
tcg_gen_subfi_i64(t1, 64, arg2);
|
1832 |
tcg_gen_shr_i64(t1, arg1, t1); |
1833 |
tcg_gen_or_i64(ret, t0, t1); |
1834 |
tcg_temp_free_i64(t0); |
1835 |
tcg_temp_free_i64(t1); |
1836 |
#endif
|
1837 |
} |
1838 |
|
1839 |
static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
1840 |
{ |
1841 |
/* some cases can be optimized here */
|
1842 |
if (arg2 == 0) { |
1843 |
tcg_gen_mov_i32(ret, arg1); |
1844 |
} else {
|
1845 |
#ifdef TCG_TARGET_HAS_rot_i32
|
1846 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
1847 |
tcg_gen_rotl_i32(ret, arg1, t0); |
1848 |
tcg_temp_free_i32(t0); |
1849 |
#else
|
1850 |
TCGv_i32 t0, t1; |
1851 |
t0 = tcg_temp_new_i32(); |
1852 |
t1 = tcg_temp_new_i32(); |
1853 |
tcg_gen_shli_i32(t0, arg1, arg2); |
1854 |
tcg_gen_shri_i32(t1, arg1, 32 - arg2);
|
1855 |
tcg_gen_or_i32(ret, t0, t1); |
1856 |
tcg_temp_free_i32(t0); |
1857 |
tcg_temp_free_i32(t1); |
1858 |
#endif
|
1859 |
} |
1860 |
} |
1861 |
|
1862 |
static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1863 |
{ |
1864 |
/* some cases can be optimized here */
|
1865 |
if (arg2 == 0) { |
1866 |
tcg_gen_mov_i64(ret, arg1); |
1867 |
} else {
|
1868 |
#ifdef TCG_TARGET_HAS_rot_i64
|
1869 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1870 |
tcg_gen_rotl_i64(ret, arg1, t0); |
1871 |
tcg_temp_free_i64(t0); |
1872 |
#else
|
1873 |
TCGv_i64 t0, t1; |
1874 |
t0 = tcg_temp_new_i64(); |
1875 |
t1 = tcg_temp_new_i64(); |
1876 |
tcg_gen_shli_i64(t0, arg1, arg2); |
1877 |
tcg_gen_shri_i64(t1, arg1, 64 - arg2);
|
1878 |
tcg_gen_or_i64(ret, t0, t1); |
1879 |
tcg_temp_free_i64(t0); |
1880 |
tcg_temp_free_i64(t1); |
1881 |
#endif
|
1882 |
} |
1883 |
} |
1884 |
|
1885 |
static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1886 |
{ |
1887 |
#ifdef TCG_TARGET_HAS_rot_i32
|
1888 |
tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); |
1889 |
#else
|
1890 |
TCGv_i32 t0, t1; |
1891 |
|
1892 |
t0 = tcg_temp_new_i32(); |
1893 |
t1 = tcg_temp_new_i32(); |
1894 |
tcg_gen_shr_i32(t0, arg1, arg2); |
1895 |
tcg_gen_subfi_i32(t1, 32, arg2);
|
1896 |
tcg_gen_shl_i32(t1, arg1, t1); |
1897 |
tcg_gen_or_i32(ret, t0, t1); |
1898 |
tcg_temp_free_i32(t0); |
1899 |
tcg_temp_free_i32(t1); |
1900 |
#endif
|
1901 |
} |
1902 |
|
1903 |
static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1904 |
{ |
1905 |
#ifdef TCG_TARGET_HAS_rot_i64
|
1906 |
tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); |
1907 |
#else
|
1908 |
TCGv_i64 t0, t1; |
1909 |
|
1910 |
t0 = tcg_temp_new_i64(); |
1911 |
t1 = tcg_temp_new_i64(); |
1912 |
tcg_gen_shr_i64(t0, arg1, arg2); |
1913 |
tcg_gen_subfi_i64(t1, 64, arg2);
|
1914 |
tcg_gen_shl_i64(t1, arg1, t1); |
1915 |
tcg_gen_or_i64(ret, t0, t1); |
1916 |
tcg_temp_free_i64(t0); |
1917 |
tcg_temp_free_i64(t1); |
1918 |
#endif
|
1919 |
} |
1920 |
|
1921 |
static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
1922 |
{ |
1923 |
/* some cases can be optimized here */
|
1924 |
if (arg2 == 0) { |
1925 |
tcg_gen_mov_i32(ret, arg1); |
1926 |
} else {
|
1927 |
tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
|
1928 |
} |
1929 |
} |
1930 |
|
1931 |
static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1932 |
{ |
1933 |
/* some cases can be optimized here */
|
1934 |
if (arg2 == 0) { |
1935 |
tcg_gen_mov_i64(ret, arg1); |
1936 |
} else {
|
1937 |
tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
|
1938 |
} |
1939 |
} |
1940 |
|
1941 |
/***************************************/
|
1942 |
/* QEMU specific operations. Their type depend on the QEMU CPU
|
1943 |
type. */
|
1944 |
#ifndef TARGET_LONG_BITS
|
1945 |
#error must include QEMU headers
|
1946 |
#endif
|
1947 |
|
1948 |
#if TARGET_LONG_BITS == 32 |
1949 |
#define TCGv TCGv_i32
|
1950 |
#define tcg_temp_new() tcg_temp_new_i32()
|
1951 |
#define tcg_global_reg_new tcg_global_reg_new_i32
|
1952 |
#define tcg_global_mem_new tcg_global_mem_new_i32
|
1953 |
#define tcg_temp_local_new() tcg_temp_local_new_i32()
|
1954 |
#define tcg_temp_free tcg_temp_free_i32
|
1955 |
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
|
1956 |
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
|
1957 |
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
|
1958 |
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
|
1959 |
#else
|
1960 |
#define TCGv TCGv_i64
|
1961 |
#define tcg_temp_new() tcg_temp_new_i64()
|
1962 |
#define tcg_global_reg_new tcg_global_reg_new_i64
|
1963 |
#define tcg_global_mem_new tcg_global_mem_new_i64
|
1964 |
#define tcg_temp_local_new() tcg_temp_local_new_i64()
|
1965 |
#define tcg_temp_free tcg_temp_free_i64
|
1966 |
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
|
1967 |
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
|
1968 |
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
|
1969 |
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
|
1970 |
#endif
|
1971 |
|
1972 |
/* debug info: write the PC of the corresponding QEMU CPU instruction */
|
1973 |
static inline void tcg_gen_debug_insn_start(uint64_t pc) |
1974 |
{ |
1975 |
/* XXX: must really use a 32 bit size for TCGArg in all cases */
|
1976 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
1977 |
tcg_gen_op2ii(INDEX_op_debug_insn_start, |
1978 |
(uint32_t)(pc), (uint32_t)(pc >> 32));
|
1979 |
#else
|
1980 |
tcg_gen_op1i(INDEX_op_debug_insn_start, pc); |
1981 |
#endif
|
1982 |
} |
1983 |
|
1984 |
static inline void tcg_gen_exit_tb(tcg_target_long val) |
1985 |
{ |
1986 |
tcg_gen_op1i(INDEX_op_exit_tb, val); |
1987 |
} |
1988 |
|
1989 |
static inline void tcg_gen_goto_tb(int idx) |
1990 |
{ |
1991 |
tcg_gen_op1i(INDEX_op_goto_tb, idx); |
1992 |
} |
1993 |
|
1994 |
#if TCG_TARGET_REG_BITS == 32 |
1995 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
1996 |
{ |
1997 |
#if TARGET_LONG_BITS == 32 |
1998 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
1999 |
#else
|
2000 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr), |
2001 |
TCGV_HIGH(addr), mem_index); |
2002 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
2003 |
#endif
|
2004 |
} |
2005 |
|
2006 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
2007 |
{ |
2008 |
#if TARGET_LONG_BITS == 32 |
2009 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
2010 |
#else
|
2011 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr), |
2012 |
TCGV_HIGH(addr), mem_index); |
2013 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
2014 |
#endif
|
2015 |
} |
2016 |
|
2017 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
2018 |
{ |
2019 |
#if TARGET_LONG_BITS == 32 |
2020 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
2021 |
#else
|
2022 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr), |
2023 |
TCGV_HIGH(addr), mem_index); |
2024 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
2025 |
#endif
|
2026 |
} |
2027 |
|
2028 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
2029 |
{ |
2030 |
#if TARGET_LONG_BITS == 32 |
2031 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
2032 |
#else
|
2033 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr), |
2034 |
TCGV_HIGH(addr), mem_index); |
2035 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
2036 |
#endif
|
2037 |
} |
2038 |
|
2039 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
2040 |
{ |
2041 |
#if TARGET_LONG_BITS == 32 |
2042 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
2043 |
#else
|
2044 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
2045 |
TCGV_HIGH(addr), mem_index); |
2046 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
2047 |
#endif
|
2048 |
} |
2049 |
|
2050 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
2051 |
{ |
2052 |
#if TARGET_LONG_BITS == 32 |
2053 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
2054 |
#else
|
2055 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
2056 |
TCGV_HIGH(addr), mem_index); |
2057 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
2058 |
#endif
|
2059 |
} |
2060 |
|
2061 |
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
2062 |
{ |
2063 |
#if TARGET_LONG_BITS == 32 |
2064 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index); |
2065 |
#else
|
2066 |
tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), |
2067 |
TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
2068 |
#endif
|
2069 |
} |
2070 |
|
2071 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
2072 |
{ |
2073 |
#if TARGET_LONG_BITS == 32 |
2074 |
tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index); |
2075 |
#else
|
2076 |
tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr), |
2077 |
TCGV_HIGH(addr), mem_index); |
2078 |
#endif
|
2079 |
} |
2080 |
|
2081 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
2082 |
{ |
2083 |
#if TARGET_LONG_BITS == 32 |
2084 |
tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index); |
2085 |
#else
|
2086 |
tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr), |
2087 |
TCGV_HIGH(addr), mem_index); |
2088 |
#endif
|
2089 |
} |
2090 |
|
2091 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
2092 |
{ |
2093 |
#if TARGET_LONG_BITS == 32 |
2094 |
tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index); |
2095 |
#else
|
2096 |
tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr), |
2097 |
TCGV_HIGH(addr), mem_index); |
2098 |
#endif
|
2099 |
} |
2100 |
|
2101 |
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
2102 |
{ |
2103 |
#if TARGET_LONG_BITS == 32 |
2104 |
tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr, |
2105 |
mem_index); |
2106 |
#else
|
2107 |
tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), |
2108 |
TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
2109 |
#endif
|
2110 |
} |
2111 |
|
2112 |
#define tcg_gen_ld_ptr tcg_gen_ld_i32
|
2113 |
#define tcg_gen_discard_ptr tcg_gen_discard_i32
|
2114 |
|
2115 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
2116 |
|
2117 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
2118 |
{ |
2119 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
2120 |
} |
2121 |
|
2122 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
2123 |
{ |
2124 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
2125 |
} |
2126 |
|
2127 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
2128 |
{ |
2129 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
2130 |
} |
2131 |
|
2132 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
2133 |
{ |
2134 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
2135 |
} |
2136 |
|
2137 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
2138 |
{ |
2139 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
2140 |
} |
2141 |
|
2142 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
2143 |
{ |
2144 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
2145 |
} |
2146 |
|
2147 |
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
2148 |
{ |
2149 |
tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index); |
2150 |
} |
2151 |
|
2152 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
2153 |
{ |
2154 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index); |
2155 |
} |
2156 |
|
2157 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
2158 |
{ |
2159 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index); |
2160 |
} |
2161 |
|
2162 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
2163 |
{ |
2164 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index); |
2165 |
} |
2166 |
|
2167 |
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
2168 |
{ |
2169 |
tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index); |
2170 |
} |
2171 |
|
2172 |
#define tcg_gen_ld_ptr tcg_gen_ld_i64
|
2173 |
#define tcg_gen_discard_ptr tcg_gen_discard_i64
|
2174 |
|
2175 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |
2176 |
|
2177 |
#if TARGET_LONG_BITS == 64 |
2178 |
#define TCG_TYPE_TL TCG_TYPE_I64
|
2179 |
#define tcg_gen_movi_tl tcg_gen_movi_i64
|
2180 |
#define tcg_gen_mov_tl tcg_gen_mov_i64
|
2181 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
|
2182 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
|
2183 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
|
2184 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
|
2185 |
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
|
2186 |
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
|
2187 |
#define tcg_gen_ld_tl tcg_gen_ld_i64
|
2188 |
#define tcg_gen_st8_tl tcg_gen_st8_i64
|
2189 |
#define tcg_gen_st16_tl tcg_gen_st16_i64
|
2190 |
#define tcg_gen_st32_tl tcg_gen_st32_i64
|
2191 |
#define tcg_gen_st_tl tcg_gen_st_i64
|
2192 |
#define tcg_gen_add_tl tcg_gen_add_i64
|
2193 |
#define tcg_gen_addi_tl tcg_gen_addi_i64
|
2194 |
#define tcg_gen_sub_tl tcg_gen_sub_i64
|
2195 |
#define tcg_gen_neg_tl tcg_gen_neg_i64
|
2196 |
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
|
2197 |
#define tcg_gen_subi_tl tcg_gen_subi_i64
|
2198 |
#define tcg_gen_and_tl tcg_gen_and_i64
|
2199 |
#define tcg_gen_andi_tl tcg_gen_andi_i64
|
2200 |
#define tcg_gen_or_tl tcg_gen_or_i64
|
2201 |
#define tcg_gen_ori_tl tcg_gen_ori_i64
|
2202 |
#define tcg_gen_xor_tl tcg_gen_xor_i64
|
2203 |
#define tcg_gen_xori_tl tcg_gen_xori_i64
|
2204 |
#define tcg_gen_not_tl tcg_gen_not_i64
|
2205 |
#define tcg_gen_shl_tl tcg_gen_shl_i64
|
2206 |
#define tcg_gen_shli_tl tcg_gen_shli_i64
|
2207 |
#define tcg_gen_shr_tl tcg_gen_shr_i64
|
2208 |
#define tcg_gen_shri_tl tcg_gen_shri_i64
|
2209 |
#define tcg_gen_sar_tl tcg_gen_sar_i64
|
2210 |
#define tcg_gen_sari_tl tcg_gen_sari_i64
|
2211 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
|
2212 |
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
|
2213 |
#define tcg_gen_setcond_tl tcg_gen_setcond_i64
|
2214 |
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
|
2215 |
#define tcg_gen_mul_tl tcg_gen_mul_i64
|
2216 |
#define tcg_gen_muli_tl tcg_gen_muli_i64
|
2217 |
#define tcg_gen_div_tl tcg_gen_div_i64
|
2218 |
#define tcg_gen_rem_tl tcg_gen_rem_i64
|
2219 |
#define tcg_gen_divu_tl tcg_gen_divu_i64
|
2220 |
#define tcg_gen_remu_tl tcg_gen_remu_i64
|
2221 |
#define tcg_gen_discard_tl tcg_gen_discard_i64
|
2222 |
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
|
2223 |
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
|
2224 |
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
|
2225 |
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
|
2226 |
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
|
2227 |
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
|
2228 |
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
|
2229 |
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
|
2230 |
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
|
2231 |
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
|
2232 |
#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
|
2233 |
#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
|
2234 |
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
|
2235 |
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
|
2236 |
#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
|
2237 |
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
|
2238 |
#define tcg_gen_andc_tl tcg_gen_andc_i64
|
2239 |
#define tcg_gen_eqv_tl tcg_gen_eqv_i64
|
2240 |
#define tcg_gen_nand_tl tcg_gen_nand_i64
|
2241 |
#define tcg_gen_nor_tl tcg_gen_nor_i64
|
2242 |
#define tcg_gen_orc_tl tcg_gen_orc_i64
|
2243 |
#define tcg_gen_rotl_tl tcg_gen_rotl_i64
|
2244 |
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
|
2245 |
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
|
2246 |
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
|
2247 |
#define tcg_const_tl tcg_const_i64
|
2248 |
#define tcg_const_local_tl tcg_const_local_i64
|
2249 |
#else
|
2250 |
#define TCG_TYPE_TL TCG_TYPE_I32
|
2251 |
#define tcg_gen_movi_tl tcg_gen_movi_i32
|
2252 |
#define tcg_gen_mov_tl tcg_gen_mov_i32
|
2253 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
|
2254 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
|
2255 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
|
2256 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
|
2257 |
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
|
2258 |
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
|
2259 |
#define tcg_gen_ld_tl tcg_gen_ld_i32
|
2260 |
#define tcg_gen_st8_tl tcg_gen_st8_i32
|
2261 |
#define tcg_gen_st16_tl tcg_gen_st16_i32
|
2262 |
#define tcg_gen_st32_tl tcg_gen_st_i32
|
2263 |
#define tcg_gen_st_tl tcg_gen_st_i32
|
2264 |
#define tcg_gen_add_tl tcg_gen_add_i32
|
2265 |
#define tcg_gen_addi_tl tcg_gen_addi_i32
|
2266 |
#define tcg_gen_sub_tl tcg_gen_sub_i32
|
2267 |
#define tcg_gen_neg_tl tcg_gen_neg_i32
|
2268 |
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
|
2269 |
#define tcg_gen_subi_tl tcg_gen_subi_i32
|
2270 |
#define tcg_gen_and_tl tcg_gen_and_i32
|
2271 |
#define tcg_gen_andi_tl tcg_gen_andi_i32
|
2272 |
#define tcg_gen_or_tl tcg_gen_or_i32
|
2273 |
#define tcg_gen_ori_tl tcg_gen_ori_i32
|
2274 |
#define tcg_gen_xor_tl tcg_gen_xor_i32
|
2275 |
#define tcg_gen_xori_tl tcg_gen_xori_i32
|
2276 |
#define tcg_gen_not_tl tcg_gen_not_i32
|
2277 |
#define tcg_gen_shl_tl tcg_gen_shl_i32
|
2278 |
#define tcg_gen_shli_tl tcg_gen_shli_i32
|
2279 |
#define tcg_gen_shr_tl tcg_gen_shr_i32
|
2280 |
#define tcg_gen_shri_tl tcg_gen_shri_i32
|
2281 |
#define tcg_gen_sar_tl tcg_gen_sar_i32
|
2282 |
#define tcg_gen_sari_tl tcg_gen_sari_i32
|
2283 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
|
2284 |
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
|
2285 |
#define tcg_gen_setcond_tl tcg_gen_setcond_i32
|
2286 |
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
|
2287 |
#define tcg_gen_mul_tl tcg_gen_mul_i32
|
2288 |
#define tcg_gen_muli_tl tcg_gen_muli_i32
|
2289 |
#define tcg_gen_div_tl tcg_gen_div_i32
|
2290 |
#define tcg_gen_rem_tl tcg_gen_rem_i32
|
2291 |
#define tcg_gen_divu_tl tcg_gen_divu_i32
|
2292 |
#define tcg_gen_remu_tl tcg_gen_remu_i32
|
2293 |
#define tcg_gen_discard_tl tcg_gen_discard_i32
|
2294 |
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
|
2295 |
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
|
2296 |
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
|
2297 |
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
|
2298 |
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
|
2299 |
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
|
2300 |
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
|
2301 |
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
|
2302 |
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
|
2303 |
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
|
2304 |
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
|
2305 |
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
|
2306 |
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
|
2307 |
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
|
2308 |
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
|
2309 |
#define tcg_gen_andc_tl tcg_gen_andc_i32
|
2310 |
#define tcg_gen_eqv_tl tcg_gen_eqv_i32
|
2311 |
#define tcg_gen_nand_tl tcg_gen_nand_i32
|
2312 |
#define tcg_gen_nor_tl tcg_gen_nor_i32
|
2313 |
#define tcg_gen_orc_tl tcg_gen_orc_i32
|
2314 |
#define tcg_gen_rotl_tl tcg_gen_rotl_i32
|
2315 |
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
|
2316 |
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
|
2317 |
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
|
2318 |
#define tcg_const_tl tcg_const_i32
|
2319 |
#define tcg_const_local_tl tcg_const_local_i32
|
2320 |
#endif
|
2321 |
|
2322 |
#if TCG_TARGET_REG_BITS == 32 |
2323 |
#define tcg_gen_add_ptr tcg_gen_add_i32
|
2324 |
#define tcg_gen_addi_ptr tcg_gen_addi_i32
|
2325 |
#define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
|
2326 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
2327 |
#define tcg_gen_add_ptr tcg_gen_add_i64
|
2328 |
#define tcg_gen_addi_ptr tcg_gen_addi_i64
|
2329 |
#define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
|
2330 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |