Revision a9f49946 hw/pci.h

b/hw/pci.h
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#define PCI_CONFIG_HEADER_SIZE 0x40
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/* Size of the standard PCI config space */
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#define PCI_CONFIG_SPACE_SIZE 0x100
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/* Size of the standart PCIe config space: 4KB */
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#define PCIE_CONFIG_SPACE_SIZE  0x1000
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#define PCI_NUM_PINS 4 /* A-D */
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/* Bits in cap_present field. */
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enum {
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    QEMU_PCI_CAP_MSIX = 0x1,
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    QEMU_PCI_CAP_EXPRESS = 0x2,
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};
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struct PCIDevice {
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    DeviceState qdev;
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    /* PCI config space */
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    uint8_t config[PCI_CONFIG_SPACE_SIZE];
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    uint8_t *config;
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    /* Used to enable config checks on load. Note that writeable bits are
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     * never checked even if set in cmask. */
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    uint8_t cmask[PCI_CONFIG_SPACE_SIZE];
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    uint8_t *cmask;
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    /* Used to implement R/W bytes */
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    uint8_t wmask[PCI_CONFIG_SPACE_SIZE];
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    uint8_t *wmask;
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    /* Used to allocate config space for capabilities. */
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    uint8_t used[PCI_CONFIG_SPACE_SIZE];
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    uint8_t *used;
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    /* the following fields are read only */
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    PCIBus *bus;
......
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    PCIUnregisterFunc *exit;
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    PCIConfigReadFunc *config_read;
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    PCIConfigWriteFunc *config_write;
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    /* pcie stuff */
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    int is_express;   /* is this device pci express?
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                       * initialization code needs to know this before
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                       * each specific device initialization.
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                       */
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} PCIDeviceInfo;
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void pci_qdev_register(PCIDeviceInfo *info);
......
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PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
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PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
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static inline int pci_is_express(PCIDevice *d)
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{
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    return d->cap_present & QEMU_PCI_CAP_EXPRESS;
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}
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static inline uint32_t pci_config_size(PCIDevice *d)
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{
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    return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
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}
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/* lsi53c895a.c */
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#define LSI_MAX_DEVS 7
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