Statistics
| Branch: | Revision:

root / hw / pcie_host.c @ a9f49946

History | View | Annotate | Download (5.8 kB)

1
/*
2
 * pcie_host.c
3
 * utility functions for pci express host bridge.
4
 *
5
 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
6
 *                    VA Linux Systems Japan K.K.
7
 *
8
 * This program is free software; you can redistribute it and/or modify
9
 * it under the terms of the GNU General Public License as published by
10
 * the Free Software Foundation; either version 2 of the License, or
11
 * (at your option) any later version.
12

13
 * This program is distributed in the hope that it will be useful,
14
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
 * GNU General Public License for more details.
17

18
 * You should have received a copy of the GNU General Public License along
19
 * with this program; if not, write to the Free Software Foundation, Inc.,
20
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21
 */
22

    
23
#include "hw.h"
24
#include "pci.h"
25
#include "pcie_host.h"
26

    
27
/*
28
 * PCI express mmcfig address
29
 * bit 20 - 28: bus number
30
 * bit 15 - 19: device number
31
 * bit 12 - 14: function number
32
 * bit  0 - 11: offset in configuration space of a given device
33
 */
34
#define PCIE_MMCFG_SIZE_MAX             (1ULL << 28)
35
#define PCIE_MMCFG_SIZE_MIN             (1ULL << 20)
36
#define PCIE_MMCFG_BUS_BIT              20
37
#define PCIE_MMCFG_BUS_MASK             0x1ff
38
#define PCIE_MMCFG_DEVFN_BIT            12
39
#define PCIE_MMCFG_DEVFN_MASK           0xff
40
#define PCIE_MMCFG_CONFOFFSET_MASK      0xfff
41
#define PCIE_MMCFG_BUS(addr)            (((addr) >> PCIE_MMCFG_BUS_BIT) & \
42
                                         PCIE_MMCFG_BUS_MASK)
43
#define PCIE_MMCFG_DEVFN(addr)          (((addr) >> PCIE_MMCFG_DEVFN_BIT) & \
44
                                         PCIE_MMCFG_DEVFN_MASK)
45
#define PCIE_MMCFG_CONFOFFSET(addr)     ((addr) & PCIE_MMCFG_CONFOFFSET_MASK)
46

    
47

    
48
/* a helper function to get a PCIDevice for a given mmconfig address */
49
static inline PCIDevice *pcie_mmcfg_addr_to_dev(PCIBus *s, uint32_t mmcfg_addr)
50
{
51
    return pci_find_device(s, PCIE_MMCFG_BUS(mmcfg_addr),
52
                           PCI_SLOT(PCIE_MMCFG_DEVFN(mmcfg_addr)),
53
                           PCI_FUNC(PCIE_MMCFG_DEVFN(mmcfg_addr)));
54
}
55

    
56
static void pcie_mmcfg_data_write(PCIBus *s,
57
                                  uint32_t mmcfg_addr, uint32_t val, int len)
58
{
59
    PCIDevice *pci_dev = pcie_mmcfg_addr_to_dev(s, mmcfg_addr);
60

    
61
    if (!pci_dev)
62
        return;
63

    
64
    pci_dev->config_write(pci_dev,
65
                          PCIE_MMCFG_CONFOFFSET(mmcfg_addr), val, len);
66
}
67

    
68
static uint32_t pcie_mmcfg_data_read(PCIBus *s,
69
                                     uint32_t mmcfg_addr, int len)
70
{
71
    PCIDevice *pci_dev = pcie_mmcfg_addr_to_dev(s, mmcfg_addr);
72
    uint32_t val;
73

    
74
    if (!pci_dev) {
75
        switch(len) {
76
        case 1:
77
            val = 0xff;
78
            break;
79
        case 2:
80
            val = 0xffff;
81
            break;
82
        default:
83
        case 4:
84
            val = 0xffffffff;
85
            break;
86
        }
87
    } else {
88
        val = pci_dev->config_read(pci_dev,
89
                                   PCIE_MMCFG_CONFOFFSET(mmcfg_addr), len);
90
    }
91

    
92
    return val;
93
}
94

    
95
static void pcie_mmcfg_data_writeb(void *opaque,
96
                                   target_phys_addr_t addr, uint32_t value)
97
{
98
    PCIExpressHost *e = opaque;
99
    pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 1);
100
}
101

    
102
static void pcie_mmcfg_data_writew(void *opaque,
103
                                   target_phys_addr_t addr, uint32_t value)
104
{
105
    PCIExpressHost *e = opaque;
106
    pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 2);
107
}
108

    
109
static void pcie_mmcfg_data_writel(void *opaque,
110
                                   target_phys_addr_t addr, uint32_t value)
111
{
112
    PCIExpressHost *e = opaque;
113
    pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 4);
114
}
115

    
116
static uint32_t pcie_mmcfg_data_readb(void *opaque, target_phys_addr_t addr)
117
{
118
    PCIExpressHost *e = opaque;
119
    return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 1);
120
}
121

    
122
static uint32_t pcie_mmcfg_data_readw(void *opaque, target_phys_addr_t addr)
123
{
124
    PCIExpressHost *e = opaque;
125
    return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 2);
126
}
127

    
128
static uint32_t pcie_mmcfg_data_readl(void *opaque, target_phys_addr_t addr)
129
{
130
    PCIExpressHost *e = opaque;
131
    return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 4);
132
}
133

    
134

    
135
static CPUWriteMemoryFunc * const pcie_mmcfg_write[] =
136
{
137
    pcie_mmcfg_data_writeb,
138
    pcie_mmcfg_data_writew,
139
    pcie_mmcfg_data_writel,
140
};
141

    
142
static CPUReadMemoryFunc * const pcie_mmcfg_read[] =
143
{
144
    pcie_mmcfg_data_readb,
145
    pcie_mmcfg_data_readw,
146
    pcie_mmcfg_data_readl,
147
};
148

    
149
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
150
#define PCIE_BASE_ADDR_UNMAPPED  ((target_phys_addr_t)-1ULL)
151

    
152
int pcie_host_init(PCIExpressHost *e)
153
{
154
    e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
155
    e->mmio_index =
156
        cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e);
157
    if (e->mmio_index < 0) {
158
        return -1;
159
    }
160

    
161
    return 0;
162
}
163

    
164
void pcie_host_mmcfg_unmap(PCIExpressHost *e)
165
{
166
    if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
167
        cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED);
168
        e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
169
    }
170
}
171

    
172
void pcie_host_mmcfg_map(PCIExpressHost *e,
173
                         target_phys_addr_t addr, uint32_t size)
174
{
175
    assert(!(size & (size - 1)));       /* power of 2 */
176
    assert(size >= PCIE_MMCFG_SIZE_MIN);
177
    assert(size <= PCIE_MMCFG_SIZE_MAX);
178

    
179
    e->base_addr = addr;
180
    e->size = size;
181
    cpu_register_physical_memory(e->base_addr, e->size, e->mmio_index);
182
}
183

    
184
void pcie_host_mmcfg_update(PCIExpressHost *e,
185
                            int enable,
186
                            target_phys_addr_t addr, uint32_t size)
187
{
188
    pcie_host_mmcfg_unmap(e);
189
    if (enable) {
190
        pcie_host_mmcfg_map(e, addr, size);
191
    }
192
}