/ - Diff - qemu - Greek Research and Technology Network's projects

     #if 0
     /***********************************************/
     /* removable device additionnal commands */
     /* removable device additional commands */
     static int raw_is_inserted(BlockDriverState *bs)
+    {

     /* Call this macro to initialize only the internal variables for the
        disassembler.  Architecture dependent things such as byte order, or machine
        variant are not touched by this macro.  This makes things much easier for
        GDB which must initialize these things seperatly.  */
        GDB which must initialize these things separately.  */
     #define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
       (INFO).fprintf_func = (FPRINTF_FUNC), \

b/gdbstub.c
1248	1248	return 0;
1249	1249	}
1250	1250	#else
1251		static int gdb_chr_can_recieve(void *opaque)
	1251	static int gdb_chr_can_receive(void *opaque)
1252	1252	{
1253	1253	return 1;
1254	1254	}
1255	1255
1256		static void gdb_chr_recieve(void opaque, const uint8_t buf, int size)
	1256	static void gdb_chr_receive(void opaque, const uint8_t buf, int size)
1257	1257	{
1258	1258	GDBState *s = opaque;
1259	1259	int i;
...	...
1304	1304	}
1305	1305	s->env = first_cpu; /* XXX: allow to change CPU */
1306	1306	s->chr = chr;
1307		qemu_chr_add_handlers(chr, gdb_chr_can_recieve, gdb_chr_recieve,
	1307	qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
1308	1308	gdb_chr_event, s);
1309	1309	qemu_add_vm_stop_handler(gdb_vm_stopped, s);
1310	1310	return 0;

         I2C_START_RECV,
         I2C_START_SEND,
         I2C_FINISH,
         I2C_NACK /* Masker NACKed a recieve byte.  */
         I2C_NACK /* Masker NACKed a receive byte.  */
     };
     typedef struct i2c_slave i2c_slave;

             buf[1] = 0x80; /* removable */
             buf[2] = 0x00; /* ISO */
             buf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
             buf[4] = 31; /* additionnal length */
             buf[4] = 31; /* additional length */
             buf[5] = 0; /* reserved */
             buf[6] = 0; /* reserved */
             buf[7] = 0; /* reserved */

b/hw/pl011.c
176	176	}
177	177	}
178	178
179		static int pl011_can_recieve(void *opaque)
	179	static int pl011_can_receive(void *opaque)
180	180	{
181	181	pl011_state s = (pl011_state )opaque;
182	182
...	...
186	186	return s->read_count < 1;
187	187	}
188	188
189		static void pl011_recieve(void opaque, const uint8_t buf, int size)
	189	static void pl011_receive(void opaque, const uint8_t buf, int size)
190	190	{
191	191	pl011_state s = (pl011_state )opaque;
192	192	int slot;
...	...
241	241	s->cr = 0x300;
242	242	s->flags = 0x90;
243	243	if (chr){
244		qemu_chr_add_handlers(chr, pl011_can_recieve, pl011_recieve,
	244	qemu_chr_add_handlers(chr, pl011_can_receive, pl011_receive,
245	245	pl011_event, s);
246	246	}
247	247	/* ??? Save/restore. */

                 s->response[2] = RWORD(8);
                 s->response[3] = RWORD(12) & ~1;
+            }
             DPRINTF("Response recieved\n");
             DPRINTF("Response received\n");
             s->status |= PL181_STATUS_CMDRESPEND;
     #undef RWORD
         } else {
-...
         s->status |= PL181_STATUS_CMDTIMEOUT;
+    }
     /* Transfer data between teh card and the FIFO.  This is complicated by
     /* Transfer data between the card and the FIFO.  This is complicated by
        the FIFO holding 32-bit words and the card taking data in single byte
        chunks.  FIFO bytes are transferred in little-endian order.  */

         RTL8139State *s = opaque;
         int avail;
         /* Recieve (drop) packets if card is disabled.  */
         /* Receive (drop) packets if card is disabled.  */
         if (!s->clock_enabled)
           return 1;
         if (!rtl8139_receiver_enabled(s))

                         s->setup_state = SETUP_STATE_IDLE;
                         /* transfer OK */
                     } else {
                         /* ignore additionnal output */
                         /* ignore additional output */
+                    }
                     break;
                 case SETUP_STATE_DATA:

b/linux-user/signal.c
244	244	}
245	245
246	246	/* XXX: we support only POSIX RT signals are used. */
247		/* XXX: find a solution for 64 bit (additionnal malloced data is needed) */
	247	/* XXX: find a solution for 64 bit (additional malloced data is needed) */
248	248	void target_to_host_siginfo(siginfo_t info, const target_siginfo_t tinfo)
249	249	{
250	250	info->si_signo = tswap32(tinfo->si_signo);

     };
     /* Name of register halves for MAC/EMAC.
        Seperate from reg_names since 'spu', 'fpl' look weird.  */
        Separate from reg_names since 'spu', 'fpl' look weird.  */
     static char *const reg_half_names[] =
+    {
       "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",

     #define VIP_MASK                0x00100000
     #define ID_MASK                 0x00200000
     /* hidden flags - used internally by qemu to represent additionnal cpu
     /* hidden flags - used internally by qemu to represent additional cpu
        states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
        using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
        with eflags. */

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