root / target-mips / op_helper.c @ aa343735
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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
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3 | 5fafdf24 | ths | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | 2d0e944d | ths | #include <stdlib.h> |
21 | 6af0bf9c | bellard | #include "exec.h" |
22 | 6af0bf9c | bellard | |
23 | 4ad40f36 | bellard | #define GETPC() (__builtin_return_address(0)) |
24 | 4ad40f36 | bellard | |
25 | 6af0bf9c | bellard | /*****************************************************************************/
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26 | 6af0bf9c | bellard | /* Exceptions processing helpers */
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27 | 6af0bf9c | bellard | |
28 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code) |
29 | 6af0bf9c | bellard | { |
30 | 6af0bf9c | bellard | #if 1 |
31 | 6af0bf9c | bellard | if (logfile && exception < 0x100) |
32 | 6af0bf9c | bellard | fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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33 | 6af0bf9c | bellard | #endif
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34 | 6af0bf9c | bellard | env->exception_index = exception; |
35 | 6af0bf9c | bellard | env->error_code = error_code; |
36 | 6af0bf9c | bellard | T0 = 0;
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37 | 6af0bf9c | bellard | cpu_loop_exit(); |
38 | 6af0bf9c | bellard | } |
39 | 6af0bf9c | bellard | |
40 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception)
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41 | 6af0bf9c | bellard | { |
42 | 6af0bf9c | bellard | do_raise_exception_err(exception, 0);
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43 | 6af0bf9c | bellard | } |
44 | 6af0bf9c | bellard | |
45 | 4ad40f36 | bellard | void do_restore_state (void *pc_ptr) |
46 | 4ad40f36 | bellard | { |
47 | 4ad40f36 | bellard | TranslationBlock *tb; |
48 | 4ad40f36 | bellard | unsigned long pc = (unsigned long) pc_ptr; |
49 | 4ad40f36 | bellard | |
50 | 4ad40f36 | bellard | tb = tb_find_pc (pc); |
51 | 4ad40f36 | bellard | cpu_restore_state (tb, env, pc, NULL);
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52 | 4ad40f36 | bellard | } |
53 | 4ad40f36 | bellard | |
54 | e397ee33 | ths | void do_raise_exception_direct_err (uint32_t exception, int error_code) |
55 | 4ad40f36 | bellard | { |
56 | 4ad40f36 | bellard | do_restore_state (GETPC ()); |
57 | e397ee33 | ths | do_raise_exception_err (exception, error_code); |
58 | e397ee33 | ths | } |
59 | e397ee33 | ths | |
60 | e397ee33 | ths | void do_raise_exception_direct (uint32_t exception)
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61 | e397ee33 | ths | { |
62 | e397ee33 | ths | do_raise_exception_direct_err (exception, 0);
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63 | 4ad40f36 | bellard | } |
64 | 4ad40f36 | bellard | |
65 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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66 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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67 | c570fd16 | ths | /* Those might call libgcc functions. */
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68 | c570fd16 | ths | void do_dsll (void) |
69 | c570fd16 | ths | { |
70 | c570fd16 | ths | T0 = T0 << T1; |
71 | c570fd16 | ths | } |
72 | c570fd16 | ths | |
73 | c570fd16 | ths | void do_dsll32 (void) |
74 | c570fd16 | ths | { |
75 | c570fd16 | ths | T0 = T0 << (T1 + 32);
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76 | c570fd16 | ths | } |
77 | c570fd16 | ths | |
78 | c570fd16 | ths | void do_dsra (void) |
79 | c570fd16 | ths | { |
80 | c570fd16 | ths | T0 = (int64_t)T0 >> T1; |
81 | c570fd16 | ths | } |
82 | c570fd16 | ths | |
83 | c570fd16 | ths | void do_dsra32 (void) |
84 | c570fd16 | ths | { |
85 | c570fd16 | ths | T0 = (int64_t)T0 >> (T1 + 32);
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86 | c570fd16 | ths | } |
87 | c570fd16 | ths | |
88 | c570fd16 | ths | void do_dsrl (void) |
89 | c570fd16 | ths | { |
90 | c570fd16 | ths | T0 = T0 >> T1; |
91 | c570fd16 | ths | } |
92 | c570fd16 | ths | |
93 | c570fd16 | ths | void do_dsrl32 (void) |
94 | c570fd16 | ths | { |
95 | c570fd16 | ths | T0 = T0 >> (T1 + 32);
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96 | c570fd16 | ths | } |
97 | c570fd16 | ths | |
98 | c570fd16 | ths | void do_drotr (void) |
99 | c570fd16 | ths | { |
100 | c570fd16 | ths | target_ulong tmp; |
101 | c570fd16 | ths | |
102 | c570fd16 | ths | if (T1) {
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103 | c570fd16 | ths | tmp = T0 << (0x40 - T1);
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104 | c570fd16 | ths | T0 = (T0 >> T1) | tmp; |
105 | 5a63bcb2 | ths | } |
106 | c570fd16 | ths | } |
107 | c570fd16 | ths | |
108 | c570fd16 | ths | void do_drotr32 (void) |
109 | c570fd16 | ths | { |
110 | c570fd16 | ths | target_ulong tmp; |
111 | c570fd16 | ths | |
112 | c570fd16 | ths | if (T1) {
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113 | c570fd16 | ths | tmp = T0 << (0x40 - (32 + T1)); |
114 | c570fd16 | ths | T0 = (T0 >> (32 + T1)) | tmp;
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115 | 5a63bcb2 | ths | } |
116 | c570fd16 | ths | } |
117 | c570fd16 | ths | |
118 | c570fd16 | ths | void do_dsllv (void) |
119 | c570fd16 | ths | { |
120 | c570fd16 | ths | T0 = T1 << (T0 & 0x3F);
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121 | c570fd16 | ths | } |
122 | c570fd16 | ths | |
123 | c570fd16 | ths | void do_dsrav (void) |
124 | c570fd16 | ths | { |
125 | c570fd16 | ths | T0 = (int64_t)T1 >> (T0 & 0x3F);
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126 | c570fd16 | ths | } |
127 | c570fd16 | ths | |
128 | c570fd16 | ths | void do_dsrlv (void) |
129 | c570fd16 | ths | { |
130 | c570fd16 | ths | T0 = T1 >> (T0 & 0x3F);
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131 | c570fd16 | ths | } |
132 | c570fd16 | ths | |
133 | c570fd16 | ths | void do_drotrv (void) |
134 | c570fd16 | ths | { |
135 | c570fd16 | ths | target_ulong tmp; |
136 | c570fd16 | ths | |
137 | c570fd16 | ths | T0 &= 0x3F;
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138 | c570fd16 | ths | if (T0) {
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139 | c570fd16 | ths | tmp = T1 << (0x40 - T0);
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140 | c570fd16 | ths | T0 = (T1 >> T0) | tmp; |
141 | c570fd16 | ths | } else
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142 | c570fd16 | ths | T0 = T1; |
143 | c570fd16 | ths | } |
144 | c570fd16 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
145 | 540635ba | ths | #endif /* TARGET_MIPSN32 || TARGET_MIPS64 */ |
146 | c570fd16 | ths | |
147 | 6af0bf9c | bellard | /* 64 bits arithmetic for 32 bits hosts */
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148 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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149 | aa343735 | ths | static always_inline uint64_t get_HILO (void) |
150 | 6af0bf9c | bellard | { |
151 | ead9360e | ths | return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc]; |
152 | 6af0bf9c | bellard | } |
153 | 6af0bf9c | bellard | |
154 | aa343735 | ths | static always_inline void set_HILO (uint64_t HILO) |
155 | 6af0bf9c | bellard | { |
156 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)HILO;
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157 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)(HILO >> 32); |
158 | 6af0bf9c | bellard | } |
159 | 6af0bf9c | bellard | |
160 | 6af0bf9c | bellard | void do_mult (void) |
161 | 6af0bf9c | bellard | { |
162 | 4ad40f36 | bellard | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
163 | 6af0bf9c | bellard | } |
164 | 6af0bf9c | bellard | |
165 | 6af0bf9c | bellard | void do_multu (void) |
166 | 6af0bf9c | bellard | { |
167 | c570fd16 | ths | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
168 | 6af0bf9c | bellard | } |
169 | 6af0bf9c | bellard | |
170 | 6af0bf9c | bellard | void do_madd (void) |
171 | 6af0bf9c | bellard | { |
172 | 6af0bf9c | bellard | int64_t tmp; |
173 | 6af0bf9c | bellard | |
174 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
175 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() + tmp); |
176 | 6af0bf9c | bellard | } |
177 | 6af0bf9c | bellard | |
178 | 6af0bf9c | bellard | void do_maddu (void) |
179 | 6af0bf9c | bellard | { |
180 | 6af0bf9c | bellard | uint64_t tmp; |
181 | 6af0bf9c | bellard | |
182 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
183 | 6af0bf9c | bellard | set_HILO(get_HILO() + tmp); |
184 | 6af0bf9c | bellard | } |
185 | 6af0bf9c | bellard | |
186 | 6af0bf9c | bellard | void do_msub (void) |
187 | 6af0bf9c | bellard | { |
188 | 6af0bf9c | bellard | int64_t tmp; |
189 | 6af0bf9c | bellard | |
190 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
191 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() - tmp); |
192 | 6af0bf9c | bellard | } |
193 | 6af0bf9c | bellard | |
194 | 6af0bf9c | bellard | void do_msubu (void) |
195 | 6af0bf9c | bellard | { |
196 | 6af0bf9c | bellard | uint64_t tmp; |
197 | 6af0bf9c | bellard | |
198 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
199 | 6af0bf9c | bellard | set_HILO(get_HILO() - tmp); |
200 | 6af0bf9c | bellard | } |
201 | 6af0bf9c | bellard | #endif
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202 | 6af0bf9c | bellard | |
203 | 80c27194 | ths | #if HOST_LONG_BITS < 64 |
204 | 80c27194 | ths | void do_div (void) |
205 | 80c27194 | ths | { |
206 | 80c27194 | ths | /* 64bit datatypes because we may see overflow/underflow. */
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207 | 80c27194 | ths | if (T1 != 0) { |
208 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
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209 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
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210 | 80c27194 | ths | } |
211 | 80c27194 | ths | } |
212 | 80c27194 | ths | #endif
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213 | 80c27194 | ths | |
214 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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215 | c570fd16 | ths | void do_ddiv (void) |
216 | c570fd16 | ths | { |
217 | c570fd16 | ths | if (T1 != 0) { |
218 | 2d0e944d | ths | lldiv_t res = lldiv((int64_t)T0, (int64_t)T1); |
219 | ead9360e | ths | env->LO[0][env->current_tc] = res.quot;
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220 | ead9360e | ths | env->HI[0][env->current_tc] = res.rem;
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221 | c570fd16 | ths | } |
222 | c570fd16 | ths | } |
223 | c570fd16 | ths | |
224 | 12a4b2aa | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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225 | c570fd16 | ths | void do_ddivu (void) |
226 | c570fd16 | ths | { |
227 | c570fd16 | ths | if (T1 != 0) { |
228 | ead9360e | ths | env->LO[0][env->current_tc] = T0 / T1;
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229 | ead9360e | ths | env->HI[0][env->current_tc] = T0 % T1;
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230 | c570fd16 | ths | } |
231 | c570fd16 | ths | } |
232 | c570fd16 | ths | #endif
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233 | 540635ba | ths | #endif /* TARGET_MIPSN32 || TARGET_MIPS64 */ |
234 | c570fd16 | ths | |
235 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
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236 | 873eb012 | ths | void do_mfc0_random (void) |
237 | 048f6b4d | bellard | { |
238 | 873eb012 | ths | cpu_abort(env, "mfc0 random\n");
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239 | 048f6b4d | bellard | } |
240 | 873eb012 | ths | |
241 | 873eb012 | ths | void do_mfc0_count (void) |
242 | 873eb012 | ths | { |
243 | 873eb012 | ths | cpu_abort(env, "mfc0 count\n");
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244 | 873eb012 | ths | } |
245 | 873eb012 | ths | |
246 | 8c0fdd85 | ths | void cpu_mips_store_count(CPUState *env, uint32_t value)
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247 | 048f6b4d | bellard | { |
248 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 count\n");
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249 | 8c0fdd85 | ths | } |
250 | 8c0fdd85 | ths | |
251 | 8c0fdd85 | ths | void cpu_mips_store_compare(CPUState *env, uint32_t value)
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252 | 8c0fdd85 | ths | { |
253 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 compare\n");
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254 | 8c0fdd85 | ths | } |
255 | 8c0fdd85 | ths | |
256 | 42532189 | ths | void cpu_mips_start_count(CPUState *env)
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257 | 42532189 | ths | { |
258 | 42532189 | ths | cpu_abort(env, "start count\n");
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259 | 42532189 | ths | } |
260 | 42532189 | ths | |
261 | 42532189 | ths | void cpu_mips_stop_count(CPUState *env)
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262 | 42532189 | ths | { |
263 | 42532189 | ths | cpu_abort(env, "stop count\n");
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264 | 42532189 | ths | } |
265 | 42532189 | ths | |
266 | 4de9b249 | ths | void cpu_mips_update_irq(CPUState *env)
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267 | 4de9b249 | ths | { |
268 | 4de9b249 | ths | cpu_abort(env, "mtc0 status / mtc0 cause\n");
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269 | 4de9b249 | ths | } |
270 | 4de9b249 | ths | |
271 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
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272 | 8c0fdd85 | ths | { |
273 | 7a387fff | ths | cpu_abort(env, "mtc0 status debug\n");
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274 | 8c0fdd85 | ths | } |
275 | 8c0fdd85 | ths | |
276 | 7a387fff | ths | void do_mtc0_status_irqraise_debug (void) |
277 | 8c0fdd85 | ths | { |
278 | 7a387fff | ths | cpu_abort(env, "mtc0 status irqraise debug\n");
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279 | 048f6b4d | bellard | } |
280 | 048f6b4d | bellard | |
281 | 8c0fdd85 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
282 | 8c0fdd85 | ths | { |
283 | 8c0fdd85 | ths | cpu_abort(env, "mips_tlb_flush\n");
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284 | 8c0fdd85 | ths | } |
285 | 8c0fdd85 | ths | |
286 | 048f6b4d | bellard | #else
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287 | 048f6b4d | bellard | |
288 | 6af0bf9c | bellard | /* CP0 helpers */
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289 | 873eb012 | ths | void do_mfc0_random (void) |
290 | 6af0bf9c | bellard | { |
291 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_random(env); |
292 | 873eb012 | ths | } |
293 | 6af0bf9c | bellard | |
294 | 873eb012 | ths | void do_mfc0_count (void) |
295 | 873eb012 | ths | { |
296 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_count(env); |
297 | 6af0bf9c | bellard | } |
298 | 6af0bf9c | bellard | |
299 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
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300 | 6af0bf9c | bellard | { |
301 | f41c52f1 | ths | fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
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302 | f41c52f1 | ths | old, old & env->CP0_Cause & CP0Ca_IP_mask, |
303 | f41c52f1 | ths | val, val & env->CP0_Cause & CP0Ca_IP_mask, |
304 | f41c52f1 | ths | env->CP0_Cause); |
305 | f41c52f1 | ths | (env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
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306 | f41c52f1 | ths | : fputs("\n", logfile);
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307 | 8c0fdd85 | ths | } |
308 | 8c0fdd85 | ths | |
309 | 8c0fdd85 | ths | void do_mtc0_status_irqraise_debug(void) |
310 | 8c0fdd85 | ths | { |
311 | 8c0fdd85 | ths | fprintf(logfile, "Raise pending IRQs\n");
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312 | 6af0bf9c | bellard | } |
313 | 6af0bf9c | bellard | |
314 | 6ea83fed | bellard | void fpu_handle_exception(void) |
315 | 6ea83fed | bellard | { |
316 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
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317 | ead9360e | ths | int flags = get_float_exception_flags(&env->fpu->fp_status);
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318 | 6ea83fed | bellard | unsigned int cpuflags = 0, enable, cause = 0; |
319 | 6ea83fed | bellard | |
320 | ead9360e | ths | enable = GET_FP_ENABLE(env->fpu->fcr31); |
321 | 6ea83fed | bellard | |
322 | 3b46e624 | ths | /* determine current flags */
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323 | 6ea83fed | bellard | if (flags & float_flag_invalid) {
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324 | 6ea83fed | bellard | cpuflags |= FP_INVALID; |
325 | 6ea83fed | bellard | cause |= FP_INVALID & enable; |
326 | 6ea83fed | bellard | } |
327 | 6ea83fed | bellard | if (flags & float_flag_divbyzero) {
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328 | 3b46e624 | ths | cpuflags |= FP_DIV0; |
329 | 6ea83fed | bellard | cause |= FP_DIV0 & enable; |
330 | 6ea83fed | bellard | } |
331 | 6ea83fed | bellard | if (flags & float_flag_overflow) {
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332 | 3b46e624 | ths | cpuflags |= FP_OVERFLOW; |
333 | 6ea83fed | bellard | cause |= FP_OVERFLOW & enable; |
334 | 6ea83fed | bellard | } |
335 | 6ea83fed | bellard | if (flags & float_flag_underflow) {
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336 | 3b46e624 | ths | cpuflags |= FP_UNDERFLOW; |
337 | 6ea83fed | bellard | cause |= FP_UNDERFLOW & enable; |
338 | 6ea83fed | bellard | } |
339 | 6ea83fed | bellard | if (flags & float_flag_inexact) {
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340 | 5fafdf24 | ths | cpuflags |= FP_INEXACT; |
341 | 6ea83fed | bellard | cause |= FP_INEXACT & enable; |
342 | 6ea83fed | bellard | } |
343 | ead9360e | ths | SET_FP_FLAGS(env->fpu->fcr31, cpuflags); |
344 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, cause); |
345 | 6ea83fed | bellard | #else
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346 | ead9360e | ths | SET_FP_FLAGS(env->fpu->fcr31, 0);
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347 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, 0);
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348 | 6ea83fed | bellard | #endif
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349 | 6ea83fed | bellard | } |
350 | 6ea83fed | bellard | |
351 | 6af0bf9c | bellard | /* TLB management */
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352 | 814b9a47 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
353 | 814b9a47 | ths | { |
354 | 814b9a47 | ths | /* Flush qemu's TLB and discard all shadowed entries. */
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355 | 814b9a47 | ths | tlb_flush (env, flush_global); |
356 | ead9360e | ths | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
357 | 814b9a47 | ths | } |
358 | 814b9a47 | ths | |
359 | 29929e34 | ths | static void r4k_mips_tlb_flush_extra (CPUState *env, int first) |
360 | 814b9a47 | ths | { |
361 | 814b9a47 | ths | /* Discard entries from env->tlb[first] onwards. */
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362 | ead9360e | ths | while (env->tlb->tlb_in_use > first) {
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363 | ead9360e | ths | r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
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364 | 814b9a47 | ths | } |
365 | 814b9a47 | ths | } |
366 | 814b9a47 | ths | |
367 | 29929e34 | ths | static void r4k_fill_tlb (int idx) |
368 | 6af0bf9c | bellard | { |
369 | 29929e34 | ths | r4k_tlb_t *tlb; |
370 | 6af0bf9c | bellard | |
371 | 6af0bf9c | bellard | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
372 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
373 | f2e9ebef | ths | tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
|
374 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
375 | e034e2c3 | ths | tlb->VPN &= env->SEGMask; |
376 | 100ce988 | ths | #endif
|
377 | 98c1b82b | pbrook | tlb->ASID = env->CP0_EntryHi & 0xFF;
|
378 | 3b1c8be4 | ths | tlb->PageMask = env->CP0_PageMask; |
379 | 6af0bf9c | bellard | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
380 | 98c1b82b | pbrook | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
381 | 98c1b82b | pbrook | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
382 | 98c1b82b | pbrook | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
383 | 6af0bf9c | bellard | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
384 | 98c1b82b | pbrook | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
385 | 98c1b82b | pbrook | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
386 | 98c1b82b | pbrook | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
387 | 6af0bf9c | bellard | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
388 | 6af0bf9c | bellard | } |
389 | 6af0bf9c | bellard | |
390 | 29929e34 | ths | void r4k_do_tlbwi (void) |
391 | 6af0bf9c | bellard | { |
392 | 814b9a47 | ths | /* Discard cached TLB entries. We could avoid doing this if the
|
393 | 814b9a47 | ths | tlbwi is just upgrading access permissions on the current entry;
|
394 | 814b9a47 | ths | that might be a further win. */
|
395 | ead9360e | ths | r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); |
396 | 814b9a47 | ths | |
397 | ead9360e | ths | r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
|
398 | ead9360e | ths | r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb); |
399 | 6af0bf9c | bellard | } |
400 | 6af0bf9c | bellard | |
401 | 29929e34 | ths | void r4k_do_tlbwr (void) |
402 | 6af0bf9c | bellard | { |
403 | 6af0bf9c | bellard | int r = cpu_mips_get_random(env);
|
404 | 6af0bf9c | bellard | |
405 | 29929e34 | ths | r4k_invalidate_tlb(env, r, 1);
|
406 | 29929e34 | ths | r4k_fill_tlb(r); |
407 | 6af0bf9c | bellard | } |
408 | 6af0bf9c | bellard | |
409 | 29929e34 | ths | void r4k_do_tlbp (void) |
410 | 6af0bf9c | bellard | { |
411 | 29929e34 | ths | r4k_tlb_t *tlb; |
412 | f2e9ebef | ths | target_ulong mask; |
413 | 6af0bf9c | bellard | target_ulong tag; |
414 | f2e9ebef | ths | target_ulong VPN; |
415 | 6af0bf9c | bellard | uint8_t ASID; |
416 | 6af0bf9c | bellard | int i;
|
417 | 6af0bf9c | bellard | |
418 | 3d9fb9fe | bellard | ASID = env->CP0_EntryHi & 0xFF;
|
419 | ead9360e | ths | for (i = 0; i < env->tlb->nb_tlb; i++) { |
420 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[i]; |
421 | f2e9ebef | ths | /* 1k pages are not supported. */
|
422 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
423 | f2e9ebef | ths | tag = env->CP0_EntryHi & ~mask; |
424 | f2e9ebef | ths | VPN = tlb->VPN & ~mask; |
425 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
|
426 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
427 | 6af0bf9c | bellard | /* TLB match */
|
428 | 9c2149c8 | ths | env->CP0_Index = i; |
429 | 6af0bf9c | bellard | break;
|
430 | 6af0bf9c | bellard | } |
431 | 6af0bf9c | bellard | } |
432 | ead9360e | ths | if (i == env->tlb->nb_tlb) {
|
433 | 814b9a47 | ths | /* No match. Discard any shadow entries, if any of them match. */
|
434 | ead9360e | ths | for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
|
435 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[i]; |
436 | f2e9ebef | ths | /* 1k pages are not supported. */
|
437 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
438 | f2e9ebef | ths | tag = env->CP0_EntryHi & ~mask; |
439 | f2e9ebef | ths | VPN = tlb->VPN & ~mask; |
440 | 814b9a47 | ths | /* Check ASID, virtual page number & size */
|
441 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
442 | 29929e34 | ths | r4k_mips_tlb_flush_extra (env, i); |
443 | 814b9a47 | ths | break;
|
444 | 814b9a47 | ths | } |
445 | 814b9a47 | ths | } |
446 | 814b9a47 | ths | |
447 | 9c2149c8 | ths | env->CP0_Index |= 0x80000000;
|
448 | 6af0bf9c | bellard | } |
449 | 6af0bf9c | bellard | } |
450 | 6af0bf9c | bellard | |
451 | 29929e34 | ths | void r4k_do_tlbr (void) |
452 | 6af0bf9c | bellard | { |
453 | 29929e34 | ths | r4k_tlb_t *tlb; |
454 | 09c56b84 | pbrook | uint8_t ASID; |
455 | 6af0bf9c | bellard | |
456 | 09c56b84 | pbrook | ASID = env->CP0_EntryHi & 0xFF;
|
457 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb]; |
458 | 4ad40f36 | bellard | |
459 | 4ad40f36 | bellard | /* If this will change the current ASID, flush qemu's TLB. */
|
460 | 814b9a47 | ths | if (ASID != tlb->ASID)
|
461 | 814b9a47 | ths | cpu_mips_tlb_flush (env, 1);
|
462 | 814b9a47 | ths | |
463 | ead9360e | ths | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
464 | 4ad40f36 | bellard | |
465 | 6af0bf9c | bellard | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
466 | 3b1c8be4 | ths | env->CP0_PageMask = tlb->PageMask; |
467 | 7495fd0f | ths | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
468 | 7495fd0f | ths | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
469 | 7495fd0f | ths | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
470 | 7495fd0f | ths | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
471 | 6af0bf9c | bellard | } |
472 | 6af0bf9c | bellard | |
473 | 048f6b4d | bellard | #endif /* !CONFIG_USER_ONLY */ |
474 | 048f6b4d | bellard | |
475 | c570fd16 | ths | void dump_ldst (const unsigned char *func) |
476 | 6af0bf9c | bellard | { |
477 | 6af0bf9c | bellard | if (loglevel)
|
478 | 3594c774 | ths | fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1); |
479 | 6af0bf9c | bellard | } |
480 | 6af0bf9c | bellard | |
481 | 6af0bf9c | bellard | void dump_sc (void) |
482 | 6af0bf9c | bellard | { |
483 | 6af0bf9c | bellard | if (loglevel) {
|
484 | 3594c774 | ths | fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__, |
485 | 6af0bf9c | bellard | T1, T0, env->CP0_LLAddr); |
486 | 6af0bf9c | bellard | } |
487 | 6af0bf9c | bellard | } |
488 | 6af0bf9c | bellard | |
489 | f41c52f1 | ths | void debug_pre_eret (void) |
490 | 6af0bf9c | bellard | { |
491 | f41c52f1 | ths | fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
492 | ead9360e | ths | env->PC[env->current_tc], env->CP0_EPC); |
493 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
494 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
495 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
496 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
497 | f41c52f1 | ths | fputs("\n", logfile);
|
498 | f41c52f1 | ths | } |
499 | f41c52f1 | ths | |
500 | f41c52f1 | ths | void debug_post_eret (void) |
501 | f41c52f1 | ths | { |
502 | 744e0915 | ths | fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
503 | ead9360e | ths | env->PC[env->current_tc], env->CP0_EPC); |
504 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
505 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
506 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
507 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
508 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_UM)
|
509 | f41c52f1 | ths | fputs(", UM\n", logfile);
|
510 | f41c52f1 | ths | else
|
511 | 24c7b0e3 | ths | fputs("\n", logfile);
|
512 | 6af0bf9c | bellard | } |
513 | 6af0bf9c | bellard | |
514 | 6af0bf9c | bellard | void do_pmon (int function) |
515 | 6af0bf9c | bellard | { |
516 | 6af0bf9c | bellard | function /= 2;
|
517 | 6af0bf9c | bellard | switch (function) {
|
518 | 6af0bf9c | bellard | case 2: /* TODO: char inbyte(int waitflag); */ |
519 | ead9360e | ths | if (env->gpr[4][env->current_tc] == 0) |
520 | ead9360e | ths | env->gpr[2][env->current_tc] = -1; |
521 | 6af0bf9c | bellard | /* Fall through */
|
522 | 6af0bf9c | bellard | case 11: /* TODO: char inbyte (void); */ |
523 | ead9360e | ths | env->gpr[2][env->current_tc] = -1; |
524 | 6af0bf9c | bellard | break;
|
525 | 6af0bf9c | bellard | case 3: |
526 | 6af0bf9c | bellard | case 12: |
527 | ead9360e | ths | printf("%c", (char)(env->gpr[4][env->current_tc] & 0xFF)); |
528 | 6af0bf9c | bellard | break;
|
529 | 6af0bf9c | bellard | case 17: |
530 | 6af0bf9c | bellard | break;
|
531 | 6af0bf9c | bellard | case 158: |
532 | 6af0bf9c | bellard | { |
533 | ead9360e | ths | unsigned char *fmt = (void *)(unsigned long)env->gpr[4][env->current_tc]; |
534 | 6af0bf9c | bellard | printf("%s", fmt);
|
535 | 6af0bf9c | bellard | } |
536 | 6af0bf9c | bellard | break;
|
537 | 6af0bf9c | bellard | } |
538 | 6af0bf9c | bellard | } |
539 | e37e863f | bellard | |
540 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
541 | e37e863f | bellard | |
542 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
543 | 4ad40f36 | bellard | |
544 | e37e863f | bellard | #define MMUSUFFIX _mmu
|
545 | 4ad40f36 | bellard | #define ALIGNED_ONLY
|
546 | e37e863f | bellard | |
547 | e37e863f | bellard | #define SHIFT 0 |
548 | e37e863f | bellard | #include "softmmu_template.h" |
549 | e37e863f | bellard | |
550 | e37e863f | bellard | #define SHIFT 1 |
551 | e37e863f | bellard | #include "softmmu_template.h" |
552 | e37e863f | bellard | |
553 | e37e863f | bellard | #define SHIFT 2 |
554 | e37e863f | bellard | #include "softmmu_template.h" |
555 | e37e863f | bellard | |
556 | e37e863f | bellard | #define SHIFT 3 |
557 | e37e863f | bellard | #include "softmmu_template.h" |
558 | e37e863f | bellard | |
559 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
560 | 4ad40f36 | bellard | { |
561 | 4ad40f36 | bellard | env->CP0_BadVAddr = addr; |
562 | 4ad40f36 | bellard | do_restore_state (retaddr); |
563 | 4ad40f36 | bellard | do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
564 | 4ad40f36 | bellard | } |
565 | 4ad40f36 | bellard | |
566 | e37e863f | bellard | void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) |
567 | e37e863f | bellard | { |
568 | e37e863f | bellard | TranslationBlock *tb; |
569 | e37e863f | bellard | CPUState *saved_env; |
570 | e37e863f | bellard | unsigned long pc; |
571 | e37e863f | bellard | int ret;
|
572 | e37e863f | bellard | |
573 | e37e863f | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
574 | e37e863f | bellard | generated code */
|
575 | e37e863f | bellard | saved_env = env; |
576 | e37e863f | bellard | env = cpu_single_env; |
577 | e37e863f | bellard | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
578 | e37e863f | bellard | if (ret) {
|
579 | e37e863f | bellard | if (retaddr) {
|
580 | e37e863f | bellard | /* now we have a real cpu fault */
|
581 | e37e863f | bellard | pc = (unsigned long)retaddr; |
582 | e37e863f | bellard | tb = tb_find_pc(pc); |
583 | e37e863f | bellard | if (tb) {
|
584 | e37e863f | bellard | /* the PC is inside the translated code. It means that we have
|
585 | e37e863f | bellard | a virtual CPU fault */
|
586 | e37e863f | bellard | cpu_restore_state(tb, env, pc, NULL);
|
587 | e37e863f | bellard | } |
588 | e37e863f | bellard | } |
589 | e37e863f | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
590 | e37e863f | bellard | } |
591 | e37e863f | bellard | env = saved_env; |
592 | e37e863f | bellard | } |
593 | e37e863f | bellard | |
594 | e37e863f | bellard | #endif
|
595 | fd4a04eb | ths | |
596 | fd4a04eb | ths | /* Complex FPU operations which may need stack space. */
|
597 | fd4a04eb | ths | |
598 | 8dfdb87c | ths | #define FLOAT_SIGN32 (1 << 31) |
599 | 8dfdb87c | ths | #define FLOAT_SIGN64 (1ULL << 63) |
600 | 8dfdb87c | ths | #define FLOAT_ONE32 (0x3f8 << 20) |
601 | 8dfdb87c | ths | #define FLOAT_ONE64 (0x3ffULL << 52) |
602 | 8dfdb87c | ths | #define FLOAT_TWO32 (1 << 30) |
603 | 8dfdb87c | ths | #define FLOAT_TWO64 (1ULL << 62) |
604 | 54454097 | ths | #define FLOAT_QNAN32 0x7fbfffff |
605 | 54454097 | ths | #define FLOAT_QNAN64 0x7ff7ffffffffffffULL |
606 | 54454097 | ths | #define FLOAT_SNAN32 0x7fffffff |
607 | 54454097 | ths | #define FLOAT_SNAN64 0x7fffffffffffffffULL |
608 | 8dfdb87c | ths | |
609 | fd4a04eb | ths | /* convert MIPS rounding mode in FCR31 to IEEE library */
|
610 | fd4a04eb | ths | unsigned int ieee_rm[] = { |
611 | fd4a04eb | ths | float_round_nearest_even, |
612 | fd4a04eb | ths | float_round_to_zero, |
613 | fd4a04eb | ths | float_round_up, |
614 | fd4a04eb | ths | float_round_down |
615 | fd4a04eb | ths | }; |
616 | fd4a04eb | ths | |
617 | fd4a04eb | ths | #define RESTORE_ROUNDING_MODE \
|
618 | ead9360e | ths | set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
|
619 | fd4a04eb | ths | |
620 | ead9360e | ths | void do_cfc1 (int reg) |
621 | fd4a04eb | ths | { |
622 | ead9360e | ths | switch (reg) {
|
623 | ead9360e | ths | case 0: |
624 | ead9360e | ths | T0 = (int32_t)env->fpu->fcr0; |
625 | ead9360e | ths | break;
|
626 | ead9360e | ths | case 25: |
627 | ead9360e | ths | T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1); |
628 | ead9360e | ths | break;
|
629 | ead9360e | ths | case 26: |
630 | ead9360e | ths | T0 = env->fpu->fcr31 & 0x0003f07c;
|
631 | ead9360e | ths | break;
|
632 | ead9360e | ths | case 28: |
633 | ead9360e | ths | T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4); |
634 | ead9360e | ths | break;
|
635 | ead9360e | ths | default:
|
636 | ead9360e | ths | T0 = (int32_t)env->fpu->fcr31; |
637 | ead9360e | ths | break;
|
638 | ead9360e | ths | } |
639 | ead9360e | ths | } |
640 | ead9360e | ths | |
641 | ead9360e | ths | void do_ctc1 (int reg) |
642 | ead9360e | ths | { |
643 | ead9360e | ths | switch(reg) {
|
644 | fd4a04eb | ths | case 25: |
645 | fd4a04eb | ths | if (T0 & 0xffffff00) |
646 | fd4a04eb | ths | return;
|
647 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) | |
648 | fd4a04eb | ths | ((T0 & 0x1) << 23); |
649 | fd4a04eb | ths | break;
|
650 | fd4a04eb | ths | case 26: |
651 | fd4a04eb | ths | if (T0 & 0x007c0000) |
652 | fd4a04eb | ths | return;
|
653 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c); |
654 | fd4a04eb | ths | break;
|
655 | fd4a04eb | ths | case 28: |
656 | fd4a04eb | ths | if (T0 & 0x007c0000) |
657 | fd4a04eb | ths | return;
|
658 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) | |
659 | fd4a04eb | ths | ((T0 & 0x4) << 22); |
660 | fd4a04eb | ths | break;
|
661 | fd4a04eb | ths | case 31: |
662 | fd4a04eb | ths | if (T0 & 0x007c0000) |
663 | fd4a04eb | ths | return;
|
664 | ead9360e | ths | env->fpu->fcr31 = T0; |
665 | fd4a04eb | ths | break;
|
666 | fd4a04eb | ths | default:
|
667 | fd4a04eb | ths | return;
|
668 | fd4a04eb | ths | } |
669 | fd4a04eb | ths | /* set rounding mode */
|
670 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
671 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
672 | ead9360e | ths | if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31)) |
673 | fd4a04eb | ths | do_raise_exception(EXCP_FPE); |
674 | fd4a04eb | ths | } |
675 | fd4a04eb | ths | |
676 | aa343735 | ths | static always_inline char ieee_ex_to_mips(char xcpt) |
677 | fd4a04eb | ths | { |
678 | fd4a04eb | ths | return (xcpt & float_flag_inexact) >> 5 | |
679 | fd4a04eb | ths | (xcpt & float_flag_underflow) >> 3 |
|
680 | fd4a04eb | ths | (xcpt & float_flag_overflow) >> 1 |
|
681 | fd4a04eb | ths | (xcpt & float_flag_divbyzero) << 1 |
|
682 | fd4a04eb | ths | (xcpt & float_flag_invalid) << 4;
|
683 | fd4a04eb | ths | } |
684 | fd4a04eb | ths | |
685 | aa343735 | ths | static always_inline char mips_ex_to_ieee(char xcpt) |
686 | fd4a04eb | ths | { |
687 | fd4a04eb | ths | return (xcpt & FP_INEXACT) << 5 | |
688 | fd4a04eb | ths | (xcpt & FP_UNDERFLOW) << 3 |
|
689 | fd4a04eb | ths | (xcpt & FP_OVERFLOW) << 1 |
|
690 | fd4a04eb | ths | (xcpt & FP_DIV0) >> 1 |
|
691 | fd4a04eb | ths | (xcpt & FP_INVALID) >> 4;
|
692 | fd4a04eb | ths | } |
693 | fd4a04eb | ths | |
694 | aa343735 | ths | static always_inline void update_fcr31(void) |
695 | fd4a04eb | ths | { |
696 | ead9360e | ths | int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
|
697 | fd4a04eb | ths | |
698 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, tmp); |
699 | ead9360e | ths | if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
|
700 | fd4a04eb | ths | do_raise_exception(EXCP_FPE); |
701 | fd4a04eb | ths | else
|
702 | ead9360e | ths | UPDATE_FP_FLAGS(env->fpu->fcr31, tmp); |
703 | fd4a04eb | ths | } |
704 | fd4a04eb | ths | |
705 | fd4a04eb | ths | #define FLOAT_OP(name, p) void do_float_##name##_##p(void) |
706 | fd4a04eb | ths | |
707 | fd4a04eb | ths | FLOAT_OP(cvtd, s) |
708 | fd4a04eb | ths | { |
709 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
710 | ead9360e | ths | FDT2 = float32_to_float64(FST0, &env->fpu->fp_status); |
711 | fd4a04eb | ths | update_fcr31(); |
712 | fd4a04eb | ths | } |
713 | fd4a04eb | ths | FLOAT_OP(cvtd, w) |
714 | fd4a04eb | ths | { |
715 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
716 | ead9360e | ths | FDT2 = int32_to_float64(WT0, &env->fpu->fp_status); |
717 | fd4a04eb | ths | update_fcr31(); |
718 | fd4a04eb | ths | } |
719 | fd4a04eb | ths | FLOAT_OP(cvtd, l) |
720 | fd4a04eb | ths | { |
721 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
722 | ead9360e | ths | FDT2 = int64_to_float64(DT0, &env->fpu->fp_status); |
723 | fd4a04eb | ths | update_fcr31(); |
724 | fd4a04eb | ths | } |
725 | fd4a04eb | ths | FLOAT_OP(cvtl, d) |
726 | fd4a04eb | ths | { |
727 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
728 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
729 | fd4a04eb | ths | update_fcr31(); |
730 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
731 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
732 | fd4a04eb | ths | } |
733 | fd4a04eb | ths | FLOAT_OP(cvtl, s) |
734 | fd4a04eb | ths | { |
735 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
736 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
737 | fd4a04eb | ths | update_fcr31(); |
738 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
739 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
740 | fd4a04eb | ths | } |
741 | fd4a04eb | ths | |
742 | fd4a04eb | ths | FLOAT_OP(cvtps, pw) |
743 | fd4a04eb | ths | { |
744 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
745 | ead9360e | ths | FST2 = int32_to_float32(WT0, &env->fpu->fp_status); |
746 | ead9360e | ths | FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status); |
747 | fd4a04eb | ths | update_fcr31(); |
748 | fd4a04eb | ths | } |
749 | fd4a04eb | ths | FLOAT_OP(cvtpw, ps) |
750 | fd4a04eb | ths | { |
751 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
752 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
753 | ead9360e | ths | WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status); |
754 | fd4a04eb | ths | update_fcr31(); |
755 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
756 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
757 | fd4a04eb | ths | } |
758 | fd4a04eb | ths | FLOAT_OP(cvts, d) |
759 | fd4a04eb | ths | { |
760 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
761 | ead9360e | ths | FST2 = float64_to_float32(FDT0, &env->fpu->fp_status); |
762 | fd4a04eb | ths | update_fcr31(); |
763 | fd4a04eb | ths | } |
764 | fd4a04eb | ths | FLOAT_OP(cvts, w) |
765 | fd4a04eb | ths | { |
766 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
767 | ead9360e | ths | FST2 = int32_to_float32(WT0, &env->fpu->fp_status); |
768 | fd4a04eb | ths | update_fcr31(); |
769 | fd4a04eb | ths | } |
770 | fd4a04eb | ths | FLOAT_OP(cvts, l) |
771 | fd4a04eb | ths | { |
772 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
773 | ead9360e | ths | FST2 = int64_to_float32(DT0, &env->fpu->fp_status); |
774 | fd4a04eb | ths | update_fcr31(); |
775 | fd4a04eb | ths | } |
776 | fd4a04eb | ths | FLOAT_OP(cvts, pl) |
777 | fd4a04eb | ths | { |
778 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
779 | fd4a04eb | ths | WT2 = WT0; |
780 | fd4a04eb | ths | update_fcr31(); |
781 | fd4a04eb | ths | } |
782 | fd4a04eb | ths | FLOAT_OP(cvts, pu) |
783 | fd4a04eb | ths | { |
784 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
785 | fd4a04eb | ths | WT2 = WTH0; |
786 | fd4a04eb | ths | update_fcr31(); |
787 | fd4a04eb | ths | } |
788 | fd4a04eb | ths | FLOAT_OP(cvtw, s) |
789 | fd4a04eb | ths | { |
790 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
791 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
792 | fd4a04eb | ths | update_fcr31(); |
793 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
794 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
795 | fd4a04eb | ths | } |
796 | fd4a04eb | ths | FLOAT_OP(cvtw, d) |
797 | fd4a04eb | ths | { |
798 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
799 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
800 | fd4a04eb | ths | update_fcr31(); |
801 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
802 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
803 | fd4a04eb | ths | } |
804 | fd4a04eb | ths | |
805 | fd4a04eb | ths | FLOAT_OP(roundl, d) |
806 | fd4a04eb | ths | { |
807 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
808 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
809 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
810 | fd4a04eb | ths | update_fcr31(); |
811 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
812 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
813 | fd4a04eb | ths | } |
814 | fd4a04eb | ths | FLOAT_OP(roundl, s) |
815 | fd4a04eb | ths | { |
816 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
817 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
818 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
819 | fd4a04eb | ths | update_fcr31(); |
820 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
821 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
822 | fd4a04eb | ths | } |
823 | fd4a04eb | ths | FLOAT_OP(roundw, d) |
824 | fd4a04eb | ths | { |
825 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
826 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
827 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
828 | fd4a04eb | ths | update_fcr31(); |
829 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
830 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
831 | fd4a04eb | ths | } |
832 | fd4a04eb | ths | FLOAT_OP(roundw, s) |
833 | fd4a04eb | ths | { |
834 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
835 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
836 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
837 | fd4a04eb | ths | update_fcr31(); |
838 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
839 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
840 | fd4a04eb | ths | } |
841 | fd4a04eb | ths | |
842 | fd4a04eb | ths | FLOAT_OP(truncl, d) |
843 | fd4a04eb | ths | { |
844 | ead9360e | ths | DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status); |
845 | fd4a04eb | ths | update_fcr31(); |
846 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
847 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
848 | fd4a04eb | ths | } |
849 | fd4a04eb | ths | FLOAT_OP(truncl, s) |
850 | fd4a04eb | ths | { |
851 | ead9360e | ths | DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status); |
852 | fd4a04eb | ths | update_fcr31(); |
853 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
854 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
855 | fd4a04eb | ths | } |
856 | fd4a04eb | ths | FLOAT_OP(truncw, d) |
857 | fd4a04eb | ths | { |
858 | ead9360e | ths | WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status); |
859 | fd4a04eb | ths | update_fcr31(); |
860 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
861 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
862 | fd4a04eb | ths | } |
863 | fd4a04eb | ths | FLOAT_OP(truncw, s) |
864 | fd4a04eb | ths | { |
865 | ead9360e | ths | WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status); |
866 | fd4a04eb | ths | update_fcr31(); |
867 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
868 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
869 | fd4a04eb | ths | } |
870 | fd4a04eb | ths | |
871 | fd4a04eb | ths | FLOAT_OP(ceill, d) |
872 | fd4a04eb | ths | { |
873 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
874 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
875 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
876 | fd4a04eb | ths | update_fcr31(); |
877 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
878 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
879 | fd4a04eb | ths | } |
880 | fd4a04eb | ths | FLOAT_OP(ceill, s) |
881 | fd4a04eb | ths | { |
882 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
883 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
884 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
885 | fd4a04eb | ths | update_fcr31(); |
886 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
887 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
888 | fd4a04eb | ths | } |
889 | fd4a04eb | ths | FLOAT_OP(ceilw, d) |
890 | fd4a04eb | ths | { |
891 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
892 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
893 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
894 | fd4a04eb | ths | update_fcr31(); |
895 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
896 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
897 | fd4a04eb | ths | } |
898 | fd4a04eb | ths | FLOAT_OP(ceilw, s) |
899 | fd4a04eb | ths | { |
900 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
901 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
902 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
903 | fd4a04eb | ths | update_fcr31(); |
904 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
905 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
906 | fd4a04eb | ths | } |
907 | fd4a04eb | ths | |
908 | fd4a04eb | ths | FLOAT_OP(floorl, d) |
909 | fd4a04eb | ths | { |
910 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
911 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
912 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
913 | fd4a04eb | ths | update_fcr31(); |
914 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
915 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
916 | fd4a04eb | ths | } |
917 | fd4a04eb | ths | FLOAT_OP(floorl, s) |
918 | fd4a04eb | ths | { |
919 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
920 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
921 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
922 | fd4a04eb | ths | update_fcr31(); |
923 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
924 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
925 | fd4a04eb | ths | } |
926 | fd4a04eb | ths | FLOAT_OP(floorw, d) |
927 | fd4a04eb | ths | { |
928 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
929 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
930 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
931 | fd4a04eb | ths | update_fcr31(); |
932 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
933 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
934 | fd4a04eb | ths | } |
935 | fd4a04eb | ths | FLOAT_OP(floorw, s) |
936 | fd4a04eb | ths | { |
937 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
938 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
939 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
940 | fd4a04eb | ths | update_fcr31(); |
941 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
942 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
943 | fd4a04eb | ths | } |
944 | fd4a04eb | ths | |
945 | 8dfdb87c | ths | /* MIPS specific unary operations */
|
946 | 8dfdb87c | ths | FLOAT_OP(recip, d) |
947 | 8dfdb87c | ths | { |
948 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
949 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status); |
950 | 8dfdb87c | ths | update_fcr31(); |
951 | 8dfdb87c | ths | } |
952 | 8dfdb87c | ths | FLOAT_OP(recip, s) |
953 | 8dfdb87c | ths | { |
954 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
955 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
956 | 8dfdb87c | ths | update_fcr31(); |
957 | 57fa1fb3 | ths | } |
958 | 57fa1fb3 | ths | |
959 | 8dfdb87c | ths | FLOAT_OP(rsqrt, d) |
960 | 8dfdb87c | ths | { |
961 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
962 | ead9360e | ths | FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status); |
963 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status); |
964 | 8dfdb87c | ths | update_fcr31(); |
965 | 8dfdb87c | ths | } |
966 | 8dfdb87c | ths | FLOAT_OP(rsqrt, s) |
967 | 8dfdb87c | ths | { |
968 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
969 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
970 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
971 | 8dfdb87c | ths | update_fcr31(); |
972 | 8dfdb87c | ths | } |
973 | 8dfdb87c | ths | |
974 | 8dfdb87c | ths | FLOAT_OP(recip1, d) |
975 | 8dfdb87c | ths | { |
976 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
977 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status); |
978 | 8dfdb87c | ths | update_fcr31(); |
979 | 8dfdb87c | ths | } |
980 | 8dfdb87c | ths | FLOAT_OP(recip1, s) |
981 | 8dfdb87c | ths | { |
982 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
983 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
984 | 8dfdb87c | ths | update_fcr31(); |
985 | 8dfdb87c | ths | } |
986 | 8dfdb87c | ths | FLOAT_OP(recip1, ps) |
987 | 8dfdb87c | ths | { |
988 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
989 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
990 | ead9360e | ths | FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status); |
991 | 8dfdb87c | ths | update_fcr31(); |
992 | 8dfdb87c | ths | } |
993 | 8dfdb87c | ths | |
994 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, d) |
995 | 8dfdb87c | ths | { |
996 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
997 | ead9360e | ths | FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status); |
998 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status); |
999 | 8dfdb87c | ths | update_fcr31(); |
1000 | 8dfdb87c | ths | } |
1001 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, s) |
1002 | 8dfdb87c | ths | { |
1003 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1004 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
1005 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
1006 | 8dfdb87c | ths | update_fcr31(); |
1007 | 8dfdb87c | ths | } |
1008 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, ps) |
1009 | 8dfdb87c | ths | { |
1010 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1011 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
1012 | ead9360e | ths | FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status); |
1013 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
1014 | ead9360e | ths | FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status); |
1015 | 8dfdb87c | ths | update_fcr31(); |
1016 | 57fa1fb3 | ths | } |
1017 | 57fa1fb3 | ths | |
1018 | fd4a04eb | ths | /* binary operations */
|
1019 | fd4a04eb | ths | #define FLOAT_BINOP(name) \
|
1020 | fd4a04eb | ths | FLOAT_OP(name, d) \ |
1021 | fd4a04eb | ths | { \ |
1022 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1023 | ead9360e | ths | FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \ |
1024 | ead9360e | ths | update_fcr31(); \ |
1025 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
1026 | 54454097 | ths | FDT2 = FLOAT_QNAN64; \ |
1027 | fd4a04eb | ths | } \ |
1028 | fd4a04eb | ths | FLOAT_OP(name, s) \ |
1029 | fd4a04eb | ths | { \ |
1030 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1031 | ead9360e | ths | FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \ |
1032 | ead9360e | ths | update_fcr31(); \ |
1033 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
1034 | 54454097 | ths | FST2 = FLOAT_QNAN32; \ |
1035 | fd4a04eb | ths | } \ |
1036 | fd4a04eb | ths | FLOAT_OP(name, ps) \ |
1037 | fd4a04eb | ths | { \ |
1038 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1039 | ead9360e | ths | FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \ |
1040 | ead9360e | ths | FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \ |
1041 | fd4a04eb | ths | update_fcr31(); \ |
1042 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
|
1043 | 54454097 | ths | FST2 = FLOAT_QNAN32; \ |
1044 | 54454097 | ths | FSTH2 = FLOAT_QNAN32; \ |
1045 | 3a5b360d | ths | } \ |
1046 | fd4a04eb | ths | } |
1047 | fd4a04eb | ths | FLOAT_BINOP(add) |
1048 | fd4a04eb | ths | FLOAT_BINOP(sub) |
1049 | fd4a04eb | ths | FLOAT_BINOP(mul) |
1050 | fd4a04eb | ths | FLOAT_BINOP(div) |
1051 | fd4a04eb | ths | #undef FLOAT_BINOP
|
1052 | fd4a04eb | ths | |
1053 | 8dfdb87c | ths | /* MIPS specific binary operations */
|
1054 | 8dfdb87c | ths | FLOAT_OP(recip2, d) |
1055 | 8dfdb87c | ths | { |
1056 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1057 | ead9360e | ths | FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status); |
1058 | ead9360e | ths | FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status) ^ FLOAT_SIGN64; |
1059 | 8dfdb87c | ths | update_fcr31(); |
1060 | 8dfdb87c | ths | } |
1061 | 8dfdb87c | ths | FLOAT_OP(recip2, s) |
1062 | 8dfdb87c | ths | { |
1063 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1064 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1065 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1066 | 8dfdb87c | ths | update_fcr31(); |
1067 | 8dfdb87c | ths | } |
1068 | 8dfdb87c | ths | FLOAT_OP(recip2, ps) |
1069 | 8dfdb87c | ths | { |
1070 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1071 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1072 | ead9360e | ths | FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status); |
1073 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1074 | ead9360e | ths | FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1075 | 8dfdb87c | ths | update_fcr31(); |
1076 | 8dfdb87c | ths | } |
1077 | 8dfdb87c | ths | |
1078 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, d) |
1079 | 8dfdb87c | ths | { |
1080 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1081 | ead9360e | ths | FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status); |
1082 | ead9360e | ths | FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status); |
1083 | ead9360e | ths | FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status) ^ FLOAT_SIGN64; |
1084 | 8dfdb87c | ths | update_fcr31(); |
1085 | 8dfdb87c | ths | } |
1086 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, s) |
1087 | 8dfdb87c | ths | { |
1088 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1089 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1090 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status); |
1091 | ead9360e | ths | FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1092 | 8dfdb87c | ths | update_fcr31(); |
1093 | 8dfdb87c | ths | } |
1094 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, ps) |
1095 | 8dfdb87c | ths | { |
1096 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1097 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1098 | ead9360e | ths | FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status); |
1099 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status); |
1100 | ead9360e | ths | FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status); |
1101 | ead9360e | ths | FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1102 | ead9360e | ths | FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1103 | 8dfdb87c | ths | update_fcr31(); |
1104 | 57fa1fb3 | ths | } |
1105 | 57fa1fb3 | ths | |
1106 | fd4a04eb | ths | FLOAT_OP(addr, ps) |
1107 | fd4a04eb | ths | { |
1108 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1109 | ead9360e | ths | FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status); |
1110 | ead9360e | ths | FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status); |
1111 | fd4a04eb | ths | update_fcr31(); |
1112 | fd4a04eb | ths | } |
1113 | fd4a04eb | ths | |
1114 | 57fa1fb3 | ths | FLOAT_OP(mulr, ps) |
1115 | 57fa1fb3 | ths | { |
1116 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1117 | ead9360e | ths | FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status); |
1118 | ead9360e | ths | FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status); |
1119 | 57fa1fb3 | ths | update_fcr31(); |
1120 | 57fa1fb3 | ths | } |
1121 | 57fa1fb3 | ths | |
1122 | 8dfdb87c | ths | /* compare operations */
|
1123 | fd4a04eb | ths | #define FOP_COND_D(op, cond) \
|
1124 | fd4a04eb | ths | void do_cmp_d_ ## op (long cc) \ |
1125 | fd4a04eb | ths | { \ |
1126 | fd4a04eb | ths | int c = cond; \
|
1127 | fd4a04eb | ths | update_fcr31(); \ |
1128 | fd4a04eb | ths | if (c) \
|
1129 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1130 | fd4a04eb | ths | else \
|
1131 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1132 | fd4a04eb | ths | } \ |
1133 | fd4a04eb | ths | void do_cmpabs_d_ ## op (long cc) \ |
1134 | fd4a04eb | ths | { \ |
1135 | fd4a04eb | ths | int c; \
|
1136 | 8dfdb87c | ths | FDT0 &= ~FLOAT_SIGN64; \ |
1137 | 8dfdb87c | ths | FDT1 &= ~FLOAT_SIGN64; \ |
1138 | fd4a04eb | ths | c = cond; \ |
1139 | fd4a04eb | ths | update_fcr31(); \ |
1140 | fd4a04eb | ths | if (c) \
|
1141 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1142 | fd4a04eb | ths | else \
|
1143 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1144 | fd4a04eb | ths | } |
1145 | fd4a04eb | ths | |
1146 | fd4a04eb | ths | int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) |
1147 | fd4a04eb | ths | { |
1148 | fd4a04eb | ths | if (float64_is_signaling_nan(a) ||
|
1149 | fd4a04eb | ths | float64_is_signaling_nan(b) || |
1150 | fd4a04eb | ths | (sig && (float64_is_nan(a) || float64_is_nan(b)))) { |
1151 | fd4a04eb | ths | float_raise(float_flag_invalid, status); |
1152 | fd4a04eb | ths | return 1; |
1153 | fd4a04eb | ths | } else if (float64_is_nan(a) || float64_is_nan(b)) { |
1154 | fd4a04eb | ths | return 1; |
1155 | fd4a04eb | ths | } else {
|
1156 | fd4a04eb | ths | return 0; |
1157 | fd4a04eb | ths | } |
1158 | fd4a04eb | ths | } |
1159 | fd4a04eb | ths | |
1160 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1161 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1162 | ead9360e | ths | FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0)) |
1163 | ead9360e | ths | FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
|
1164 | ead9360e | ths | FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1165 | ead9360e | ths | FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1166 | ead9360e | ths | FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1167 | ead9360e | ths | FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1168 | ead9360e | ths | FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1169 | ead9360e | ths | FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1170 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1171 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1172 | ead9360e | ths | FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0)) |
1173 | ead9360e | ths | FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
|
1174 | ead9360e | ths | FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1175 | ead9360e | ths | FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1176 | ead9360e | ths | FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1177 | ead9360e | ths | FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1178 | ead9360e | ths | FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1179 | ead9360e | ths | FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1180 | fd4a04eb | ths | |
1181 | fd4a04eb | ths | #define FOP_COND_S(op, cond) \
|
1182 | fd4a04eb | ths | void do_cmp_s_ ## op (long cc) \ |
1183 | fd4a04eb | ths | { \ |
1184 | fd4a04eb | ths | int c = cond; \
|
1185 | fd4a04eb | ths | update_fcr31(); \ |
1186 | fd4a04eb | ths | if (c) \
|
1187 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1188 | fd4a04eb | ths | else \
|
1189 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1190 | fd4a04eb | ths | } \ |
1191 | fd4a04eb | ths | void do_cmpabs_s_ ## op (long cc) \ |
1192 | fd4a04eb | ths | { \ |
1193 | fd4a04eb | ths | int c; \
|
1194 | 8dfdb87c | ths | FST0 &= ~FLOAT_SIGN32; \ |
1195 | 8dfdb87c | ths | FST1 &= ~FLOAT_SIGN32; \ |
1196 | fd4a04eb | ths | c = cond; \ |
1197 | fd4a04eb | ths | update_fcr31(); \ |
1198 | fd4a04eb | ths | if (c) \
|
1199 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1200 | fd4a04eb | ths | else \
|
1201 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1202 | fd4a04eb | ths | } |
1203 | fd4a04eb | ths | |
1204 | fd4a04eb | ths | flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
|
1205 | fd4a04eb | ths | { |
1206 | fd4a04eb | ths | if (float32_is_signaling_nan(a) ||
|
1207 | fd4a04eb | ths | float32_is_signaling_nan(b) || |
1208 | fd4a04eb | ths | (sig && (float32_is_nan(a) || float32_is_nan(b)))) { |
1209 | fd4a04eb | ths | float_raise(float_flag_invalid, status); |
1210 | fd4a04eb | ths | return 1; |
1211 | fd4a04eb | ths | } else if (float32_is_nan(a) || float32_is_nan(b)) { |
1212 | fd4a04eb | ths | return 1; |
1213 | fd4a04eb | ths | } else {
|
1214 | fd4a04eb | ths | return 0; |
1215 | fd4a04eb | ths | } |
1216 | fd4a04eb | ths | } |
1217 | fd4a04eb | ths | |
1218 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1219 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1220 | ead9360e | ths | FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0)) |
1221 | ead9360e | ths | FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
|
1222 | ead9360e | ths | FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1223 | ead9360e | ths | FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1224 | ead9360e | ths | FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1225 | ead9360e | ths | FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1226 | ead9360e | ths | FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
1227 | ead9360e | ths | FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
1228 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1229 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1230 | ead9360e | ths | FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0)) |
1231 | ead9360e | ths | FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
|
1232 | ead9360e | ths | FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1233 | ead9360e | ths | FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1234 | ead9360e | ths | FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1235 | ead9360e | ths | FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1236 | ead9360e | ths | FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
1237 | ead9360e | ths | FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
1238 | fd4a04eb | ths | |
1239 | fd4a04eb | ths | #define FOP_COND_PS(op, condl, condh) \
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1240 | fd4a04eb | ths | void do_cmp_ps_ ## op (long cc) \ |
1241 | fd4a04eb | ths | { \ |
1242 | fd4a04eb | ths | int cl = condl; \
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1243 | fd4a04eb | ths | int ch = condh; \
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1244 | fd4a04eb | ths | update_fcr31(); \ |
1245 | fd4a04eb | ths | if (cl) \
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1246 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1247 | fd4a04eb | ths | else \
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1248 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1249 | fd4a04eb | ths | if (ch) \
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1250 | ead9360e | ths | SET_FP_COND(cc + 1, env->fpu); \
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1251 | fd4a04eb | ths | else \
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1252 | ead9360e | ths | CLEAR_FP_COND(cc + 1, env->fpu); \
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1253 | fd4a04eb | ths | } \ |
1254 | fd4a04eb | ths | void do_cmpabs_ps_ ## op (long cc) \ |
1255 | fd4a04eb | ths | { \ |
1256 | fd4a04eb | ths | int cl, ch; \
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1257 | 8dfdb87c | ths | FST0 &= ~FLOAT_SIGN32; \ |
1258 | 8dfdb87c | ths | FSTH0 &= ~FLOAT_SIGN32; \ |
1259 | 8dfdb87c | ths | FST1 &= ~FLOAT_SIGN32; \ |
1260 | 8dfdb87c | ths | FSTH1 &= ~FLOAT_SIGN32; \ |
1261 | fd4a04eb | ths | cl = condl; \ |
1262 | fd4a04eb | ths | ch = condh; \ |
1263 | fd4a04eb | ths | update_fcr31(); \ |
1264 | fd4a04eb | ths | if (cl) \
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1265 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1266 | fd4a04eb | ths | else \
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1267 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1268 | fd4a04eb | ths | if (ch) \
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1269 | ead9360e | ths | SET_FP_COND(cc + 1, env->fpu); \
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1270 | fd4a04eb | ths | else \
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1271 | ead9360e | ths | CLEAR_FP_COND(cc + 1, env->fpu); \
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1272 | fd4a04eb | ths | } |
1273 | fd4a04eb | ths | |
1274 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
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1275 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
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1276 | ead9360e | ths | FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0), |
1277 | ead9360e | ths | (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0)) |
1278 | ead9360e | ths | FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
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1279 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
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1280 | ead9360e | ths | FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
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1281 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
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1282 | ead9360e | ths | FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
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1283 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
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1284 | ead9360e | ths | FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
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1285 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
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1286 | ead9360e | ths | FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
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1287 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
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1288 | ead9360e | ths | FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
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1289 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
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1290 | ead9360e | ths | FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
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1291 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
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1292 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
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1293 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
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1294 | ead9360e | ths | FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0), |
1295 | ead9360e | ths | (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0)) |
1296 | ead9360e | ths | FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
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1297 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
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1298 | ead9360e | ths | FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
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1299 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
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1300 | ead9360e | ths | FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
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1301 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
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1302 | ead9360e | ths | FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
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1303 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
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1304 | ead9360e | ths | FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
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1305 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
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1306 | ead9360e | ths | FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
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1307 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
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1308 | ead9360e | ths | FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
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1309 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status)) |