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# Date Author Comment
540635ba 09/30/2007 04:58 am ths

Code provision for n32/n64 mips userland emulation. Not functional yet.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3284 c046a42c-6fe2-441c-8c8c-71466251a162

e189e748 09/24/2007 03:48 pm ths

Per-CPU instruction decoding implementation, by Aurelien Jarno.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3228 c046a42c-6fe2-441c-8c8c-71466251a162

29929e34 05/13/2007 04:49 pm ths

MIPS TLB style selection at runtime, by Herve Poussineau.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2809 c046a42c-6fe2-441c-8c8c-71466251a162

01179c38 04/30/2007 12:26 am ths

Kill broken host register definitions, thanks to Paul Brook and Herve
Poussineau for debugging this.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2747 c046a42c-6fe2-441c-8c8c-71466251a162

19221bda 04/19/2007 07:35 pm ths

Update comment. We can't easily adhere to the architecture spec because
it would involve counting the actually executed instructions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2708 c046a42c-6fe2-441c-8c8c-71466251a162

fcb4a419 04/17/2007 06:26 pm ths

Choose number of TLBs at runtime, by Herve Poussineau.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2693 c046a42c-6fe2-441c-8c8c-71466251a162

b48cfdff 04/11/2007 05:24 am ths

Throw RI for invalid MFMC0-class instructions. Introduce optional
MIPS_STRICT_STANDARD define to adhere more to the spec than it makes
sense in normal operation.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2650 c046a42c-6fe2-441c-8c8c-71466251a162

60aa19ab 04/01/2007 03:36 pm ths

Actually enable 64bit configuration.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2565 c046a42c-6fe2-441c-8c8c-71466251a162

3953d786 03/21/2007 01:04 pm ths

Move mips CPU specific initialization to translate_init.c.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2522 c046a42c-6fe2-441c-8c8c-71466251a162

33d68b5f 03/18/2007 02:30 am ths

MIPS -cpu selection support, by Herve Poussineau.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2491 c046a42c-6fe2-441c-8c8c-71466251a162

36d23958 03/01/2007 12:37 am ths

MIPS FPU dynamic activation, part 1, by Herve Poussineau.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2463 c046a42c-6fe2-441c-8c8c-71466251a162

c570fd16 12/21/2006 03:19 am ths

Preliminiary MIPS64 support, disabled by default due to performance impact.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2250 c046a42c-6fe2-441c-8c8c-71466251a162

7a387fff 12/06/2006 10:17 pm ths

Add MIPS32R2 instructions, and generally straighten out the instruction
decoding. This is also the first percent towards MIPS64 support.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2224 c046a42c-6fe2-441c-8c8c-71466251a162

814b9a47 12/06/2006 07:42 pm ths

MIPS TLB performance improvements, by Daniel Jacobowitz.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2220 c046a42c-6fe2-441c-8c8c-71466251a162

c5d6edc3 06/14/2006 07:49 pm bellard

mips config fixes (initial patch by Stefan Weil)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1977 c046a42c-6fe2-441c-8c8c-71466251a162

6ea83fed 06/14/2006 03:56 pm bellard

MIPS FPU support (Marius Goeger)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1964 c046a42c-6fe2-441c-8c8c-71466251a162

6af0bf9c 07/02/2005 05:58 pm bellard

MIPS target (Jocelyn Mayer)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1464 c046a42c-6fe2-441c-8c8c-71466251a162