/ - Diff - qemu - Greek Research and Technology Network's projects

b/target-mips/exec.h
205	205	FOP_PROTO(ngt)
206	206	#undef FOP_PROTO
207	207
208		static inline void env_to_regs(void)
	208	static always_inline void env_to_regs(void)
209	209	{
210	210	}
211	211
212		static inline void regs_to_env(void)
	212	static always_inline void regs_to_env(void)
213	213	{
214	214	}
215	215
216		static inline int cpu_halted(CPUState *env)
	216	static always_inline int cpu_halted(CPUState *env)
217	217	{
218	218	if (!env->halted)
219	219	return 0;
...	...
225	225	return EXCP_HALTED;
226	226	}
227	227
228		static inline void compute_hflags(CPUState *env)
	228	static always_inline void compute_hflags(CPUState *env)
229	229	{
230	230	env->hflags &= ~(MIPS_HFLAG_64 \| MIPS_HFLAG_CP0 \| MIPS_HFLAG_F64 \|
231	231	MIPS_HFLAG_FPU \| MIPS_HFLAG_UM);

b/target-mips/op.c
812	812
813	813	#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
814	814
815		static inline uint64_t get_HILO (void)
	815	static always_inline uint64_t get_HILO (void)
816	816	{
817	817	return ((uint64_t)env->HI[0][env->current_tc] << 32) \|
818	818	((uint64_t)(uint32_t)env->LO[0][env->current_tc]);
819	819	}
820	820
821		static inline void set_HILO (uint64_t HILO)
	821	static always_inline void set_HILO (uint64_t HILO)
822	822	{
823	823	env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF);
824	824	env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);

b/target-mips/op_helper.c
146	146
147	147	/* 64 bits arithmetic for 32 bits hosts */
148	148	#if TARGET_LONG_BITS > HOST_LONG_BITS
149		static inline uint64_t get_HILO (void)
	149	static always_inline uint64_t get_HILO (void)
150	150	{
151	151	return (env->HI[0][env->current_tc] << 32) \| (uint32_t)env->LO[0][env->current_tc];
152	152	}
153	153
154		static inline void set_HILO (uint64_t HILO)
	154	static always_inline void set_HILO (uint64_t HILO)
155	155	{
156	156	env->LO[0][env->current_tc] = (int32_t)HILO;
157	157	env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
...	...
673	673	do_raise_exception(EXCP_FPE);
674	674	}
675	675
676		inline char ieee_ex_to_mips(char xcpt)
	676	static always_inline char ieee_ex_to_mips(char xcpt)
677	677	{
678	678	return (xcpt & float_flag_inexact) >> 5 \|
679	679	(xcpt & float_flag_underflow) >> 3 \|
...	...
682	682	(xcpt & float_flag_invalid) << 4;
683	683	}
684	684
685		inline char mips_ex_to_ieee(char xcpt)
	685	static always_inline char mips_ex_to_ieee(char xcpt)
686	686	{
687	687	return (xcpt & FP_INEXACT) << 5 \|
688	688	(xcpt & FP_UNDERFLOW) << 3 \|
...	...
691	691	(xcpt & FP_INVALID) >> 4;
692	692	}
693	693
694		inline void update_fcr31(void)
	694	static always_inline void update_fcr31(void)
695	695	{
696	696	int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
697	697

b/target-mips/translate.c
436	436	NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
437	437	NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
438	438	}; \
439		static inline void func(int n) \
	439	static always_inline void func(int n) \
440	440	{ \
441	441	NAME ## _table[n](); \
442	442	}
...	...
470	470	NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
471	471	NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
472	472	}; \
473		static inline void func(int n) \
	473	static always_inline void func(int n) \
474	474	{ \
475	475	NAME ## _table[n](); \
476	476	}
...	...
521	521	gen_op_cmp ## type ## _ ## fmt ## _le, \
522	522	gen_op_cmp ## type ## _ ## fmt ## _ngt, \
523	523	}; \
524		static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
	524	static always_inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
525	525	{ \
526	526	gen_op_cmp ## type ## _ ## fmt ## _table[n](cc); \
527	527	}
...	...
636	636	glue(gen_op_store_fpr_, FTn)(Fn); \
637	637	} while (0)
638	638
639		static inline void gen_save_pc(target_ulong pc)
	639	static always_inline void gen_save_pc(target_ulong pc)
640	640	{
641	641	#if defined(TARGET_MIPSN32) \|\| defined(TARGET_MIPS64)
642	642	if (pc == (int32_t)pc) {
...	...
649	649	#endif
650	650	}
651	651
652		static inline void gen_save_btarget(target_ulong btarget)
	652	static always_inline void gen_save_btarget(target_ulong btarget)
653	653	{
654	654	#if defined(TARGET_MIPSN32) \|\| defined(TARGET_MIPS64)
655	655	if (btarget == (int32_t)btarget) {
...	...
662	662	#endif
663	663	}
664	664
665		static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
	665	static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
666	666	{
667	667	#if defined MIPS_DEBUG_DISAS
668	668	if (loglevel & CPU_LOG_TB_IN_ASM) {
...	...
694	694	}
695	695	}
696	696
697		static inline void restore_cpu_state (CPUState env, DisasContext ctx)
	697	static always_inline void restore_cpu_state (CPUState env, DisasContext ctx)
698	698	{
699	699	ctx->saved_hflags = ctx->hflags;
700	700	switch (ctx->hflags & MIPS_HFLAG_BMASK) {
...	...
712	712	}
713	713	}
714	714
715		static inline void generate_exception_err (DisasContext *ctx, int excp, int err)
	715	static always_inline void generate_exception_err (DisasContext *ctx, int excp, int err)
716	716	{
717	717	#if defined MIPS_DEBUG_DISAS
718	718	if (loglevel & CPU_LOG_TB_IN_ASM)
...	...
726	726	ctx->bstate = BS_EXCP;
727	727	}
728	728
729		static inline void generate_exception (DisasContext *ctx, int excp)
	729	static always_inline void generate_exception (DisasContext *ctx, int excp)
730	730	{
731	731	generate_exception_err (ctx, excp, 0);
732	732	}
733	733
734		static inline void check_cp0_enabled(DisasContext *ctx)
	734	static always_inline void check_cp0_enabled(DisasContext *ctx)
735	735	{
736	736	if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
737	737	generate_exception_err(ctx, EXCP_CpU, 1);
738	738	}
739	739
740		static inline void check_cp1_enabled(DisasContext *ctx)
	740	static always_inline void check_cp1_enabled(DisasContext *ctx)
741	741	{
742	742	if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
743	743	generate_exception_err(ctx, EXCP_CpU, 1);
744	744	}
745	745
746		static inline void check_cp1_64bitmode(DisasContext *ctx)
	746	static always_inline void check_cp1_64bitmode(DisasContext *ctx)
747	747	{
748	748	if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64)))
749	749	generate_exception(ctx, EXCP_RI);
...	...
768	768
769	769	/* This code generates a "reserved instruction" exception if the
770	770	CPU does not support the instruction set corresponding to flags. */
771		static inline void check_insn(CPUState env, DisasContext ctx, int flags)
	771	static always_inline void check_insn(CPUState env, DisasContext ctx, int flags)
772	772	{
773	773	if (unlikely(!(env->insn_flags & flags)))
774	774	generate_exception(ctx, EXCP_RI);
...	...
776	776
777	777	/* This code generates a "reserved instruction" exception if the
778	778	CPU is not MIPS MT capable. */
779		static inline void check_mips_mt(CPUState env, DisasContext ctx)
	779	static always_inline void check_mips_mt(CPUState env, DisasContext ctx)
780	780	{
781	781	if (unlikely(!(env->CP0_Config3 & (1 << CP0C3_MT))))
782	782	generate_exception(ctx, EXCP_RI);
...	...
784	784
785	785	/* This code generates a "reserved instruction" exception if 64-bit
786	786	instructions are not enabled. */
787		static inline void check_mips_64(DisasContext *ctx)
	787	static always_inline void check_mips_64(DisasContext *ctx)
788	788	{
789	789	if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
790	790	generate_exception(ctx, EXCP_RI);
...	...
1634	1634	ctx->bstate = BS_STOP;
1635	1635	}
1636	1636
1637		static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
	1637	static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
1638	1638	{
1639	1639	TranslationBlock *tb;
1640	1640	tb = ctx->tb;
...	...
6477	6477	}
6478	6478	}
6479	6479
6480		static inline int
	6480	static always_inline int
6481	6481	gen_intermediate_code_internal (CPUState env, TranslationBlock tb,
6482	6482	int search_pc)
6483	6483	{

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Revision aa343735