/target-mips/translate.c - Diff - qemu - Greek Research and Technology Network's projects

Revision aa343735 target-mips/translate.c

b/target-mips/translate.c
436	436	NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
437	437	NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
438	438	}; \
439		static inline void func(int n) \
	439	static always_inline void func(int n) \
440	440	{ \
441	441	NAME ## _table[n](); \
442	442	}
...	...
470	470	NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
471	471	NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
472	472	}; \
473		static inline void func(int n) \
	473	static always_inline void func(int n) \
474	474	{ \
475	475	NAME ## _table[n](); \
476	476	}
...	...
521	521	gen_op_cmp ## type ## _ ## fmt ## _le, \
522	522	gen_op_cmp ## type ## _ ## fmt ## _ngt, \
523	523	}; \
524		static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
	524	static always_inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
525	525	{ \
526	526	gen_op_cmp ## type ## _ ## fmt ## _table[n](cc); \
527	527	}
...	...
636	636	glue(gen_op_store_fpr_, FTn)(Fn); \
637	637	} while (0)
638	638
639		static inline void gen_save_pc(target_ulong pc)
	639	static always_inline void gen_save_pc(target_ulong pc)
640	640	{
641	641	#if defined(TARGET_MIPSN32) \|\| defined(TARGET_MIPS64)
642	642	if (pc == (int32_t)pc) {
...	...
649	649	#endif
650	650	}
651	651
652		static inline void gen_save_btarget(target_ulong btarget)
	652	static always_inline void gen_save_btarget(target_ulong btarget)
653	653	{
654	654	#if defined(TARGET_MIPSN32) \|\| defined(TARGET_MIPS64)
655	655	if (btarget == (int32_t)btarget) {
...	...
662	662	#endif
663	663	}
664	664
665		static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
	665	static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
666	666	{
667	667	#if defined MIPS_DEBUG_DISAS
668	668	if (loglevel & CPU_LOG_TB_IN_ASM) {
...	...
694	694	}
695	695	}
696	696
697		static inline void restore_cpu_state (CPUState env, DisasContext ctx)
	697	static always_inline void restore_cpu_state (CPUState env, DisasContext ctx)
698	698	{
699	699	ctx->saved_hflags = ctx->hflags;
700	700	switch (ctx->hflags & MIPS_HFLAG_BMASK) {
...	...
712	712	}
713	713	}
714	714
715		static inline void generate_exception_err (DisasContext *ctx, int excp, int err)
	715	static always_inline void generate_exception_err (DisasContext *ctx, int excp, int err)
716	716	{
717	717	#if defined MIPS_DEBUG_DISAS
718	718	if (loglevel & CPU_LOG_TB_IN_ASM)
...	...
726	726	ctx->bstate = BS_EXCP;
727	727	}
728	728
729		static inline void generate_exception (DisasContext *ctx, int excp)
	729	static always_inline void generate_exception (DisasContext *ctx, int excp)
730	730	{
731	731	generate_exception_err (ctx, excp, 0);
732	732	}
733	733
734		static inline void check_cp0_enabled(DisasContext *ctx)
	734	static always_inline void check_cp0_enabled(DisasContext *ctx)
735	735	{
736	736	if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
737	737	generate_exception_err(ctx, EXCP_CpU, 1);
738	738	}
739	739
740		static inline void check_cp1_enabled(DisasContext *ctx)
	740	static always_inline void check_cp1_enabled(DisasContext *ctx)
741	741	{
742	742	if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
743	743	generate_exception_err(ctx, EXCP_CpU, 1);
744	744	}
745	745
746		static inline void check_cp1_64bitmode(DisasContext *ctx)
	746	static always_inline void check_cp1_64bitmode(DisasContext *ctx)
747	747	{
748	748	if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64)))
749	749	generate_exception(ctx, EXCP_RI);
...	...
768	768
769	769	/* This code generates a "reserved instruction" exception if the
770	770	CPU does not support the instruction set corresponding to flags. */
771		static inline void check_insn(CPUState env, DisasContext ctx, int flags)
	771	static always_inline void check_insn(CPUState env, DisasContext ctx, int flags)
772	772	{
773	773	if (unlikely(!(env->insn_flags & flags)))
774	774	generate_exception(ctx, EXCP_RI);
...	...
776	776
777	777	/* This code generates a "reserved instruction" exception if the
778	778	CPU is not MIPS MT capable. */
779		static inline void check_mips_mt(CPUState env, DisasContext ctx)
	779	static always_inline void check_mips_mt(CPUState env, DisasContext ctx)
780	780	{
781	781	if (unlikely(!(env->CP0_Config3 & (1 << CP0C3_MT))))
782	782	generate_exception(ctx, EXCP_RI);
...	...
784	784
785	785	/* This code generates a "reserved instruction" exception if 64-bit
786	786	instructions are not enabled. */
787		static inline void check_mips_64(DisasContext *ctx)
	787	static always_inline void check_mips_64(DisasContext *ctx)
788	788	{
789	789	if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
790	790	generate_exception(ctx, EXCP_RI);
...	...
1634	1634	ctx->bstate = BS_STOP;
1635	1635	}
1636	1636
1637		static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
	1637	static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
1638	1638	{
1639	1639	TranslationBlock *tb;
1640	1640	tb = ctx->tb;
...	...
6477	6477	}
6478	6478	}
6479	6479
6480		static inline int
	6480	static always_inline int
6481	6481	gen_intermediate_code_internal (CPUState env, TranslationBlock tb,
6482	6482	int search_pc)
6483	6483	{

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Revision aa343735 target-mips/translate.c