Revision aa77bebd tcg/ppc/tcg-target.c
| b/tcg/ppc/tcg-target.c | ||
|---|---|---|
| 369 | 369 |
#define NOR XO31(124) |
| 370 | 370 |
#define ANDC XO31( 60) |
| 371 | 371 |
#define ORC XO31(412) |
| 372 |
#define EQV XO31(284) |
|
| 373 |
#define NAND XO31(476) |
|
| 372 | 374 |
|
| 373 | 375 |
#define LBZX XO31( 87) |
| 374 | 376 |
#define LHZX XO31(279) |
| ... | ... | |
| 1475 | 1477 |
case INDEX_op_orc_i32: |
| 1476 | 1478 |
tcg_out32 (s, ORC | SAB (args[1], args[0], args[2])); |
| 1477 | 1479 |
break; |
| 1480 |
case INDEX_op_eqv_i32: |
|
| 1481 |
tcg_out32 (s, EQV | SAB (args[1], args[0], args[2])); |
|
| 1482 |
break; |
|
| 1483 |
case INDEX_op_nand_i32: |
|
| 1484 |
tcg_out32 (s, NAND | SAB (args[1], args[0], args[2])); |
|
| 1485 |
break; |
|
| 1486 |
case INDEX_op_nor_i32: |
|
| 1487 |
tcg_out32 (s, NOR | SAB (args[1], args[0], args[2])); |
|
| 1488 |
break; |
|
| 1478 | 1489 |
|
| 1479 | 1490 |
case INDEX_op_mul_i32: |
| 1480 | 1491 |
if (const_args[2]) {
|
| ... | ... | |
| 1758 | 1769 |
|
| 1759 | 1770 |
{ INDEX_op_andc_i32, { "r", "r", "r" } },
|
| 1760 | 1771 |
{ INDEX_op_orc_i32, { "r", "r", "r" } },
|
| 1772 |
{ INDEX_op_eqv_i32, { "r", "r", "r" } },
|
|
| 1773 |
{ INDEX_op_nand_i32, { "r", "r", "r" } },
|
|
| 1774 |
{ INDEX_op_nor_i32, { "r", "r", "r" } },
|
|
| 1761 | 1775 |
|
| 1762 | 1776 |
{ INDEX_op_setcond_i32, { "r", "r", "ri" } },
|
| 1763 | 1777 |
{ INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
|
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