Revision aa941b94 hw/pxa2xx.c
| b/hw/pxa2xx.c | ||
|---|---|---|
| 141 | 141 |
pxa2xx_pm_write, |
| 142 | 142 |
}; |
| 143 | 143 |
|
| 144 |
static void pxa2xx_pm_save(QEMUFile *f, void *opaque) |
|
| 145 |
{
|
|
| 146 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 147 |
int i; |
|
| 148 |
|
|
| 149 |
for (i = 0; i < 0x40; i ++) |
|
| 150 |
qemu_put_be32s(f, &s->pm_regs[i]); |
|
| 151 |
} |
|
| 152 |
|
|
| 153 |
static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id) |
|
| 154 |
{
|
|
| 155 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 156 |
int i; |
|
| 157 |
|
|
| 158 |
for (i = 0; i < 0x40; i ++) |
|
| 159 |
qemu_get_be32s(f, &s->pm_regs[i]); |
|
| 160 |
|
|
| 161 |
return 0; |
|
| 162 |
} |
|
| 163 |
|
|
| 144 | 164 |
#define CCCR 0x00 /* Core Clock Configuration register */ |
| 145 | 165 |
#define CKEN 0x04 /* Clock Enable register */ |
| 146 | 166 |
#define OSCC 0x08 /* Oscillator Configuration register */ |
| ... | ... | |
| 204 | 224 |
pxa2xx_cm_write, |
| 205 | 225 |
}; |
| 206 | 226 |
|
| 227 |
static void pxa2xx_cm_save(QEMUFile *f, void *opaque) |
|
| 228 |
{
|
|
| 229 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 230 |
int i; |
|
| 231 |
|
|
| 232 |
for (i = 0; i < 4; i ++) |
|
| 233 |
qemu_put_be32s(f, &s->cm_regs[i]); |
|
| 234 |
qemu_put_be32s(f, &s->clkcfg); |
|
| 235 |
qemu_put_be32s(f, &s->pmnc); |
|
| 236 |
} |
|
| 237 |
|
|
| 238 |
static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id) |
|
| 239 |
{
|
|
| 240 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 241 |
int i; |
|
| 242 |
|
|
| 243 |
for (i = 0; i < 4; i ++) |
|
| 244 |
qemu_get_be32s(f, &s->cm_regs[i]); |
|
| 245 |
qemu_get_be32s(f, &s->clkcfg); |
|
| 246 |
qemu_get_be32s(f, &s->pmnc); |
|
| 247 |
|
|
| 248 |
return 0; |
|
| 249 |
} |
|
| 250 |
|
|
| 207 | 251 |
static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm) |
| 208 | 252 |
{
|
| 209 | 253 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
| ... | ... | |
| 482 | 526 |
pxa2xx_mm_write, |
| 483 | 527 |
}; |
| 484 | 528 |
|
| 529 |
static void pxa2xx_mm_save(QEMUFile *f, void *opaque) |
|
| 530 |
{
|
|
| 531 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 532 |
int i; |
|
| 533 |
|
|
| 534 |
for (i = 0; i < 0x1a; i ++) |
|
| 535 |
qemu_put_be32s(f, &s->mm_regs[i]); |
|
| 536 |
} |
|
| 537 |
|
|
| 538 |
static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id) |
|
| 539 |
{
|
|
| 540 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 541 |
int i; |
|
| 542 |
|
|
| 543 |
for (i = 0; i < 0x1a; i ++) |
|
| 544 |
qemu_get_be32s(f, &s->mm_regs[i]); |
|
| 545 |
|
|
| 546 |
return 0; |
|
| 547 |
} |
|
| 548 |
|
|
| 485 | 549 |
/* Synchronous Serial Ports */ |
| 486 | 550 |
struct pxa2xx_ssp_s {
|
| 487 | 551 |
target_phys_addr_t base; |
| ... | ... | |
| 761 | 825 |
pxa2xx_ssp_write, |
| 762 | 826 |
}; |
| 763 | 827 |
|
| 828 |
static void pxa2xx_ssp_save(QEMUFile *f, void *opaque) |
|
| 829 |
{
|
|
| 830 |
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; |
|
| 831 |
int i; |
|
| 832 |
|
|
| 833 |
qemu_put_be32(f, s->enable); |
|
| 834 |
|
|
| 835 |
qemu_put_be32s(f, &s->sscr[0]); |
|
| 836 |
qemu_put_be32s(f, &s->sscr[1]); |
|
| 837 |
qemu_put_be32s(f, &s->sspsp); |
|
| 838 |
qemu_put_be32s(f, &s->ssto); |
|
| 839 |
qemu_put_be32s(f, &s->ssitr); |
|
| 840 |
qemu_put_be32s(f, &s->sssr); |
|
| 841 |
qemu_put_8s(f, &s->sstsa); |
|
| 842 |
qemu_put_8s(f, &s->ssrsa); |
|
| 843 |
qemu_put_8s(f, &s->ssacd); |
|
| 844 |
|
|
| 845 |
qemu_put_byte(f, s->rx_level); |
|
| 846 |
for (i = 0; i < s->rx_level; i ++) |
|
| 847 |
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]); |
|
| 848 |
} |
|
| 849 |
|
|
| 850 |
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id) |
|
| 851 |
{
|
|
| 852 |
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; |
|
| 853 |
int i; |
|
| 854 |
|
|
| 855 |
s->enable = qemu_get_be32(f); |
|
| 856 |
|
|
| 857 |
qemu_get_be32s(f, &s->sscr[0]); |
|
| 858 |
qemu_get_be32s(f, &s->sscr[1]); |
|
| 859 |
qemu_get_be32s(f, &s->sspsp); |
|
| 860 |
qemu_get_be32s(f, &s->ssto); |
|
| 861 |
qemu_get_be32s(f, &s->ssitr); |
|
| 862 |
qemu_get_be32s(f, &s->sssr); |
|
| 863 |
qemu_get_8s(f, &s->sstsa); |
|
| 864 |
qemu_get_8s(f, &s->ssrsa); |
|
| 865 |
qemu_get_8s(f, &s->ssacd); |
|
| 866 |
|
|
| 867 |
s->rx_level = qemu_get_byte(f); |
|
| 868 |
s->rx_start = 0; |
|
| 869 |
for (i = 0; i < s->rx_level; i ++) |
|
| 870 |
s->rx_fifo[i] = qemu_get_byte(f); |
|
| 871 |
|
|
| 872 |
return 0; |
|
| 873 |
} |
|
| 874 |
|
|
| 764 | 875 |
/* Real-Time Clock */ |
| 765 | 876 |
#define RCNR 0x00 /* RTC Counter register */ |
| 766 | 877 |
#define RTAR 0x04 /* RTC Alarm register */ |
| ... | ... | |
| 1052 | 1163 |
} |
| 1053 | 1164 |
} |
| 1054 | 1165 |
|
| 1055 |
static void pxa2xx_rtc_reset(struct pxa2xx_state_s *s) |
|
| 1166 |
static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
|
|
| 1167 |
pxa2xx_rtc_read, |
|
| 1168 |
pxa2xx_rtc_read, |
|
| 1169 |
pxa2xx_rtc_read, |
|
| 1170 |
}; |
|
| 1171 |
|
|
| 1172 |
static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
|
|
| 1173 |
pxa2xx_rtc_write, |
|
| 1174 |
pxa2xx_rtc_write, |
|
| 1175 |
pxa2xx_rtc_write, |
|
| 1176 |
}; |
|
| 1177 |
|
|
| 1178 |
static void pxa2xx_rtc_init(struct pxa2xx_state_s *s) |
|
| 1056 | 1179 |
{
|
| 1057 | 1180 |
struct tm *tm; |
| 1058 | 1181 |
time_t ti; |
| ... | ... | |
| 1086 | 1209 |
s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s); |
| 1087 | 1210 |
} |
| 1088 | 1211 |
|
| 1089 |
static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
|
|
| 1090 |
pxa2xx_rtc_read, |
|
| 1091 |
pxa2xx_rtc_read, |
|
| 1092 |
pxa2xx_rtc_read, |
|
| 1093 |
}; |
|
| 1212 |
static void pxa2xx_rtc_save(QEMUFile *f, void *opaque) |
|
| 1213 |
{
|
|
| 1214 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 1094 | 1215 |
|
| 1095 |
static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
|
|
| 1096 |
pxa2xx_rtc_write, |
|
| 1097 |
pxa2xx_rtc_write, |
|
| 1098 |
pxa2xx_rtc_write, |
|
| 1099 |
}; |
|
| 1216 |
pxa2xx_rtc_hzupdate(s); |
|
| 1217 |
pxa2xx_rtc_piupdate(s); |
|
| 1218 |
pxa2xx_rtc_swupdate(s); |
|
| 1219 |
|
|
| 1220 |
qemu_put_be32s(f, &s->rttr); |
|
| 1221 |
qemu_put_be32s(f, &s->rtsr); |
|
| 1222 |
qemu_put_be32s(f, &s->rtar); |
|
| 1223 |
qemu_put_be32s(f, &s->rdar1); |
|
| 1224 |
qemu_put_be32s(f, &s->rdar2); |
|
| 1225 |
qemu_put_be32s(f, &s->ryar1); |
|
| 1226 |
qemu_put_be32s(f, &s->ryar2); |
|
| 1227 |
qemu_put_be32s(f, &s->swar1); |
|
| 1228 |
qemu_put_be32s(f, &s->swar2); |
|
| 1229 |
qemu_put_be32s(f, &s->piar); |
|
| 1230 |
qemu_put_be32s(f, &s->last_rcnr); |
|
| 1231 |
qemu_put_be32s(f, &s->last_rdcr); |
|
| 1232 |
qemu_put_be32s(f, &s->last_rycr); |
|
| 1233 |
qemu_put_be32s(f, &s->last_swcr); |
|
| 1234 |
qemu_put_be32s(f, &s->last_rtcpicr); |
|
| 1235 |
qemu_put_be64s(f, &s->last_hz); |
|
| 1236 |
qemu_put_be64s(f, &s->last_sw); |
|
| 1237 |
qemu_put_be64s(f, &s->last_pi); |
|
| 1238 |
} |
|
| 1239 |
|
|
| 1240 |
static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id) |
|
| 1241 |
{
|
|
| 1242 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 1243 |
|
|
| 1244 |
qemu_get_be32s(f, &s->rttr); |
|
| 1245 |
qemu_get_be32s(f, &s->rtsr); |
|
| 1246 |
qemu_get_be32s(f, &s->rtar); |
|
| 1247 |
qemu_get_be32s(f, &s->rdar1); |
|
| 1248 |
qemu_get_be32s(f, &s->rdar2); |
|
| 1249 |
qemu_get_be32s(f, &s->ryar1); |
|
| 1250 |
qemu_get_be32s(f, &s->ryar2); |
|
| 1251 |
qemu_get_be32s(f, &s->swar1); |
|
| 1252 |
qemu_get_be32s(f, &s->swar2); |
|
| 1253 |
qemu_get_be32s(f, &s->piar); |
|
| 1254 |
qemu_get_be32s(f, &s->last_rcnr); |
|
| 1255 |
qemu_get_be32s(f, &s->last_rdcr); |
|
| 1256 |
qemu_get_be32s(f, &s->last_rycr); |
|
| 1257 |
qemu_get_be32s(f, &s->last_swcr); |
|
| 1258 |
qemu_get_be32s(f, &s->last_rtcpicr); |
|
| 1259 |
qemu_get_be64s(f, &s->last_hz); |
|
| 1260 |
qemu_get_be64s(f, &s->last_sw); |
|
| 1261 |
qemu_get_be64s(f, &s->last_pi); |
|
| 1262 |
|
|
| 1263 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
|
| 1264 |
|
|
| 1265 |
return 0; |
|
| 1266 |
} |
|
| 1100 | 1267 |
|
| 1101 | 1268 |
/* I2C Interface */ |
| 1102 | 1269 |
struct pxa2xx_i2c_s {
|
| ... | ... | |
| 1289 | 1456 |
pxa2xx_i2c_write, |
| 1290 | 1457 |
}; |
| 1291 | 1458 |
|
| 1459 |
static void pxa2xx_i2c_save(QEMUFile *f, void *opaque) |
|
| 1460 |
{
|
|
| 1461 |
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; |
|
| 1462 |
|
|
| 1463 |
qemu_put_be16s(f, &s->control); |
|
| 1464 |
qemu_put_be16s(f, &s->status); |
|
| 1465 |
qemu_put_8s(f, &s->ibmr); |
|
| 1466 |
qemu_put_8s(f, &s->data); |
|
| 1467 |
|
|
| 1468 |
i2c_bus_save(f, s->bus); |
|
| 1469 |
i2c_slave_save(f, &s->slave); |
|
| 1470 |
} |
|
| 1471 |
|
|
| 1472 |
static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id) |
|
| 1473 |
{
|
|
| 1474 |
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; |
|
| 1475 |
|
|
| 1476 |
qemu_get_be16s(f, &s->control); |
|
| 1477 |
qemu_get_be16s(f, &s->status); |
|
| 1478 |
qemu_get_8s(f, &s->ibmr); |
|
| 1479 |
qemu_get_8s(f, &s->data); |
|
| 1480 |
|
|
| 1481 |
i2c_bus_load(f, s->bus); |
|
| 1482 |
i2c_slave_load(f, &s->slave); |
|
| 1483 |
return 0; |
|
| 1484 |
} |
|
| 1485 |
|
|
| 1292 | 1486 |
struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base, |
| 1293 | 1487 |
qemu_irq irq, int ioregister) |
| 1294 | 1488 |
{
|
| ... | ... | |
| 1309 | 1503 |
cpu_register_physical_memory(s->base & 0xfffff000, 0xfff, iomemtype); |
| 1310 | 1504 |
} |
| 1311 | 1505 |
|
| 1506 |
register_savevm("pxa2xx_i2c", base, 0,
|
|
| 1507 |
pxa2xx_i2c_save, pxa2xx_i2c_load, s); |
|
| 1508 |
|
|
| 1312 | 1509 |
return s; |
| 1313 | 1510 |
} |
| 1314 | 1511 |
|
| ... | ... | |
| 1470 | 1667 |
pxa2xx_i2s_write, |
| 1471 | 1668 |
}; |
| 1472 | 1669 |
|
| 1670 |
static void pxa2xx_i2s_save(QEMUFile *f, void *opaque) |
|
| 1671 |
{
|
|
| 1672 |
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
|
| 1673 |
|
|
| 1674 |
qemu_put_be32s(f, &s->control[0]); |
|
| 1675 |
qemu_put_be32s(f, &s->control[1]); |
|
| 1676 |
qemu_put_be32s(f, &s->status); |
|
| 1677 |
qemu_put_be32s(f, &s->mask); |
|
| 1678 |
qemu_put_be32s(f, &s->clk); |
|
| 1679 |
|
|
| 1680 |
qemu_put_be32(f, s->enable); |
|
| 1681 |
qemu_put_be32(f, s->rx_len); |
|
| 1682 |
qemu_put_be32(f, s->tx_len); |
|
| 1683 |
qemu_put_be32(f, s->fifo_len); |
|
| 1684 |
} |
|
| 1685 |
|
|
| 1686 |
static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id) |
|
| 1687 |
{
|
|
| 1688 |
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
|
| 1689 |
|
|
| 1690 |
qemu_get_be32s(f, &s->control[0]); |
|
| 1691 |
qemu_get_be32s(f, &s->control[1]); |
|
| 1692 |
qemu_get_be32s(f, &s->status); |
|
| 1693 |
qemu_get_be32s(f, &s->mask); |
|
| 1694 |
qemu_get_be32s(f, &s->clk); |
|
| 1695 |
|
|
| 1696 |
s->enable = qemu_get_be32(f); |
|
| 1697 |
s->rx_len = qemu_get_be32(f); |
|
| 1698 |
s->tx_len = qemu_get_be32(f); |
|
| 1699 |
s->fifo_len = qemu_get_be32(f); |
|
| 1700 |
|
|
| 1701 |
return 0; |
|
| 1702 |
} |
|
| 1703 |
|
|
| 1473 | 1704 |
static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) |
| 1474 | 1705 |
{
|
| 1475 | 1706 |
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
| ... | ... | |
| 1510 | 1741 |
pxa2xx_i2s_writefn, s); |
| 1511 | 1742 |
cpu_register_physical_memory(s->base & 0xfff00000, 0xfffff, iomemtype); |
| 1512 | 1743 |
|
| 1744 |
register_savevm("pxa2xx_i2s", base, 0,
|
|
| 1745 |
pxa2xx_i2s_save, pxa2xx_i2s_load, s); |
|
| 1746 |
|
|
| 1513 | 1747 |
return s; |
| 1514 | 1748 |
} |
| 1515 | 1749 |
|
| ... | ... | |
| 1712 | 1946 |
{
|
| 1713 | 1947 |
} |
| 1714 | 1948 |
|
| 1949 |
static void pxa2xx_fir_save(QEMUFile *f, void *opaque) |
|
| 1950 |
{
|
|
| 1951 |
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
|
| 1952 |
int i; |
|
| 1953 |
|
|
| 1954 |
qemu_put_be32(f, s->enable); |
|
| 1955 |
|
|
| 1956 |
qemu_put_8s(f, &s->control[0]); |
|
| 1957 |
qemu_put_8s(f, &s->control[1]); |
|
| 1958 |
qemu_put_8s(f, &s->control[2]); |
|
| 1959 |
qemu_put_8s(f, &s->status[0]); |
|
| 1960 |
qemu_put_8s(f, &s->status[1]); |
|
| 1961 |
|
|
| 1962 |
qemu_put_byte(f, s->rx_len); |
|
| 1963 |
for (i = 0; i < s->rx_len; i ++) |
|
| 1964 |
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]); |
|
| 1965 |
} |
|
| 1966 |
|
|
| 1967 |
static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) |
|
| 1968 |
{
|
|
| 1969 |
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
|
| 1970 |
int i; |
|
| 1971 |
|
|
| 1972 |
s->enable = qemu_get_be32(f); |
|
| 1973 |
|
|
| 1974 |
qemu_get_8s(f, &s->control[0]); |
|
| 1975 |
qemu_get_8s(f, &s->control[1]); |
|
| 1976 |
qemu_get_8s(f, &s->control[2]); |
|
| 1977 |
qemu_get_8s(f, &s->status[0]); |
|
| 1978 |
qemu_get_8s(f, &s->status[1]); |
|
| 1979 |
|
|
| 1980 |
s->rx_len = qemu_get_byte(f); |
|
| 1981 |
s->rx_start = 0; |
|
| 1982 |
for (i = 0; i < s->rx_len; i ++) |
|
| 1983 |
s->rx_fifo[i] = qemu_get_byte(f); |
|
| 1984 |
|
|
| 1985 |
return 0; |
|
| 1986 |
} |
|
| 1987 |
|
|
| 1715 | 1988 |
static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base, |
| 1716 | 1989 |
qemu_irq irq, struct pxa2xx_dma_state_s *dma, |
| 1717 | 1990 |
CharDriverState *chr) |
| ... | ... | |
| 1735 | 2008 |
qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, |
| 1736 | 2009 |
pxa2xx_fir_rx, pxa2xx_fir_event, s); |
| 1737 | 2010 |
|
| 2011 |
register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save, pxa2xx_fir_load, s);
|
|
| 2012 |
|
|
| 1738 | 2013 |
return s; |
| 1739 | 2014 |
} |
| 1740 | 2015 |
|
| ... | ... | |
| 1763 | 2038 |
|
| 1764 | 2039 |
s->env = cpu_init(); |
| 1765 | 2040 |
cpu_arm_set_model(s->env, revision ?: "pxa270"); |
| 2041 |
register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
|
|
| 1766 | 2042 |
|
| 1767 | 2043 |
/* SDRAM & Internal Memory Storage */ |
| 1768 | 2044 |
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, |
| ... | ... | |
| 1800 | 2076 |
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn, |
| 1801 | 2077 |
pxa2xx_cm_writefn, s); |
| 1802 | 2078 |
cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype); |
| 2079 |
register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
|
|
| 1803 | 2080 |
|
| 1804 | 2081 |
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); |
| 1805 | 2082 |
|
| ... | ... | |
| 1810 | 2087 |
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn, |
| 1811 | 2088 |
pxa2xx_mm_writefn, s); |
| 1812 | 2089 |
cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype); |
| 2090 |
register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
|
|
| 1813 | 2091 |
|
| 1814 | 2092 |
for (i = 0; pxa27x_ssp[i].io_base; i ++); |
| 1815 | 2093 |
s->ssp = (struct pxa2xx_ssp_s **) |
| ... | ... | |
| 1824 | 2102 |
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn, |
| 1825 | 2103 |
pxa2xx_ssp_writefn, &ssp[i]); |
| 1826 | 2104 |
cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype); |
| 2105 |
register_savevm("pxa2xx_ssp", i, 0,
|
|
| 2106 |
pxa2xx_ssp_save, pxa2xx_ssp_load, s); |
|
| 1827 | 2107 |
} |
| 1828 | 2108 |
|
| 1829 | 2109 |
if (usb_enabled) {
|
| ... | ... | |
| 1837 | 2117 |
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn, |
| 1838 | 2118 |
pxa2xx_rtc_writefn, s); |
| 1839 | 2119 |
cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype); |
| 1840 |
pxa2xx_rtc_reset(s); |
|
| 2120 |
pxa2xx_rtc_init(s); |
|
| 2121 |
register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
|
|
| 1841 | 2122 |
|
| 1842 | 2123 |
/* Note that PM registers are in the same page with PWRI2C registers. |
| 1843 | 2124 |
* As a workaround we don't map PWRI2C into memory and we expect |
| ... | ... | |
| 1849 | 2130 |
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn, |
| 1850 | 2131 |
pxa2xx_pm_writefn, s); |
| 1851 | 2132 |
cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype); |
| 2133 |
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
|
|
| 1852 | 2134 |
|
| 1853 | 2135 |
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma); |
| 1854 | 2136 |
|
| ... | ... | |
| 1869 | 2151 |
|
| 1870 | 2152 |
s->env = cpu_init(); |
| 1871 | 2153 |
cpu_arm_set_model(s->env, "pxa255"); |
| 2154 |
register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
|
|
| 1872 | 2155 |
|
| 1873 | 2156 |
/* SDRAM & Internal Memory Storage */ |
| 1874 | 2157 |
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size, |
| ... | ... | |
| 1905 | 2188 |
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn, |
| 1906 | 2189 |
pxa2xx_cm_writefn, s); |
| 1907 | 2190 |
cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype); |
| 2191 |
register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
|
|
| 1908 | 2192 |
|
| 1909 | 2193 |
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); |
| 1910 | 2194 |
|
| ... | ... | |
| 1915 | 2199 |
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn, |
| 1916 | 2200 |
pxa2xx_mm_writefn, s); |
| 1917 | 2201 |
cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype); |
| 2202 |
register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
|
|
| 1918 | 2203 |
|
| 1919 | 2204 |
for (i = 0; pxa255_ssp[i].io_base; i ++); |
| 1920 | 2205 |
s->ssp = (struct pxa2xx_ssp_s **) |
| ... | ... | |
| 1929 | 2214 |
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn, |
| 1930 | 2215 |
pxa2xx_ssp_writefn, &ssp[i]); |
| 1931 | 2216 |
cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype); |
| 2217 |
register_savevm("pxa2xx_ssp", i, 0,
|
|
| 2218 |
pxa2xx_ssp_save, pxa2xx_ssp_load, s); |
|
| 1932 | 2219 |
} |
| 1933 | 2220 |
|
| 1934 | 2221 |
if (usb_enabled) {
|
| ... | ... | |
| 1942 | 2229 |
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn, |
| 1943 | 2230 |
pxa2xx_rtc_writefn, s); |
| 1944 | 2231 |
cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype); |
| 1945 |
pxa2xx_rtc_reset(s); |
|
| 2232 |
pxa2xx_rtc_init(s); |
|
| 2233 |
register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
|
|
| 1946 | 2234 |
|
| 1947 | 2235 |
/* Note that PM registers are in the same page with PWRI2C registers. |
| 1948 | 2236 |
* As a workaround we don't map PWRI2C into memory and we expect |
| ... | ... | |
| 1954 | 2242 |
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn, |
| 1955 | 2243 |
pxa2xx_pm_writefn, s); |
| 1956 | 2244 |
cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype); |
| 2245 |
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
|
|
| 1957 | 2246 |
|
| 1958 | 2247 |
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma); |
| 1959 | 2248 |
|
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