Archipelago » qemu

static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque)

{

    struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;

    int i;

    qemu_put_be32(f, s->irqlevel);

    qemu_put_be32(f, s->transp);

    for (i = 0; i < 6; i ++)

        qemu_put_be32s(f, &s->control[i]);

    for (i = 0; i < 2; i ++)

        qemu_put_be32s(f, &s->status[i]);

    for (i = 0; i < 2; i ++)

        qemu_put_be32s(f, &s->ovl1c[i]);

    for (i = 0; i < 2; i ++)

        qemu_put_be32s(f, &s->ovl2c[i]);

    qemu_put_be32s(f, &s->ccr);

    qemu_put_be32s(f, &s->cmdcr);

    qemu_put_be32s(f, &s->trgbr);

    qemu_put_be32s(f, &s->tcr);

    qemu_put_be32s(f, &s->liidr);

    qemu_put_8s(f, &s->bscntr);

    for (i = 0; i < 7; i ++) {

        qemu_put_betl(f, s->dma_ch[i].branch);

        qemu_put_byte(f, s->dma_ch[i].up);

        qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));

        qemu_put_betl(f, s->dma_ch[i].descriptor);

        qemu_put_betl(f, s->dma_ch[i].source);

        qemu_put_be32s(f, &s->dma_ch[i].id);

        qemu_put_be32s(f, &s->dma_ch[i].command);

    }

}

static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)

{

    struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;

    int i;

    s->irqlevel = qemu_get_be32(f);

    s->transp = qemu_get_be32(f);

    for (i = 0; i < 6; i ++)

        qemu_get_be32s(f, &s->control[i]);

    for (i = 0; i < 2; i ++)

        qemu_get_be32s(f, &s->status[i]);

    for (i = 0; i < 2; i ++)

        qemu_get_be32s(f, &s->ovl1c[i]);

    for (i = 0; i < 2; i ++)

        qemu_get_be32s(f, &s->ovl2c[i]);

    qemu_get_be32s(f, &s->ccr);

    qemu_get_be32s(f, &s->cmdcr);

    qemu_get_be32s(f, &s->trgbr);

    qemu_get_be32s(f, &s->tcr);

    qemu_get_be32s(f, &s->liidr);

    qemu_get_8s(f, &s->bscntr);

    for (i = 0; i < 7; i ++) {

        s->dma_ch[i].branch = qemu_get_betl(f);

        s->dma_ch[i].up = qemu_get_byte(f);

        qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));

        s->dma_ch[i].descriptor = qemu_get_betl(f);

        s->dma_ch[i].source = qemu_get_betl(f);

        qemu_get_be32s(f, &s->dma_ch[i].id);

        qemu_get_be32s(f, &s->dma_ch[i].command);

    }

    s->bpp = LCCR3_BPP(s->control[3]);

    s->xres = s->yres = s->pal_for = -1;

    return 0;

}

    register_savevm("pxa2xx_lcdc", 0, 0,

                    pxa2xx_lcdc_save, pxa2xx_lcdc_load, s);