Revision aa941b94 hw/pxa2xx_pic.c
| b/hw/pxa2xx_pic.c | ||
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| 245 | 245 |
pxa2xx_pic_mem_write, |
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}; |
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static void pxa2xx_pic_save(QEMUFile *f, void *opaque) |
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{
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struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; |
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int i; |
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for (i = 0; i < 2; i ++) |
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qemu_put_be32s(f, &s->int_enabled[i]); |
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for (i = 0; i < 2; i ++) |
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qemu_put_be32s(f, &s->int_pending[i]); |
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for (i = 0; i < 2; i ++) |
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qemu_put_be32s(f, &s->is_fiq[i]); |
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qemu_put_be32s(f, &s->int_idle); |
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for (i = 0; i < PXA2XX_PIC_SRCS; i ++) |
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qemu_put_be32s(f, &s->priority[i]); |
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} |
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static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id) |
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{
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struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; |
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int i; |
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for (i = 0; i < 2; i ++) |
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qemu_get_be32s(f, &s->int_enabled[i]); |
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for (i = 0; i < 2; i ++) |
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qemu_get_be32s(f, &s->int_pending[i]); |
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for (i = 0; i < 2; i ++) |
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qemu_get_be32s(f, &s->is_fiq[i]); |
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qemu_get_be32s(f, &s->int_idle); |
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for (i = 0; i < PXA2XX_PIC_SRCS; i ++) |
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qemu_get_be32s(f, &s->priority[i]); |
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pxa2xx_pic_update(opaque); |
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return 0; |
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} |
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qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env) |
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{
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struct pxa2xx_pic_state_s *s; |
| ... | ... | |
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/* Enable IC coprocessor access. */ |
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cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s); |
| 278 | 313 |
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register_savevm("pxa2xx_pic", 0, 0, pxa2xx_pic_save, pxa2xx_pic_load, s);
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return qi; |
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} |
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