Revision aa941b94 vl.c

b/vl.c
5679 5679

  
5680 5680
#elif defined(TARGET_ARM)
5681 5681

  
5682
/* ??? Need to implement these.  */
5683 5682
void cpu_save(QEMUFile *f, void *opaque)
5684 5683
{
5684
    int i;
5685
    CPUARMState *env = (CPUARMState *)opaque;
5686

  
5687
    for (i = 0; i < 16; i++) {
5688
        qemu_put_be32(f, env->regs[i]);
5689
    }
5690
    qemu_put_be32(f, cpsr_read(env));
5691
    qemu_put_be32(f, env->spsr);
5692
    for (i = 0; i < 6; i++) {
5693
        qemu_put_be32(f, env->banked_spsr[i]);
5694
        qemu_put_be32(f, env->banked_r13[i]);
5695
        qemu_put_be32(f, env->banked_r14[i]);
5696
    }
5697
    for (i = 0; i < 5; i++) {
5698
        qemu_put_be32(f, env->usr_regs[i]);
5699
        qemu_put_be32(f, env->fiq_regs[i]);
5700
    }
5701
    qemu_put_be32(f, env->cp15.c0_cpuid);
5702
    qemu_put_be32(f, env->cp15.c0_cachetype);
5703
    qemu_put_be32(f, env->cp15.c1_sys);
5704
    qemu_put_be32(f, env->cp15.c1_coproc);
5705
    qemu_put_be32(f, env->cp15.c2_base);
5706
    qemu_put_be32(f, env->cp15.c2_data);
5707
    qemu_put_be32(f, env->cp15.c2_insn);
5708
    qemu_put_be32(f, env->cp15.c3);
5709
    qemu_put_be32(f, env->cp15.c5_insn);
5710
    qemu_put_be32(f, env->cp15.c5_data);
5711
    for (i = 0; i < 8; i++) {
5712
        qemu_put_be32(f, env->cp15.c6_region[i]);
5713
    }
5714
    qemu_put_be32(f, env->cp15.c6_insn);
5715
    qemu_put_be32(f, env->cp15.c6_data);
5716
    qemu_put_be32(f, env->cp15.c9_insn);
5717
    qemu_put_be32(f, env->cp15.c9_data);
5718
    qemu_put_be32(f, env->cp15.c13_fcse);
5719
    qemu_put_be32(f, env->cp15.c13_context);
5720
    qemu_put_be32(f, env->cp15.c15_cpar);
5721

  
5722
    qemu_put_be32(f, env->features);
5723

  
5724
    if (arm_feature(env, ARM_FEATURE_VFP)) {
5725
        for (i = 0;  i < 16; i++) {
5726
            CPU_DoubleU u;
5727
            u.d = env->vfp.regs[i];
5728
            qemu_put_be32(f, u.l.upper);
5729
            qemu_put_be32(f, u.l.lower);
5730
        }
5731
        for (i = 0; i < 16; i++) {
5732
            qemu_put_be32(f, env->vfp.xregs[i]);
5733
        }
5734

  
5735
        /* TODO: Should use proper FPSCR access functions.  */
5736
        qemu_put_be32(f, env->vfp.vec_len);
5737
        qemu_put_be32(f, env->vfp.vec_stride);
5738
    }
5739

  
5740
    if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5741
        for (i = 0; i < 16; i++) {
5742
            qemu_put_be64(f, env->iwmmxt.regs[i]);
5743
        }
5744
        for (i = 0; i < 16; i++) {
5745
            qemu_put_be32(f, env->iwmmxt.cregs[i]);
5746
        }
5747
    }
5685 5748
}
5686 5749

  
5687 5750
int cpu_load(QEMUFile *f, void *opaque, int version_id)
5688 5751
{
5752
    CPUARMState *env = (CPUARMState *)opaque;
5753
    int i;
5754

  
5755
    if (version_id != 0)
5756
        return -EINVAL;
5757

  
5758
    for (i = 0; i < 16; i++) {
5759
        env->regs[i] = qemu_get_be32(f);
5760
    }
5761
    cpsr_write(env, qemu_get_be32(f), 0xffffffff);
5762
    env->spsr = qemu_get_be32(f);
5763
    for (i = 0; i < 6; i++) {
5764
        env->banked_spsr[i] = qemu_get_be32(f);
5765
        env->banked_r13[i] = qemu_get_be32(f);
5766
        env->banked_r14[i] = qemu_get_be32(f);
5767
    }
5768
    for (i = 0; i < 5; i++) {
5769
        env->usr_regs[i] = qemu_get_be32(f);
5770
        env->fiq_regs[i] = qemu_get_be32(f);
5771
    }
5772
    env->cp15.c0_cpuid = qemu_get_be32(f);
5773
    env->cp15.c0_cachetype = qemu_get_be32(f);
5774
    env->cp15.c1_sys = qemu_get_be32(f);
5775
    env->cp15.c1_coproc = qemu_get_be32(f);
5776
    env->cp15.c2_base = qemu_get_be32(f);
5777
    env->cp15.c2_data = qemu_get_be32(f);
5778
    env->cp15.c2_insn = qemu_get_be32(f);
5779
    env->cp15.c3 = qemu_get_be32(f);
5780
    env->cp15.c5_insn = qemu_get_be32(f);
5781
    env->cp15.c5_data = qemu_get_be32(f);
5782
    for (i = 0; i < 8; i++) {
5783
        env->cp15.c6_region[i] = qemu_get_be32(f);
5784
    }
5785
    env->cp15.c6_insn = qemu_get_be32(f);
5786
    env->cp15.c6_data = qemu_get_be32(f);
5787
    env->cp15.c9_insn = qemu_get_be32(f);
5788
    env->cp15.c9_data = qemu_get_be32(f);
5789
    env->cp15.c13_fcse = qemu_get_be32(f);
5790
    env->cp15.c13_context = qemu_get_be32(f);
5791
    env->cp15.c15_cpar = qemu_get_be32(f);
5792

  
5793
    env->features = qemu_get_be32(f);
5794

  
5795
    if (arm_feature(env, ARM_FEATURE_VFP)) {
5796
        for (i = 0;  i < 16; i++) {
5797
            CPU_DoubleU u;
5798
            u.l.upper = qemu_get_be32(f);
5799
            u.l.lower = qemu_get_be32(f);
5800
            env->vfp.regs[i] = u.d;
5801
        }
5802
        for (i = 0; i < 16; i++) {
5803
            env->vfp.xregs[i] = qemu_get_be32(f);
5804
        }
5805

  
5806
        /* TODO: Should use proper FPSCR access functions.  */
5807
        env->vfp.vec_len = qemu_get_be32(f);
5808
        env->vfp.vec_stride = qemu_get_be32(f);
5809
    }
5810

  
5811
    if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5812
        for (i = 0; i < 16; i++) {
5813
            env->iwmmxt.regs[i] = qemu_get_be64(f);
5814
        }
5815
        for (i = 0; i < 16; i++) {
5816
            env->iwmmxt.cregs[i] = qemu_get_be32(f);
5817
        }
5818
    }
5819

  
5689 5820
    return 0;
5690 5821
}
5691 5822

  

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