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/*
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* PXA270-based Clamshell PDA platforms.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GNU GPL v2.
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*/
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#include "vl.h" |
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#define spitz_printf(format, ...) \
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fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__) |
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#undef REG_FMT
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#define REG_FMT "0x%02lx" |
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/* Spitz Flash */
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#define FLASH_BASE 0x0c000000 |
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#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ |
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#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */ |
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#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */ |
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#define FLASH_ECCCNTR 0x0c /* ECC byte counter */ |
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#define FLASH_ECCCLRR 0x10 /* Clear ECC */ |
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#define FLASH_FLASHIO 0x14 /* Flash I/O */ |
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#define FLASH_FLASHCTL 0x18 /* Flash Control */ |
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#define FLASHCTL_CE0 (1 << 0) |
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#define FLASHCTL_CLE (1 << 1) |
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#define FLASHCTL_ALE (1 << 2) |
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#define FLASHCTL_WP (1 << 3) |
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#define FLASHCTL_CE1 (1 << 4) |
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#define FLASHCTL_RYBY (1 << 5) |
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#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
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struct sl_nand_s {
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target_phys_addr_t target_base; |
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struct nand_flash_s *nand;
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uint8_t ctl; |
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struct ecc_state_s ecc;
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}; |
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static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
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int ryby;
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addr -= s->target_base; |
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switch (addr) {
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#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to)) |
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case FLASH_ECCLPLB:
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return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) | |
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BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7); |
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#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to)) |
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case FLASH_ECCLPUB:
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return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) | |
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BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7); |
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case FLASH_ECCCP:
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return s->ecc.cp;
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case FLASH_ECCCNTR:
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return s->ecc.count & 0xff; |
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|
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case FLASH_FLASHCTL:
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nand_getpins(s->nand, &ryby); |
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if (ryby)
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return s->ctl | FLASHCTL_RYBY;
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else
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return s->ctl;
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case FLASH_FLASHIO:
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return ecc_digest(&s->ecc, nand_getio(s->nand));
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default:
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spitz_printf("Bad register offset " REG_FMT "\n", addr); |
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} |
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return 0; |
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} |
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static void sl_writeb(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
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addr -= s->target_base; |
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switch (addr) {
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case FLASH_ECCCLRR:
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/* Value is ignored. */
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ecc_reset(&s->ecc); |
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break;
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case FLASH_FLASHCTL:
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s->ctl = value & 0xff & ~FLASHCTL_RYBY;
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nand_setpins(s->nand, |
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s->ctl & FLASHCTL_CLE, |
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s->ctl & FLASHCTL_ALE, |
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s->ctl & FLASHCTL_NCE, |
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s->ctl & FLASHCTL_WP, |
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0);
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break;
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case FLASH_FLASHIO:
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nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
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break;
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default:
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spitz_printf("Bad register offset " REG_FMT "\n", addr); |
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} |
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} |
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static void sl_save(QEMUFile *f, void *opaque) |
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{ |
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struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
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qemu_put_8s(f, &s->ctl); |
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ecc_put(f, &s->ecc); |
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} |
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static int sl_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
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qemu_get_8s(f, &s->ctl); |
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ecc_get(f, &s->ecc); |
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return 0; |
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} |
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enum {
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FLASH_128M, |
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FLASH_1024M, |
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}; |
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static void sl_flash_register(struct pxa2xx_state_s *cpu, int size) |
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{ |
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int iomemtype;
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struct sl_nand_s *s;
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CPUReadMemoryFunc *sl_readfn[] = { |
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sl_readb, |
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sl_readb, |
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sl_readb, |
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}; |
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CPUWriteMemoryFunc *sl_writefn[] = { |
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sl_writeb, |
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sl_writeb, |
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sl_writeb, |
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}; |
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s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s)); |
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s->target_base = FLASH_BASE; |
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s->ctl = 0;
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if (size == FLASH_128M)
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s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
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else if (size == FLASH_1024M) |
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s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
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iomemtype = cpu_register_io_memory(0, sl_readfn,
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sl_writefn, s); |
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cpu_register_physical_memory(s->target_base, 0x40, iomemtype);
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register_savevm("sl_flash", 0, 0, sl_save, sl_load, s); |
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} |
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/* Spitz Keyboard */
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|
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#define SPITZ_KEY_STROBE_NUM 11 |
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#define SPITZ_KEY_SENSE_NUM 7 |
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|
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static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = { |
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12, 17, 91, 34, 36, 38, 39 |
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}; |
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static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = { |
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88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 |
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}; |
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/* Eighth additional row maps the special keys */
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static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = { |
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{ 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 }, |
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{ -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 }, |
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{ 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 }, |
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{ 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 }, |
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{ 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 }, |
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{ 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x3d }, |
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{ 0x37, 0x38, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 }, |
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{ 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 }, |
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}; |
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#define SPITZ_GPIO_AK_INT 13 /* Remote control */ |
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#define SPITZ_GPIO_SYNC 16 /* Sync button */ |
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#define SPITZ_GPIO_ON_KEY 95 /* Power button */ |
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#define SPITZ_GPIO_SWA 97 /* Lid */ |
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#define SPITZ_GPIO_SWB 96 /* Tablet mode */ |
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|
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/* The special buttons are mapped to unused keys */
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static const int spitz_gpiomap[5] = { |
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SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY, |
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SPITZ_GPIO_SWA, SPITZ_GPIO_SWB, |
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}; |
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static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, }; |
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struct spitz_keyboard_s {
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struct pxa2xx_state_s *cpu;
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int keymap[0x80]; |
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uint16_t keyrow[SPITZ_KEY_SENSE_NUM]; |
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uint16_t strobe_state; |
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uint16_t sense_state; |
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uint16_t pre_map[0x100];
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uint16_t modifiers; |
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uint16_t imodifiers; |
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uint8_t fifo[16];
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int fifopos, fifolen;
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QEMUTimer *kbdtimer; |
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}; |
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static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s) |
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{ |
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int i;
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uint16_t strobe, sense = 0;
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for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) { |
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strobe = s->keyrow[i] & s->strobe_state; |
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if (strobe) {
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sense |= 1 << i;
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if (!(s->sense_state & (1 << i))) |
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pxa2xx_gpio_set(s->cpu->gpio, spitz_gpio_key_sense[i], 1);
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} else if (s->sense_state & (1 << i)) |
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pxa2xx_gpio_set(s->cpu->gpio, spitz_gpio_key_sense[i], 0);
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} |
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s->sense_state = sense; |
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} |
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static void spitz_keyboard_strobe(int line, int level, |
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struct spitz_keyboard_s *s)
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{ |
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int i;
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for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++) |
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if (spitz_gpio_key_strobe[i] == line) {
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if (level)
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s->strobe_state |= 1 << i;
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else
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s->strobe_state &= ~(1 << i);
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spitz_keyboard_sense_update(s); |
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break;
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} |
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} |
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static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode) |
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{ |
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int spitz_keycode = s->keymap[keycode & 0x7f]; |
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if (spitz_keycode == -1) |
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return;
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/* Handle the additional keys */
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if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) { |
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pxa2xx_gpio_set(s->cpu->gpio, spitz_gpiomap[spitz_keycode & 0xf],
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(keycode < 0x80) ^
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spitz_gpio_invert[spitz_keycode & 0xf]);
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return;
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} |
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if (keycode & 0x80) |
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s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf)); |
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else
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s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf); |
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spitz_keyboard_sense_update(s); |
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} |
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|
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#define SHIFT (1 << 7) |
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#define CTRL (1 << 8) |
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#define FN (1 << 9) |
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|
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#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c |
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|
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static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode) |
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{ |
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uint16_t code; |
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int mapcode;
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switch (keycode) {
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case 0x2a: /* Left Shift */ |
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s->modifiers |= 1;
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break;
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case 0xaa: |
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s->modifiers &= ~1;
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break;
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case 0x36: /* Right Shift */ |
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s->modifiers |= 2;
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break;
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case 0xb6: |
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s->modifiers &= ~2;
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break;
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case 0x1d: /* Control */ |
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s->modifiers |= 4;
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break;
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case 0x9d: |
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s->modifiers &= ~4;
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break;
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case 0x38: /* Alt */ |
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s->modifiers |= 8;
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break;
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case 0xb8: |
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s->modifiers &= ~8;
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break;
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} |
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code = s->pre_map[mapcode = ((s->modifiers & 3) ?
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(keycode | SHIFT) : |
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(keycode & ~SHIFT))]; |
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if (code != mapcode) {
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#if 0
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if ((code & SHIFT) && !(s->modifiers & 1))
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QUEUE_KEY(0x2a | (keycode & 0x80));
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if ((code & CTRL ) && !(s->modifiers & 4))
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QUEUE_KEY(0x1d | (keycode & 0x80));
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if ((code & FN ) && !(s->modifiers & 8))
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QUEUE_KEY(0x38 | (keycode & 0x80));
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if ((code & FN ) && (s->modifiers & 1))
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QUEUE_KEY(0x2a | (~keycode & 0x80));
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if ((code & FN ) && (s->modifiers & 2))
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QUEUE_KEY(0x36 | (~keycode & 0x80));
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#else
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if (keycode & 0x80) { |
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if ((s->imodifiers & 1 ) && !(s->modifiers & 1)) |
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QUEUE_KEY(0x2a | 0x80); |
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if ((s->imodifiers & 4 ) && !(s->modifiers & 4)) |
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QUEUE_KEY(0x1d | 0x80); |
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if ((s->imodifiers & 8 ) && !(s->modifiers & 8)) |
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QUEUE_KEY(0x38 | 0x80); |
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if ((s->imodifiers & 0x10) && (s->modifiers & 1)) |
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QUEUE_KEY(0x2a);
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if ((s->imodifiers & 0x20) && (s->modifiers & 2)) |
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QUEUE_KEY(0x36);
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s->imodifiers = 0;
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} else {
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if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) { |
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QUEUE_KEY(0x2a);
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s->imodifiers |= 1;
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} |
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if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) { |
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QUEUE_KEY(0x1d);
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s->imodifiers |= 4;
|
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} |
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if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) { |
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QUEUE_KEY(0x38);
|
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s->imodifiers |= 8;
|
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} |
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if ((code & FN ) && (s->modifiers & 1) && |
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!(s->imodifiers & 0x10)) {
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QUEUE_KEY(0x2a | 0x80); |
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s->imodifiers |= 0x10;
|
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} |
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if ((code & FN ) && (s->modifiers & 2) && |
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!(s->imodifiers & 0x20)) {
|
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QUEUE_KEY(0x36 | 0x80); |
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s->imodifiers |= 0x20;
|
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} |
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} |
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#endif
|
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} |
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|
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QUEUE_KEY((code & 0x7f) | (keycode & 0x80)); |
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} |
368 |
|
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static void spitz_keyboard_tick(void *opaque) |
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{ |
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struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
372 |
|
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if (s->fifolen) {
|
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spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]); |
375 |
s->fifolen --; |
376 |
if (s->fifopos >= 16) |
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s->fifopos = 0;
|
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} |
379 |
|
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qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
|
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} |
382 |
|
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static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s) |
384 |
{ |
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int i;
|
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for (i = 0; i < 0x100; i ++) |
387 |
s->pre_map[i] = i; |
388 |
s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */ |
389 |
s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */ |
390 |
s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */ |
391 |
s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */ |
392 |
s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */ |
393 |
s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */ |
394 |
s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */ |
395 |
s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */ |
396 |
s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */ |
397 |
s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */ |
398 |
s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */ |
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s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */ |
400 |
s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */ |
401 |
s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */ |
402 |
s->pre_map[0x0d ] = 0x12 | FN; /* equal */ |
403 |
s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */ |
404 |
s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */ |
405 |
s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */ |
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s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */ |
407 |
s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */ |
408 |
s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */ |
409 |
s->pre_map[0x2b ] = 0x25 | FN; /* backslash */ |
410 |
s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */ |
411 |
s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */ |
412 |
s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */ |
413 |
s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */ |
414 |
s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */ |
415 |
s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */ |
416 |
|
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s->modifiers = 0;
|
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s->imodifiers = 0;
|
419 |
s->fifopos = 0;
|
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s->fifolen = 0;
|
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s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s); |
422 |
spitz_keyboard_tick(s); |
423 |
} |
424 |
|
425 |
#undef SHIFT
|
426 |
#undef CTRL
|
427 |
#undef FN
|
428 |
|
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static void spitz_keyboard_save(QEMUFile *f, void *opaque) |
430 |
{ |
431 |
struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
432 |
int i;
|
433 |
|
434 |
qemu_put_be16s(f, &s->sense_state); |
435 |
qemu_put_be16s(f, &s->strobe_state); |
436 |
for (i = 0; i < 5; i ++) |
437 |
qemu_put_byte(f, spitz_gpio_invert[i]); |
438 |
} |
439 |
|
440 |
static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id) |
441 |
{ |
442 |
struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
443 |
int i;
|
444 |
|
445 |
qemu_get_be16s(f, &s->sense_state); |
446 |
qemu_get_be16s(f, &s->strobe_state); |
447 |
for (i = 0; i < 5; i ++) |
448 |
spitz_gpio_invert[i] = qemu_get_byte(f); |
449 |
|
450 |
/* Release all pressed keys */
|
451 |
memset(s->keyrow, 0, sizeof(s->keyrow)); |
452 |
spitz_keyboard_sense_update(s); |
453 |
s->modifiers = 0;
|
454 |
s->imodifiers = 0;
|
455 |
s->fifopos = 0;
|
456 |
s->fifolen = 0;
|
457 |
|
458 |
return 0; |
459 |
} |
460 |
|
461 |
static void spitz_keyboard_register(struct pxa2xx_state_s *cpu) |
462 |
{ |
463 |
int i, j;
|
464 |
struct spitz_keyboard_s *s;
|
465 |
|
466 |
s = (struct spitz_keyboard_s *)
|
467 |
qemu_mallocz(sizeof(struct spitz_keyboard_s)); |
468 |
memset(s, 0, sizeof(struct spitz_keyboard_s)); |
469 |
s->cpu = cpu; |
470 |
|
471 |
for (i = 0; i < 0x80; i ++) |
472 |
s->keymap[i] = -1;
|
473 |
for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++) |
474 |
for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++) |
475 |
if (spitz_keymap[i][j] != -1) |
476 |
s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
|
477 |
|
478 |
for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++) |
479 |
pxa2xx_gpio_handler_set(cpu->gpio, spitz_gpio_key_strobe[i], |
480 |
(gpio_handler_t) spitz_keyboard_strobe, s); |
481 |
|
482 |
spitz_keyboard_pre_map(s); |
483 |
qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s); |
484 |
|
485 |
register_savevm("spitz_keyboard", 0, 0, |
486 |
spitz_keyboard_save, spitz_keyboard_load, s); |
487 |
} |
488 |
|
489 |
/* SCOOP devices */
|
490 |
|
491 |
struct scoop_info_s {
|
492 |
target_phys_addr_t target_base; |
493 |
uint16_t status; |
494 |
uint16_t power; |
495 |
uint32_t gpio_level; |
496 |
uint32_t gpio_dir; |
497 |
uint32_t prev_level; |
498 |
struct {
|
499 |
gpio_handler_t fn; |
500 |
void *opaque;
|
501 |
} handler[16];
|
502 |
|
503 |
uint16_t mcr; |
504 |
uint16_t cdr; |
505 |
uint16_t ccr; |
506 |
uint16_t irr; |
507 |
uint16_t imr; |
508 |
uint16_t isr; |
509 |
uint16_t gprr; |
510 |
}; |
511 |
|
512 |
#define SCOOP_MCR 0x00 |
513 |
#define SCOOP_CDR 0x04 |
514 |
#define SCOOP_CSR 0x08 |
515 |
#define SCOOP_CPR 0x0c |
516 |
#define SCOOP_CCR 0x10 |
517 |
#define SCOOP_IRR_IRM 0x14 |
518 |
#define SCOOP_IMR 0x18 |
519 |
#define SCOOP_ISR 0x1c |
520 |
#define SCOOP_GPCR 0x20 |
521 |
#define SCOOP_GPWR 0x24 |
522 |
#define SCOOP_GPRR 0x28 |
523 |
|
524 |
static inline void scoop_gpio_handler_update(struct scoop_info_s *s) { |
525 |
uint32_t level, diff; |
526 |
int bit;
|
527 |
level = s->gpio_level & s->gpio_dir; |
528 |
|
529 |
for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { |
530 |
bit = ffs(diff) - 1;
|
531 |
if (s->handler[bit].fn)
|
532 |
s->handler[bit].fn(bit, (level >> bit) & 1,
|
533 |
s->handler[bit].opaque); |
534 |
} |
535 |
|
536 |
s->prev_level = level; |
537 |
} |
538 |
|
539 |
static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr) |
540 |
{ |
541 |
struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
542 |
addr -= s->target_base; |
543 |
|
544 |
switch (addr) {
|
545 |
case SCOOP_MCR:
|
546 |
return s->mcr;
|
547 |
case SCOOP_CDR:
|
548 |
return s->cdr;
|
549 |
case SCOOP_CSR:
|
550 |
return s->status;
|
551 |
case SCOOP_CPR:
|
552 |
return s->power;
|
553 |
case SCOOP_CCR:
|
554 |
return s->ccr;
|
555 |
case SCOOP_IRR_IRM:
|
556 |
return s->irr;
|
557 |
case SCOOP_IMR:
|
558 |
return s->imr;
|
559 |
case SCOOP_ISR:
|
560 |
return s->isr;
|
561 |
case SCOOP_GPCR:
|
562 |
return s->gpio_dir;
|
563 |
case SCOOP_GPWR:
|
564 |
return s->gpio_level;
|
565 |
case SCOOP_GPRR:
|
566 |
return s->gprr;
|
567 |
default:
|
568 |
spitz_printf("Bad register offset " REG_FMT "\n", addr); |
569 |
} |
570 |
|
571 |
return 0; |
572 |
} |
573 |
|
574 |
static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) |
575 |
{ |
576 |
struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
577 |
addr -= s->target_base; |
578 |
value &= 0xffff;
|
579 |
|
580 |
switch (addr) {
|
581 |
case SCOOP_MCR:
|
582 |
s->mcr = value; |
583 |
break;
|
584 |
case SCOOP_CDR:
|
585 |
s->cdr = value; |
586 |
break;
|
587 |
case SCOOP_CPR:
|
588 |
s->power = value; |
589 |
if (value & 0x80) |
590 |
s->power |= 0x8040;
|
591 |
break;
|
592 |
case SCOOP_CCR:
|
593 |
s->ccr = value; |
594 |
break;
|
595 |
case SCOOP_IRR_IRM:
|
596 |
s->irr = value; |
597 |
break;
|
598 |
case SCOOP_IMR:
|
599 |
s->imr = value; |
600 |
break;
|
601 |
case SCOOP_ISR:
|
602 |
s->isr = value; |
603 |
break;
|
604 |
case SCOOP_GPCR:
|
605 |
s->gpio_dir = value; |
606 |
scoop_gpio_handler_update(s); |
607 |
break;
|
608 |
case SCOOP_GPWR:
|
609 |
s->gpio_level = value & s->gpio_dir; |
610 |
scoop_gpio_handler_update(s); |
611 |
break;
|
612 |
case SCOOP_GPRR:
|
613 |
s->gprr = value; |
614 |
break;
|
615 |
default:
|
616 |
spitz_printf("Bad register offset " REG_FMT "\n", addr); |
617 |
} |
618 |
} |
619 |
|
620 |
CPUReadMemoryFunc *scoop_readfn[] = { |
621 |
scoop_readb, |
622 |
scoop_readb, |
623 |
scoop_readb, |
624 |
}; |
625 |
CPUWriteMemoryFunc *scoop_writefn[] = { |
626 |
scoop_writeb, |
627 |
scoop_writeb, |
628 |
scoop_writeb, |
629 |
}; |
630 |
|
631 |
static inline void scoop_gpio_set(struct scoop_info_s *s, int line, int level) |
632 |
{ |
633 |
if (line >= 16) { |
634 |
spitz_printf("No GPIO pin %i\n", line);
|
635 |
return;
|
636 |
} |
637 |
|
638 |
if (level)
|
639 |
s->gpio_level |= (1 << line);
|
640 |
else
|
641 |
s->gpio_level &= ~(1 << line);
|
642 |
} |
643 |
|
644 |
static inline void scoop_gpio_handler_set(struct scoop_info_s *s, int line, |
645 |
gpio_handler_t handler, void *opaque) {
|
646 |
if (line >= 16) { |
647 |
spitz_printf("No GPIO pin %i\n", line);
|
648 |
return;
|
649 |
} |
650 |
|
651 |
s->handler[line].fn = handler; |
652 |
s->handler[line].opaque = opaque; |
653 |
} |
654 |
|
655 |
static void scoop_save(QEMUFile *f, void *opaque) |
656 |
{ |
657 |
struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
658 |
qemu_put_be16s(f, &s->status); |
659 |
qemu_put_be16s(f, &s->power); |
660 |
qemu_put_be32s(f, &s->gpio_level); |
661 |
qemu_put_be32s(f, &s->gpio_dir); |
662 |
qemu_put_be32s(f, &s->prev_level); |
663 |
qemu_put_be16s(f, &s->mcr); |
664 |
qemu_put_be16s(f, &s->cdr); |
665 |
qemu_put_be16s(f, &s->ccr); |
666 |
qemu_put_be16s(f, &s->irr); |
667 |
qemu_put_be16s(f, &s->imr); |
668 |
qemu_put_be16s(f, &s->isr); |
669 |
qemu_put_be16s(f, &s->gprr); |
670 |
} |
671 |
|
672 |
static int scoop_load(QEMUFile *f, void *opaque, int version_id) |
673 |
{ |
674 |
struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
675 |
qemu_get_be16s(f, &s->status); |
676 |
qemu_get_be16s(f, &s->power); |
677 |
qemu_get_be32s(f, &s->gpio_level); |
678 |
qemu_get_be32s(f, &s->gpio_dir); |
679 |
qemu_get_be32s(f, &s->prev_level); |
680 |
qemu_get_be16s(f, &s->mcr); |
681 |
qemu_get_be16s(f, &s->cdr); |
682 |
qemu_get_be16s(f, &s->ccr); |
683 |
qemu_get_be16s(f, &s->irr); |
684 |
qemu_get_be16s(f, &s->imr); |
685 |
qemu_get_be16s(f, &s->isr); |
686 |
qemu_get_be16s(f, &s->gprr); |
687 |
|
688 |
return 0; |
689 |
} |
690 |
|
691 |
static struct scoop_info_s *spitz_scoop_init(struct pxa2xx_state_s *cpu, |
692 |
int count) {
|
693 |
int iomemtype;
|
694 |
struct scoop_info_s *s;
|
695 |
|
696 |
s = (struct scoop_info_s *)
|
697 |
qemu_mallocz(sizeof(struct scoop_info_s) * 2); |
698 |
memset(s, 0, sizeof(struct scoop_info_s) * count); |
699 |
s[0].target_base = 0x10800000; |
700 |
s[1].target_base = 0x08800040; |
701 |
|
702 |
/* Ready */
|
703 |
s[0].status = 0x02; |
704 |
s[1].status = 0x02; |
705 |
|
706 |
iomemtype = cpu_register_io_memory(0, scoop_readfn,
|
707 |
scoop_writefn, &s[0]);
|
708 |
cpu_register_physical_memory(s[0].target_base, 0xfff, iomemtype); |
709 |
register_savevm("scoop", 0, 0, scoop_save, scoop_load, &s[0]); |
710 |
|
711 |
if (count < 2) |
712 |
return s;
|
713 |
|
714 |
iomemtype = cpu_register_io_memory(0, scoop_readfn,
|
715 |
scoop_writefn, &s[1]);
|
716 |
cpu_register_physical_memory(s[1].target_base, 0xfff, iomemtype); |
717 |
register_savevm("scoop", 1, 0, scoop_save, scoop_load, &s[1]); |
718 |
|
719 |
return s;
|
720 |
} |
721 |
|
722 |
/* LCD backlight controller */
|
723 |
|
724 |
#define LCDTG_RESCTL 0x00 |
725 |
#define LCDTG_PHACTRL 0x01 |
726 |
#define LCDTG_DUTYCTRL 0x02 |
727 |
#define LCDTG_POWERREG0 0x03 |
728 |
#define LCDTG_POWERREG1 0x04 |
729 |
#define LCDTG_GPOR3 0x05 |
730 |
#define LCDTG_PICTRL 0x06 |
731 |
#define LCDTG_POLCTRL 0x07 |
732 |
|
733 |
static int bl_intensity, bl_power; |
734 |
|
735 |
static void spitz_bl_update(struct pxa2xx_state_s *s) |
736 |
{ |
737 |
if (bl_power && bl_intensity)
|
738 |
spitz_printf("LCD Backlight now at %i/63\n", bl_intensity);
|
739 |
else
|
740 |
spitz_printf("LCD Backlight now off\n");
|
741 |
} |
742 |
|
743 |
static void spitz_bl_bit5(int line, int level, void *opaque) |
744 |
{ |
745 |
int prev = bl_intensity;
|
746 |
|
747 |
if (level)
|
748 |
bl_intensity &= ~0x20;
|
749 |
else
|
750 |
bl_intensity |= 0x20;
|
751 |
|
752 |
if (bl_power && prev != bl_intensity)
|
753 |
spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
754 |
} |
755 |
|
756 |
static void spitz_bl_power(int line, int level, void *opaque) |
757 |
{ |
758 |
bl_power = !!level; |
759 |
spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
760 |
} |
761 |
|
762 |
static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd) |
763 |
{ |
764 |
int addr, value;
|
765 |
addr = cmd >> 5;
|
766 |
value = cmd & 0x1f;
|
767 |
|
768 |
switch (addr) {
|
769 |
case LCDTG_RESCTL:
|
770 |
if (value)
|
771 |
spitz_printf("LCD in QVGA mode\n");
|
772 |
else
|
773 |
spitz_printf("LCD in VGA mode\n");
|
774 |
break;
|
775 |
|
776 |
case LCDTG_DUTYCTRL:
|
777 |
bl_intensity &= ~0x1f;
|
778 |
bl_intensity |= value; |
779 |
if (bl_power)
|
780 |
spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
781 |
break;
|
782 |
|
783 |
case LCDTG_POWERREG0:
|
784 |
/* Set common voltage to M62332FP */
|
785 |
break;
|
786 |
} |
787 |
} |
788 |
|
789 |
/* SSP devices */
|
790 |
|
791 |
#define CORGI_SSP_PORT 2 |
792 |
|
793 |
#define SPITZ_GPIO_LCDCON_CS 53 |
794 |
#define SPITZ_GPIO_ADS7846_CS 14 |
795 |
#define SPITZ_GPIO_MAX1111_CS 20 |
796 |
#define SPITZ_GPIO_TP_INT 11 |
797 |
|
798 |
static int lcd_en, ads_en, max_en; |
799 |
static struct max111x_s *max1111; |
800 |
static struct ads7846_state_s *ads7846; |
801 |
|
802 |
/* "Demux" the signal based on current chipselect */
|
803 |
static uint32_t corgi_ssp_read(void *opaque) |
804 |
{ |
805 |
if (lcd_en)
|
806 |
return 0; |
807 |
if (ads_en)
|
808 |
return ads7846_read(ads7846);
|
809 |
if (max_en)
|
810 |
return max111x_read(max1111);
|
811 |
return 0; |
812 |
} |
813 |
|
814 |
static void corgi_ssp_write(void *opaque, uint32_t value) |
815 |
{ |
816 |
if (lcd_en)
|
817 |
spitz_lcdtg_dac_put(opaque, value); |
818 |
if (ads_en)
|
819 |
ads7846_write(ads7846, value); |
820 |
if (max_en)
|
821 |
max111x_write(max1111, value); |
822 |
} |
823 |
|
824 |
static void corgi_ssp_gpio_cs(int line, int level, struct pxa2xx_state_s *s) |
825 |
{ |
826 |
if (line == SPITZ_GPIO_LCDCON_CS)
|
827 |
lcd_en = !level; |
828 |
else if (line == SPITZ_GPIO_ADS7846_CS) |
829 |
ads_en = !level; |
830 |
else if (line == SPITZ_GPIO_MAX1111_CS) |
831 |
max_en = !level; |
832 |
} |
833 |
|
834 |
#define MAX1111_BATT_VOLT 1 |
835 |
#define MAX1111_BATT_TEMP 2 |
836 |
#define MAX1111_ACIN_VOLT 3 |
837 |
|
838 |
#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */ |
839 |
#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ |
840 |
#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ |
841 |
|
842 |
static void spitz_adc_temp_on(int line, int level, void *opaque) |
843 |
{ |
844 |
if (!max1111)
|
845 |
return;
|
846 |
|
847 |
if (level)
|
848 |
max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP); |
849 |
else
|
850 |
max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
|
851 |
} |
852 |
|
853 |
static void spitz_pendown_set(void *opaque, int line, int level) |
854 |
{ |
855 |
struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque; |
856 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_TP_INT, level); |
857 |
} |
858 |
|
859 |
static void spitz_ssp_save(QEMUFile *f, void *opaque) |
860 |
{ |
861 |
qemu_put_be32(f, lcd_en); |
862 |
qemu_put_be32(f, ads_en); |
863 |
qemu_put_be32(f, max_en); |
864 |
qemu_put_be32(f, bl_intensity); |
865 |
qemu_put_be32(f, bl_power); |
866 |
} |
867 |
|
868 |
static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id) |
869 |
{ |
870 |
lcd_en = qemu_get_be32(f); |
871 |
ads_en = qemu_get_be32(f); |
872 |
max_en = qemu_get_be32(f); |
873 |
bl_intensity = qemu_get_be32(f); |
874 |
bl_power = qemu_get_be32(f); |
875 |
|
876 |
return 0; |
877 |
} |
878 |
|
879 |
static void spitz_ssp_attach(struct pxa2xx_state_s *cpu) |
880 |
{ |
881 |
lcd_en = ads_en = max_en = 0;
|
882 |
|
883 |
ads7846 = ads7846_init(qemu_allocate_irqs(spitz_pendown_set, cpu, 1)[0]); |
884 |
|
885 |
max1111 = max1111_init(0);
|
886 |
max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); |
887 |
max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
|
888 |
max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); |
889 |
|
890 |
pxa2xx_ssp_attach(cpu->ssp[CORGI_SSP_PORT - 1], corgi_ssp_read,
|
891 |
corgi_ssp_write, cpu); |
892 |
|
893 |
pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS, |
894 |
(gpio_handler_t) corgi_ssp_gpio_cs, cpu); |
895 |
pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS, |
896 |
(gpio_handler_t) corgi_ssp_gpio_cs, cpu); |
897 |
pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS, |
898 |
(gpio_handler_t) corgi_ssp_gpio_cs, cpu); |
899 |
|
900 |
bl_intensity = 0x20;
|
901 |
bl_power = 0;
|
902 |
|
903 |
register_savevm("spitz_ssp", 0, 0, spitz_ssp_save, spitz_ssp_load, cpu); |
904 |
} |
905 |
|
906 |
/* CF Microdrive */
|
907 |
|
908 |
static void spitz_microdrive_attach(struct pxa2xx_state_s *cpu) |
909 |
{ |
910 |
struct pcmcia_card_s *md;
|
911 |
BlockDriverState *bs = bs_table[0];
|
912 |
|
913 |
if (bs && bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
|
914 |
md = dscm1xxxx_init(bs); |
915 |
pxa2xx_pcmcia_attach(cpu->pcmcia[0], md);
|
916 |
} |
917 |
} |
918 |
|
919 |
/* Wm8750 and Max7310 on I2C */
|
920 |
|
921 |
#define AKITA_MAX_ADDR 0x18 |
922 |
#define SPITZ_WM_ADDRL 0x1a |
923 |
#define SPITZ_WM_ADDRH 0x1b |
924 |
|
925 |
#define SPITZ_GPIO_WM 5 |
926 |
|
927 |
#ifdef HAS_AUDIO
|
928 |
static void spitz_wm8750_addr(int line, int level, void *opaque) |
929 |
{ |
930 |
i2c_slave *wm = (i2c_slave *) opaque; |
931 |
if (level)
|
932 |
i2c_set_slave_address(wm, SPITZ_WM_ADDRH); |
933 |
else
|
934 |
i2c_set_slave_address(wm, SPITZ_WM_ADDRL); |
935 |
} |
936 |
#endif
|
937 |
|
938 |
static void spitz_i2c_setup(struct pxa2xx_state_s *cpu) |
939 |
{ |
940 |
/* Attach the CPU on one end of our I2C bus. */
|
941 |
i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
|
942 |
|
943 |
#ifdef HAS_AUDIO
|
944 |
AudioState *audio; |
945 |
i2c_slave *wm; |
946 |
|
947 |
audio = AUD_init(); |
948 |
if (!audio)
|
949 |
return;
|
950 |
/* Attach a WM8750 to the bus */
|
951 |
wm = wm8750_init(bus, audio); |
952 |
|
953 |
spitz_wm8750_addr(0, 0, wm); |
954 |
pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_WM, spitz_wm8750_addr, wm); |
955 |
/* .. and to the sound interface. */
|
956 |
cpu->i2s->opaque = wm; |
957 |
cpu->i2s->codec_out = wm8750_dac_dat; |
958 |
cpu->i2s->codec_in = wm8750_adc_dat; |
959 |
wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s); |
960 |
#endif
|
961 |
} |
962 |
|
963 |
static void spitz_akita_i2c_setup(struct pxa2xx_state_s *cpu) |
964 |
{ |
965 |
/* Attach a Max7310 to Akita I2C bus. */
|
966 |
i2c_set_slave_address(max7310_init(pxa2xx_i2c_bus(cpu->i2c[0])),
|
967 |
AKITA_MAX_ADDR); |
968 |
} |
969 |
|
970 |
/* Other peripherals */
|
971 |
|
972 |
static void spitz_charge_switch(int line, int level, void *opaque) |
973 |
{ |
974 |
spitz_printf("Charging %s.\n", level ? "off" : "on"); |
975 |
} |
976 |
|
977 |
static void spitz_discharge_switch(int line, int level, void *opaque) |
978 |
{ |
979 |
spitz_printf("Discharging %s.\n", level ? "on" : "off"); |
980 |
} |
981 |
|
982 |
static void spitz_greenled_switch(int line, int level, void *opaque) |
983 |
{ |
984 |
spitz_printf("Green LED %s.\n", level ? "on" : "off"); |
985 |
} |
986 |
|
987 |
static void spitz_orangeled_switch(int line, int level, void *opaque) |
988 |
{ |
989 |
spitz_printf("Orange LED %s.\n", level ? "on" : "off"); |
990 |
} |
991 |
|
992 |
#define SPITZ_SCP_LED_GREEN 1 |
993 |
#define SPITZ_SCP_JK_B 2 |
994 |
#define SPITZ_SCP_CHRG_ON 3 |
995 |
#define SPITZ_SCP_MUTE_L 4 |
996 |
#define SPITZ_SCP_MUTE_R 5 |
997 |
#define SPITZ_SCP_CF_POWER 6 |
998 |
#define SPITZ_SCP_LED_ORANGE 7 |
999 |
#define SPITZ_SCP_JK_A 8 |
1000 |
#define SPITZ_SCP_ADC_TEMP_ON 9 |
1001 |
#define SPITZ_SCP2_IR_ON 1 |
1002 |
#define SPITZ_SCP2_AKIN_PULLUP 2 |
1003 |
#define SPITZ_SCP2_BACKLIGHT_CONT 7 |
1004 |
#define SPITZ_SCP2_BACKLIGHT_ON 8 |
1005 |
#define SPITZ_SCP2_MIC_BIAS 9 |
1006 |
|
1007 |
static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu, |
1008 |
struct scoop_info_s *scp, int num) |
1009 |
{ |
1010 |
scoop_gpio_handler_set(&scp[0], SPITZ_SCP_CHRG_ON,
|
1011 |
spitz_charge_switch, cpu); |
1012 |
scoop_gpio_handler_set(&scp[0], SPITZ_SCP_JK_B,
|
1013 |
spitz_discharge_switch, cpu); |
1014 |
scoop_gpio_handler_set(&scp[0], SPITZ_SCP_LED_GREEN,
|
1015 |
spitz_greenled_switch, cpu); |
1016 |
scoop_gpio_handler_set(&scp[0], SPITZ_SCP_LED_ORANGE,
|
1017 |
spitz_orangeled_switch, cpu); |
1018 |
|
1019 |
if (num >= 2) { |
1020 |
scoop_gpio_handler_set(&scp[1], SPITZ_SCP2_BACKLIGHT_CONT,
|
1021 |
spitz_bl_bit5, cpu); |
1022 |
scoop_gpio_handler_set(&scp[1], SPITZ_SCP2_BACKLIGHT_ON,
|
1023 |
spitz_bl_power, cpu); |
1024 |
} |
1025 |
|
1026 |
scoop_gpio_handler_set(&scp[0], SPITZ_SCP_ADC_TEMP_ON,
|
1027 |
spitz_adc_temp_on, cpu); |
1028 |
} |
1029 |
|
1030 |
#define SPITZ_GPIO_HSYNC 22 |
1031 |
#define SPITZ_GPIO_SD_DETECT 9 |
1032 |
#define SPITZ_GPIO_SD_WP 81 |
1033 |
#define SPITZ_GPIO_ON_RESET 89 |
1034 |
#define SPITZ_GPIO_BAT_COVER 90 |
1035 |
#define SPITZ_GPIO_CF1_IRQ 105 |
1036 |
#define SPITZ_GPIO_CF1_CD 94 |
1037 |
#define SPITZ_GPIO_CF2_IRQ 106 |
1038 |
#define SPITZ_GPIO_CF2_CD 93 |
1039 |
|
1040 |
int spitz_hsync;
|
1041 |
|
1042 |
static void spitz_lcd_hsync_handler(void *opaque) |
1043 |
{ |
1044 |
struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque; |
1045 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_HSYNC, spitz_hsync); |
1046 |
spitz_hsync ^= 1;
|
1047 |
} |
1048 |
|
1049 |
static void spitz_mmc_coverswitch_change(void *opaque, int in) |
1050 |
{ |
1051 |
struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque; |
1052 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SD_DETECT, in); |
1053 |
} |
1054 |
|
1055 |
static void spitz_mmc_writeprotect_change(void *opaque, int wp) |
1056 |
{ |
1057 |
struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque; |
1058 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SD_WP, wp); |
1059 |
} |
1060 |
|
1061 |
static void spitz_pcmcia_cb(void *opaque, int line, int level) |
1062 |
{ |
1063 |
struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque; |
1064 |
static const int gpio_map[] = { |
1065 |
SPITZ_GPIO_CF1_IRQ, SPITZ_GPIO_CF1_CD, |
1066 |
SPITZ_GPIO_CF2_IRQ, SPITZ_GPIO_CF2_CD, |
1067 |
}; |
1068 |
pxa2xx_gpio_set(cpu->gpio, gpio_map[line], level); |
1069 |
} |
1070 |
|
1071 |
static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots) |
1072 |
{ |
1073 |
qemu_irq *pcmcia_cb; |
1074 |
/*
|
1075 |
* Bad hack: We toggle the LCD hsync GPIO on every GPIO status
|
1076 |
* read to satisfy broken guests that poll-wait for hsync.
|
1077 |
* Simulating a real hsync event would be less practical and
|
1078 |
* wouldn't guarantee that a guest ever exits the loop.
|
1079 |
*/
|
1080 |
spitz_hsync = 0;
|
1081 |
pxa2xx_gpio_read_notifier(cpu->gpio, spitz_lcd_hsync_handler, cpu); |
1082 |
pxa2xx_lcd_vsync_cb(cpu->lcd, spitz_lcd_hsync_handler, cpu); |
1083 |
|
1084 |
/* MMC/SD host */
|
1085 |
pxa2xx_mmci_handlers(cpu->mmc, cpu, spitz_mmc_writeprotect_change, |
1086 |
spitz_mmc_coverswitch_change); |
1087 |
|
1088 |
/* Battery lock always closed */
|
1089 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_BAT_COVER, 1);
|
1090 |
|
1091 |
/* Handle reset */
|
1092 |
pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_ON_RESET, pxa2xx_reset, cpu); |
1093 |
|
1094 |
/* PCMCIA signals: card's IRQ and Card-Detect */
|
1095 |
pcmcia_cb = qemu_allocate_irqs(spitz_pcmcia_cb, cpu, slots * 2);
|
1096 |
if (slots >= 1) |
1097 |
pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0], pcmcia_cb[0], pcmcia_cb[1]); |
1098 |
if (slots >= 2) |
1099 |
pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1], pcmcia_cb[2], pcmcia_cb[3]); |
1100 |
|
1101 |
/* Initialise the screen rotation related signals */
|
1102 |
spitz_gpio_invert[3] = 0; /* Always open */ |
1103 |
if (graphic_rotate) { /* Tablet mode */ |
1104 |
spitz_gpio_invert[4] = 0; |
1105 |
} else { /* Portrait mode */ |
1106 |
spitz_gpio_invert[4] = 1; |
1107 |
} |
1108 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SWA, spitz_gpio_invert[3]);
|
1109 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SWB, spitz_gpio_invert[4]);
|
1110 |
} |
1111 |
|
1112 |
/* Write the bootloader parameters memory area. */
|
1113 |
|
1114 |
#define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a) |
1115 |
|
1116 |
struct __attribute__ ((__packed__)) sl_param_info {
|
1117 |
uint32_t comadj_keyword; |
1118 |
int32_t comadj; |
1119 |
|
1120 |
uint32_t uuid_keyword; |
1121 |
char uuid[16]; |
1122 |
|
1123 |
uint32_t touch_keyword; |
1124 |
int32_t touch_xp; |
1125 |
int32_t touch_yp; |
1126 |
int32_t touch_xd; |
1127 |
int32_t touch_yd; |
1128 |
|
1129 |
uint32_t adadj_keyword; |
1130 |
int32_t adadj; |
1131 |
|
1132 |
uint32_t phad_keyword; |
1133 |
int32_t phadadj; |
1134 |
} spitz_bootparam = { |
1135 |
.comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'), |
1136 |
.comadj = 125,
|
1137 |
.uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'), |
1138 |
.uuid = { -1 },
|
1139 |
.touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'), |
1140 |
.touch_xp = -1,
|
1141 |
.adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'), |
1142 |
.adadj = -1,
|
1143 |
.phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'), |
1144 |
.phadadj = 0x01,
|
1145 |
}; |
1146 |
|
1147 |
static void sl_bootparam_write(uint32_t ptr) |
1148 |
{ |
1149 |
memcpy(phys_ram_base + ptr, &spitz_bootparam, |
1150 |
sizeof(struct sl_param_info)); |
1151 |
} |
1152 |
|
1153 |
#define SL_PXA_PARAM_BASE 0xa0000a00 |
1154 |
|
1155 |
/* Board init. */
|
1156 |
enum spitz_model_e { spitz, akita, borzoi, terrier };
|
1157 |
|
1158 |
static void spitz_common_init(int ram_size, int vga_ram_size, |
1159 |
DisplayState *ds, const char *kernel_filename, |
1160 |
const char *kernel_cmdline, const char *initrd_filename, |
1161 |
const char *cpu_model, enum spitz_model_e model, int arm_id) |
1162 |
{ |
1163 |
uint32_t spitz_ram = 0x04000000;
|
1164 |
uint32_t spitz_rom = 0x00800000;
|
1165 |
struct pxa2xx_state_s *cpu;
|
1166 |
struct scoop_info_s *scp;
|
1167 |
|
1168 |
if (!cpu_model)
|
1169 |
cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; |
1170 |
|
1171 |
/* Setup CPU & memory */
|
1172 |
if (ram_size < spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE) {
|
1173 |
fprintf(stderr, "This platform requires %i bytes of memory\n",
|
1174 |
spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE); |
1175 |
exit(1);
|
1176 |
} |
1177 |
cpu = pxa270_init(spitz_ram, ds, cpu_model); |
1178 |
|
1179 |
sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M); |
1180 |
|
1181 |
cpu_register_physical_memory(0, spitz_rom,
|
1182 |
qemu_ram_alloc(spitz_rom) | IO_MEM_ROM); |
1183 |
|
1184 |
/* Setup peripherals */
|
1185 |
spitz_keyboard_register(cpu); |
1186 |
|
1187 |
spitz_ssp_attach(cpu); |
1188 |
|
1189 |
scp = spitz_scoop_init(cpu, (model == akita) ? 1 : 2); |
1190 |
|
1191 |
spitz_scoop_gpio_setup(cpu, scp, (model == akita) ? 1 : 2); |
1192 |
|
1193 |
spitz_gpio_setup(cpu, (model == akita) ? 1 : 2); |
1194 |
|
1195 |
spitz_i2c_setup(cpu); |
1196 |
|
1197 |
if (model == akita)
|
1198 |
spitz_akita_i2c_setup(cpu); |
1199 |
|
1200 |
if (model == terrier)
|
1201 |
/* A 6.0 GB microdrive is permanently sitting in CF slot 0. */
|
1202 |
spitz_microdrive_attach(cpu); |
1203 |
else if (model != akita) |
1204 |
/* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
|
1205 |
spitz_microdrive_attach(cpu); |
1206 |
|
1207 |
/* Setup initial (reset) machine state */
|
1208 |
cpu->env->regs[15] = PXA2XX_SDRAM_BASE;
|
1209 |
|
1210 |
arm_load_kernel(cpu->env, spitz_ram, kernel_filename, kernel_cmdline, |
1211 |
initrd_filename, arm_id, PXA2XX_SDRAM_BASE); |
1212 |
sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE); |
1213 |
} |
1214 |
|
1215 |
static void spitz_init(int ram_size, int vga_ram_size, int boot_device, |
1216 |
DisplayState *ds, const char **fd_filename, int snapshot, |
1217 |
const char *kernel_filename, const char *kernel_cmdline, |
1218 |
const char *initrd_filename, const char *cpu_model) |
1219 |
{ |
1220 |
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
1221 |
kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
|
1222 |
} |
1223 |
|
1224 |
static void borzoi_init(int ram_size, int vga_ram_size, int boot_device, |
1225 |
DisplayState *ds, const char **fd_filename, int snapshot, |
1226 |
const char *kernel_filename, const char *kernel_cmdline, |
1227 |
const char *initrd_filename, const char *cpu_model) |
1228 |
{ |
1229 |
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
1230 |
kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
|
1231 |
} |
1232 |
|
1233 |
static void akita_init(int ram_size, int vga_ram_size, int boot_device, |
1234 |
DisplayState *ds, const char **fd_filename, int snapshot, |
1235 |
const char *kernel_filename, const char *kernel_cmdline, |
1236 |
const char *initrd_filename, const char *cpu_model) |
1237 |
{ |
1238 |
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
1239 |
kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
|
1240 |
} |
1241 |
|
1242 |
static void terrier_init(int ram_size, int vga_ram_size, int boot_device, |
1243 |
DisplayState *ds, const char **fd_filename, int snapshot, |
1244 |
const char *kernel_filename, const char *kernel_cmdline, |
1245 |
const char *initrd_filename, const char *cpu_model) |
1246 |
{ |
1247 |
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
1248 |
kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
|
1249 |
} |
1250 |
|
1251 |
QEMUMachine akitapda_machine = { |
1252 |
"akita",
|
1253 |
"Akita PDA (PXA270)",
|
1254 |
akita_init, |
1255 |
}; |
1256 |
|
1257 |
QEMUMachine spitzpda_machine = { |
1258 |
"spitz",
|
1259 |
"Spitz PDA (PXA270)",
|
1260 |
spitz_init, |
1261 |
}; |
1262 |
|
1263 |
QEMUMachine borzoipda_machine = { |
1264 |
"borzoi",
|
1265 |
"Borzoi PDA (PXA270)",
|
1266 |
borzoi_init, |
1267 |
}; |
1268 |
|
1269 |
QEMUMachine terrierpda_machine = { |
1270 |
"terrier",
|
1271 |
"Terrier PDA (PXA270)",
|
1272 |
terrier_init, |
1273 |
}; |