Revision aaed909a target-mips/translate_init.c
| b/target-mips/translate_init.c | ||
|---|---|---|
| 53 | 53 |
Define a major version 1, minor version 0. */ |
| 54 | 54 |
#define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV)) |
| 55 | 55 |
|
| 56 |
|
|
| 57 | 56 |
struct mips_def_t {
|
| 58 | 57 |
const unsigned char *name; |
| 59 | 58 |
int32_t CP0_PRid; |
| ... | ... | |
| 300 | 299 |
#endif |
| 301 | 300 |
}; |
| 302 | 301 |
|
| 303 |
int mips_find_by_name (const unsigned char *name, mips_def_t **def)
|
|
| 302 |
static const mips_def_t *cpu_mips_find_by_name (const unsigned char *name)
|
|
| 304 | 303 |
{
|
| 305 |
int i, ret;
|
|
| 304 |
int i; |
|
| 306 | 305 |
|
| 307 |
ret = -1; |
|
| 308 |
*def = NULL; |
|
| 309 | 306 |
for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
|
| 310 | 307 |
if (strcasecmp(name, mips_defs[i].name) == 0) {
|
| 311 |
*def = &mips_defs[i]; |
|
| 312 |
ret = 0; |
|
| 313 |
break; |
|
| 308 |
return &mips_defs[i]; |
|
| 314 | 309 |
} |
| 315 | 310 |
} |
| 316 |
|
|
| 317 |
return ret; |
|
| 311 |
return NULL; |
|
| 318 | 312 |
} |
| 319 | 313 |
|
| 320 | 314 |
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
| ... | ... | |
| 328 | 322 |
} |
| 329 | 323 |
|
| 330 | 324 |
#ifndef CONFIG_USER_ONLY |
| 331 |
static void no_mmu_init (CPUMIPSState *env, mips_def_t *def) |
|
| 325 |
static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
| 332 | 326 |
{
|
| 333 | 327 |
env->tlb->nb_tlb = 1; |
| 334 | 328 |
env->tlb->map_address = &no_mmu_map_address; |
| 335 | 329 |
} |
| 336 | 330 |
|
| 337 |
static void fixed_mmu_init (CPUMIPSState *env, mips_def_t *def) |
|
| 331 |
static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
| 338 | 332 |
{
|
| 339 | 333 |
env->tlb->nb_tlb = 1; |
| 340 | 334 |
env->tlb->map_address = &fixed_mmu_map_address; |
| 341 | 335 |
} |
| 342 | 336 |
|
| 343 |
static void r4k_mmu_init (CPUMIPSState *env, mips_def_t *def) |
|
| 337 |
static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
| 344 | 338 |
{
|
| 345 | 339 |
env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
| 346 | 340 |
env->tlb->map_address = &r4k_map_address; |
| ... | ... | |
| 350 | 344 |
env->tlb->do_tlbr = r4k_do_tlbr; |
| 351 | 345 |
} |
| 352 | 346 |
|
| 353 |
static void mmu_init (CPUMIPSState *env, mips_def_t *def) |
|
| 347 |
static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
| 354 | 348 |
{
|
| 355 | 349 |
env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext)); |
| 356 | 350 |
|
| ... | ... | |
| 376 | 370 |
} |
| 377 | 371 |
#endif /* CONFIG_USER_ONLY */ |
| 378 | 372 |
|
| 379 |
static void fpu_init (CPUMIPSState *env, mips_def_t *def) |
|
| 373 |
static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
| 380 | 374 |
{
|
| 381 | 375 |
env->fpu = qemu_mallocz(sizeof(CPUMIPSFPUContext)); |
| 382 | 376 |
|
| ... | ... | |
| 389 | 383 |
#endif |
| 390 | 384 |
} |
| 391 | 385 |
|
| 392 |
static void mvp_init (CPUMIPSState *env, mips_def_t *def) |
|
| 386 |
static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
|
|
| 393 | 387 |
{
|
| 394 | 388 |
env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext)); |
| 395 | 389 |
|
| ... | ... | |
| 415 | 409 |
(0x1 << CP0MVPC1_PCP1); |
| 416 | 410 |
} |
| 417 | 411 |
|
| 418 |
int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
|
|
| 412 |
static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def)
|
|
| 419 | 413 |
{
|
| 420 |
if (!def) |
|
| 421 |
def = env->cpu_model; |
|
| 422 |
if (!def) |
|
| 423 |
cpu_abort(env, "Unable to find MIPS CPU definition\n"); |
|
| 424 |
env->cpu_model = def; |
|
| 425 | 414 |
env->CP0_PRid = def->CP0_PRid; |
| 426 | 415 |
env->CP0_Config0 = def->CP0_Config0; |
| 427 | 416 |
#ifdef TARGET_WORDS_BIGENDIAN |
Also available in: Unified diff