root / hw / ppc4xx_devs.c @ aaed909a
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/*
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* QEMU PowerPC 4xx embedded processors shared devices emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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#include "ppc4xx.h" |
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extern int loglevel; |
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extern FILE *logfile;
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//#define DEBUG_MMIO
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#define DEBUG_UIC
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/*****************************************************************************/
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/* Generic PowerPC 4xx processor instanciation */
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CPUState *ppc4xx_init (const unsigned char *cpu_model, |
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clk_setup_t *cpu_clk, clk_setup_t *tb_clk, |
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uint32_t sysclk) |
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{
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CPUState *env; |
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|
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/* init CPUs */
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env = cpu_init(cpu_model); |
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if (!env) {
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fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
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cpu_model); |
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exit(1);
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} |
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cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ |
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cpu_clk->opaque = env; |
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/* Set time-base frequency to sysclk */
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tb_clk->cb = ppc_emb_timers_init(env, sysclk); |
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tb_clk->opaque = env; |
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ppc_dcr_init(env, NULL, NULL); |
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/* Register qemu callbacks */
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qemu_register_reset(&cpu_ppc_reset, env); |
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
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return env;
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} |
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|
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/*****************************************************************************/
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/* Fake device used to map multiple devices in a single memory page */
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#define MMIO_AREA_BITS 8 |
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#define MMIO_AREA_LEN (1 << MMIO_AREA_BITS) |
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#define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS)) |
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#define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1)) |
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struct ppc4xx_mmio_t {
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target_phys_addr_t base; |
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CPUReadMemoryFunc **mem_read[MMIO_AREA_NB]; |
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CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB]; |
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void *opaque[MMIO_AREA_NB];
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}; |
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static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr) |
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{
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#ifdef DEBUG_UNASSIGNED
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ppc4xx_mmio_t *mmio; |
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mmio = opaque; |
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printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n", |
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addr, mmio->base); |
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#endif
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return 0; |
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} |
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static void unassigned_mmio_writeb (void *opaque, |
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target_phys_addr_t addr, uint32_t val) |
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{
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#ifdef DEBUG_UNASSIGNED
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ppc4xx_mmio_t *mmio; |
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mmio = opaque; |
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printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n", |
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addr, val, mmio->base); |
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#endif
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} |
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static CPUReadMemoryFunc *unassigned_mmio_read[3] = { |
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unassigned_mmio_readb, |
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unassigned_mmio_readb, |
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unassigned_mmio_readb, |
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}; |
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static CPUWriteMemoryFunc *unassigned_mmio_write[3] = { |
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unassigned_mmio_writeb, |
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unassigned_mmio_writeb, |
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unassigned_mmio_writeb, |
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}; |
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static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
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target_phys_addr_t addr, int len)
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{
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CPUReadMemoryFunc **mem_read; |
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uint32_t ret; |
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int idx;
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idx = MMIO_IDX(addr - mmio->base); |
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#if defined(DEBUG_MMIO)
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printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__, |
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mmio, len, addr, idx); |
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#endif
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mem_read = mmio->mem_read[idx]; |
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ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base); |
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return ret;
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} |
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static void mmio_writelen (ppc4xx_mmio_t *mmio, |
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target_phys_addr_t addr, uint32_t value, int len)
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{
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CPUWriteMemoryFunc **mem_write; |
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int idx;
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idx = MMIO_IDX(addr - mmio->base); |
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#if defined(DEBUG_MMIO)
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printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08x\n", __func__, |
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mmio, len, addr, idx, value); |
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#endif
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mem_write = mmio->mem_write[idx]; |
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(*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value); |
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} |
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static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr) |
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{
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX "\n", __func__, addr); |
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#endif
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return mmio_readlen(opaque, addr, 0); |
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} |
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static void mmio_writeb (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
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#endif
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mmio_writelen(opaque, addr, value, 0);
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} |
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static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr) |
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{
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX "\n", __func__, addr); |
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#endif
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return mmio_readlen(opaque, addr, 1); |
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} |
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static void mmio_writew (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
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#endif
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mmio_writelen(opaque, addr, value, 1);
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} |
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static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr) |
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{
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX "\n", __func__, addr); |
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#endif
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return mmio_readlen(opaque, addr, 2); |
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} |
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static void mmio_writel (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
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#endif
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mmio_writelen(opaque, addr, value, 2);
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} |
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static CPUReadMemoryFunc *mmio_read[] = {
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&mmio_readb, |
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&mmio_readw, |
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&mmio_readl, |
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}; |
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static CPUWriteMemoryFunc *mmio_write[] = {
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&mmio_writeb, |
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&mmio_writew, |
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&mmio_writel, |
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}; |
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int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
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target_phys_addr_t offset, uint32_t len, |
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CPUReadMemoryFunc **mem_read, |
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CPUWriteMemoryFunc **mem_write, void *opaque)
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{
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uint32_t end; |
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int idx, eidx;
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|
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if ((offset + len) > TARGET_PAGE_SIZE)
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return -1; |
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idx = MMIO_IDX(offset); |
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end = offset + len - 1;
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eidx = MMIO_IDX(end); |
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#if defined(DEBUG_MMIO)
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printf("%s: offset %08x len %08x %08x %d %d\n", __func__, offset, len,
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end, idx, eidx); |
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#endif
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for (; idx <= eidx; idx++) {
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mmio->mem_read[idx] = mem_read; |
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mmio->mem_write[idx] = mem_write; |
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mmio->opaque[idx] = opaque; |
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} |
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return 0; |
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} |
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|
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ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base) |
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{
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ppc4xx_mmio_t *mmio; |
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int mmio_memory;
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|
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mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
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if (mmio != NULL) { |
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mmio->base = base; |
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mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
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#if defined(DEBUG_MMIO)
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printf("%s: %p base %08x len %08x %d\n", __func__,
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mmio, base, TARGET_PAGE_SIZE, mmio_memory); |
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#endif
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cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory); |
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ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
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unassigned_mmio_read, unassigned_mmio_write, |
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mmio); |
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} |
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return mmio;
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} |
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/*****************************************************************************/
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/* "Universal" Interrupt controller */
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enum {
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DCR_UICSR = 0x000,
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DCR_UICSRS = 0x001,
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DCR_UICER = 0x002,
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DCR_UICCR = 0x003,
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DCR_UICPR = 0x004,
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DCR_UICTR = 0x005,
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DCR_UICMSR = 0x006,
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DCR_UICVR = 0x007,
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DCR_UICVCR = 0x008,
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DCR_UICMAX = 0x009,
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}; |
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#define UIC_MAX_IRQ 32 |
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typedef struct ppcuic_t ppcuic_t; |
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struct ppcuic_t {
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uint32_t dcr_base; |
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int use_vectors;
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uint32_t uicsr; /* Status register */
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uint32_t uicer; /* Enable register */
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uint32_t uiccr; /* Critical register */
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uint32_t uicpr; /* Polarity register */
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uint32_t uictr; /* Triggering register */
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uint32_t uicvcr; /* Vector configuration register */
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uint32_t uicvr; |
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qemu_irq *irqs; |
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}; |
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|
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static void ppcuic_trigger_irq (ppcuic_t *uic) |
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{
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uint32_t ir, cr; |
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int start, end, inc, i;
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/* Trigger interrupt if any is pending */
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ir = uic->uicsr & uic->uicer & (~uic->uiccr); |
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cr = uic->uicsr & uic->uicer & uic->uiccr; |
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#ifdef DEBUG_UIC
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: uicsr %08x uicer %08x uiccr %08x\n"
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" %08x ir %08x cr %08x\n", __func__,
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uic->uicsr, uic->uicer, uic->uiccr, |
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uic->uicsr & uic->uicer, ir, cr); |
| 302 |
} |
| 303 |
#endif
|
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if (ir != 0x0000000) { |
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#ifdef DEBUG_UIC
|
| 306 |
if (loglevel & CPU_LOG_INT) {
|
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fprintf(logfile, "Raise UIC interrupt\n");
|
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} |
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#endif
|
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qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); |
| 311 |
} else {
|
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#ifdef DEBUG_UIC
|
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if (loglevel & CPU_LOG_INT) {
|
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fprintf(logfile, "Lower UIC interrupt\n");
|
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} |
| 316 |
#endif
|
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qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); |
| 318 |
} |
| 319 |
/* Trigger critical interrupt if any is pending and update vector */
|
| 320 |
if (cr != 0x0000000) { |
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qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); |
| 322 |
if (uic->use_vectors) {
|
| 323 |
/* Compute critical IRQ vector */
|
| 324 |
if (uic->uicvcr & 1) { |
| 325 |
start = 31;
|
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end = 0;
|
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inc = -1;
|
| 328 |
} else {
|
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start = 0;
|
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end = 31;
|
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inc = 1;
|
| 332 |
} |
| 333 |
uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
|
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for (i = start; i <= end; i += inc) {
|
| 335 |
if (cr & (1 << i)) { |
| 336 |
uic->uicvr += (i - start) * 512 * inc;
|
| 337 |
break;
|
| 338 |
} |
| 339 |
} |
| 340 |
} |
| 341 |
#ifdef DEBUG_UIC
|
| 342 |
if (loglevel & CPU_LOG_INT) {
|
| 343 |
fprintf(logfile, "Raise UIC critical interrupt - vector %08x\n",
|
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uic->uicvr); |
| 345 |
} |
| 346 |
#endif
|
| 347 |
} else {
|
| 348 |
#ifdef DEBUG_UIC
|
| 349 |
if (loglevel & CPU_LOG_INT) {
|
| 350 |
fprintf(logfile, "Lower UIC critical interrupt\n");
|
| 351 |
} |
| 352 |
#endif
|
| 353 |
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); |
| 354 |
uic->uicvr = 0x00000000;
|
| 355 |
} |
| 356 |
} |
| 357 |
|
| 358 |
static void ppcuic_set_irq (void *opaque, int irq_num, int level) |
| 359 |
{
|
| 360 |
ppcuic_t *uic; |
| 361 |
uint32_t mask, sr; |
| 362 |
|
| 363 |
uic = opaque; |
| 364 |
mask = 1 << irq_num;
|
| 365 |
#ifdef DEBUG_UIC
|
| 366 |
if (loglevel & CPU_LOG_INT) {
|
| 367 |
fprintf(logfile, "%s: irq %d level %d uicsr %08x mask %08x => %08x "
|
| 368 |
"%08x\n", __func__, irq_num, level,
|
| 369 |
uic->uicsr, mask, uic->uicsr & mask, level << irq_num); |
| 370 |
} |
| 371 |
#endif
|
| 372 |
if (irq_num < 0 || irq_num > 31) |
| 373 |
return;
|
| 374 |
sr = uic->uicsr; |
| 375 |
if (!(uic->uicpr & mask)) {
|
| 376 |
/* Negatively asserted IRQ */
|
| 377 |
level = level == 0 ? 1 : 0; |
| 378 |
} |
| 379 |
/* Update status register */
|
| 380 |
if (uic->uictr & mask) {
|
| 381 |
/* Edge sensitive interrupt */
|
| 382 |
if (level == 1) |
| 383 |
uic->uicsr |= mask; |
| 384 |
} else {
|
| 385 |
/* Level sensitive interrupt */
|
| 386 |
if (level == 1) |
| 387 |
uic->uicsr |= mask; |
| 388 |
else
|
| 389 |
uic->uicsr &= ~mask; |
| 390 |
} |
| 391 |
#ifdef DEBUG_UIC
|
| 392 |
if (loglevel & CPU_LOG_INT) {
|
| 393 |
fprintf(logfile, "%s: irq %d level %d sr %08x => %08x\n", __func__,
|
| 394 |
irq_num, level, uic->uicsr, sr); |
| 395 |
} |
| 396 |
#endif
|
| 397 |
if (sr != uic->uicsr)
|
| 398 |
ppcuic_trigger_irq(uic); |
| 399 |
} |
| 400 |
|
| 401 |
static target_ulong dcr_read_uic (void *opaque, int dcrn) |
| 402 |
{
|
| 403 |
ppcuic_t *uic; |
| 404 |
target_ulong ret; |
| 405 |
|
| 406 |
uic = opaque; |
| 407 |
dcrn -= uic->dcr_base; |
| 408 |
switch (dcrn) {
|
| 409 |
case DCR_UICSR:
|
| 410 |
case DCR_UICSRS:
|
| 411 |
ret = uic->uicsr; |
| 412 |
break;
|
| 413 |
case DCR_UICER:
|
| 414 |
ret = uic->uicer; |
| 415 |
break;
|
| 416 |
case DCR_UICCR:
|
| 417 |
ret = uic->uiccr; |
| 418 |
break;
|
| 419 |
case DCR_UICPR:
|
| 420 |
ret = uic->uicpr; |
| 421 |
break;
|
| 422 |
case DCR_UICTR:
|
| 423 |
ret = uic->uictr; |
| 424 |
break;
|
| 425 |
case DCR_UICMSR:
|
| 426 |
ret = uic->uicsr & uic->uicer; |
| 427 |
break;
|
| 428 |
case DCR_UICVR:
|
| 429 |
if (!uic->use_vectors)
|
| 430 |
goto no_read;
|
| 431 |
ret = uic->uicvr; |
| 432 |
break;
|
| 433 |
case DCR_UICVCR:
|
| 434 |
if (!uic->use_vectors)
|
| 435 |
goto no_read;
|
| 436 |
ret = uic->uicvcr; |
| 437 |
break;
|
| 438 |
default:
|
| 439 |
no_read:
|
| 440 |
ret = 0x00000000;
|
| 441 |
break;
|
| 442 |
} |
| 443 |
|
| 444 |
return ret;
|
| 445 |
} |
| 446 |
|
| 447 |
static void dcr_write_uic (void *opaque, int dcrn, target_ulong val) |
| 448 |
{
|
| 449 |
ppcuic_t *uic; |
| 450 |
|
| 451 |
uic = opaque; |
| 452 |
dcrn -= uic->dcr_base; |
| 453 |
#ifdef DEBUG_UIC
|
| 454 |
if (loglevel & CPU_LOG_INT) {
|
| 455 |
fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val); |
| 456 |
} |
| 457 |
#endif
|
| 458 |
switch (dcrn) {
|
| 459 |
case DCR_UICSR:
|
| 460 |
uic->uicsr &= ~val; |
| 461 |
ppcuic_trigger_irq(uic); |
| 462 |
break;
|
| 463 |
case DCR_UICSRS:
|
| 464 |
uic->uicsr |= val; |
| 465 |
ppcuic_trigger_irq(uic); |
| 466 |
break;
|
| 467 |
case DCR_UICER:
|
| 468 |
uic->uicer = val; |
| 469 |
ppcuic_trigger_irq(uic); |
| 470 |
break;
|
| 471 |
case DCR_UICCR:
|
| 472 |
uic->uiccr = val; |
| 473 |
ppcuic_trigger_irq(uic); |
| 474 |
break;
|
| 475 |
case DCR_UICPR:
|
| 476 |
uic->uicpr = val; |
| 477 |
ppcuic_trigger_irq(uic); |
| 478 |
break;
|
| 479 |
case DCR_UICTR:
|
| 480 |
uic->uictr = val; |
| 481 |
ppcuic_trigger_irq(uic); |
| 482 |
break;
|
| 483 |
case DCR_UICMSR:
|
| 484 |
break;
|
| 485 |
case DCR_UICVR:
|
| 486 |
break;
|
| 487 |
case DCR_UICVCR:
|
| 488 |
uic->uicvcr = val & 0xFFFFFFFD;
|
| 489 |
ppcuic_trigger_irq(uic); |
| 490 |
break;
|
| 491 |
} |
| 492 |
} |
| 493 |
|
| 494 |
static void ppcuic_reset (void *opaque) |
| 495 |
{
|
| 496 |
ppcuic_t *uic; |
| 497 |
|
| 498 |
uic = opaque; |
| 499 |
uic->uiccr = 0x00000000;
|
| 500 |
uic->uicer = 0x00000000;
|
| 501 |
uic->uicpr = 0x00000000;
|
| 502 |
uic->uicsr = 0x00000000;
|
| 503 |
uic->uictr = 0x00000000;
|
| 504 |
if (uic->use_vectors) {
|
| 505 |
uic->uicvcr = 0x00000000;
|
| 506 |
uic->uicvr = 0x0000000;
|
| 507 |
} |
| 508 |
} |
| 509 |
|
| 510 |
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, |
| 511 |
uint32_t dcr_base, int has_ssr, int has_vr) |
| 512 |
{
|
| 513 |
ppcuic_t *uic; |
| 514 |
int i;
|
| 515 |
|
| 516 |
uic = qemu_mallocz(sizeof(ppcuic_t));
|
| 517 |
if (uic != NULL) { |
| 518 |
uic->dcr_base = dcr_base; |
| 519 |
uic->irqs = irqs; |
| 520 |
if (has_vr)
|
| 521 |
uic->use_vectors = 1;
|
| 522 |
for (i = 0; i < DCR_UICMAX; i++) { |
| 523 |
ppc_dcr_register(env, dcr_base + i, uic, |
| 524 |
&dcr_read_uic, &dcr_write_uic); |
| 525 |
} |
| 526 |
qemu_register_reset(ppcuic_reset, uic); |
| 527 |
ppcuic_reset(uic); |
| 528 |
} |
| 529 |
|
| 530 |
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
|
| 531 |
} |