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1 | 0d78f544 | ths | /*
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2 | 0d78f544 | ths | * Renesas SH7751R R2D-PLUS emulation
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3 | 0d78f544 | ths | *
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4 | 0d78f544 | ths | * Copyright (c) 2007 Magnus Damm
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5 | b319feb7 | aurel32 | * Copyright (c) 2008 Paul Mundt
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6 | 0d78f544 | ths | *
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7 | 0d78f544 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 0d78f544 | ths | * of this software and associated documentation files (the "Software"), to deal
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9 | 0d78f544 | ths | * in the Software without restriction, including without limitation the rights
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10 | 0d78f544 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 0d78f544 | ths | * copies of the Software, and to permit persons to whom the Software is
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12 | 0d78f544 | ths | * furnished to do so, subject to the following conditions:
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13 | 0d78f544 | ths | *
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14 | 0d78f544 | ths | * The above copyright notice and this permission notice shall be included in
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15 | 0d78f544 | ths | * all copies or substantial portions of the Software.
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16 | 0d78f544 | ths | *
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17 | 0d78f544 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 0d78f544 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 0d78f544 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 0d78f544 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 0d78f544 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 0d78f544 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 0d78f544 | ths | * THE SOFTWARE.
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24 | 0d78f544 | ths | */
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25 | 0d78f544 | ths | |
26 | 87ecb68b | pbrook | #include "hw.h" |
27 | 87ecb68b | pbrook | #include "sh.h" |
28 | ffd39257 | blueswir1 | #include "devices.h" |
29 | 87ecb68b | pbrook | #include "sysemu.h" |
30 | 87ecb68b | pbrook | #include "boards.h" |
31 | c2f01775 | balrog | #include "pci.h" |
32 | c2f01775 | balrog | #include "net.h" |
33 | c2f01775 | balrog | #include "sh7750_regs.h" |
34 | 0d78f544 | ths | |
35 | 0d78f544 | ths | #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ |
36 | 0d78f544 | ths | #define SDRAM_SIZE 0x04000000 |
37 | 0d78f544 | ths | |
38 | ffd39257 | blueswir1 | #define SM501_VRAM_SIZE 0x800000 |
39 | ffd39257 | blueswir1 | |
40 | e8afa065 | aurel32 | /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
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41 | e8afa065 | aurel32 | #define LINUX_LOAD_OFFSET 0x800000 |
42 | e8afa065 | aurel32 | |
43 | d47ede60 | balrog | #define PA_IRLMSK 0x00 |
44 | b319feb7 | aurel32 | #define PA_POWOFF 0x30 |
45 | b319feb7 | aurel32 | #define PA_VERREG 0x32 |
46 | b319feb7 | aurel32 | #define PA_OUTPORT 0x36 |
47 | b319feb7 | aurel32 | |
48 | b319feb7 | aurel32 | typedef struct { |
49 | b319feb7 | aurel32 | uint16_t bcr; |
50 | d47ede60 | balrog | uint16_t irlmsk; |
51 | b319feb7 | aurel32 | uint16_t irlmon; |
52 | b319feb7 | aurel32 | uint16_t cfctl; |
53 | b319feb7 | aurel32 | uint16_t cfpow; |
54 | b319feb7 | aurel32 | uint16_t dispctl; |
55 | b319feb7 | aurel32 | uint16_t sdmpow; |
56 | b319feb7 | aurel32 | uint16_t rtcce; |
57 | b319feb7 | aurel32 | uint16_t pcicd; |
58 | b319feb7 | aurel32 | uint16_t voyagerrts; |
59 | b319feb7 | aurel32 | uint16_t cfrst; |
60 | b319feb7 | aurel32 | uint16_t admrts; |
61 | b319feb7 | aurel32 | uint16_t extrst; |
62 | b319feb7 | aurel32 | uint16_t cfcdintclr; |
63 | b319feb7 | aurel32 | uint16_t keyctlclr; |
64 | b319feb7 | aurel32 | uint16_t pad0; |
65 | b319feb7 | aurel32 | uint16_t pad1; |
66 | b319feb7 | aurel32 | uint16_t powoff; |
67 | b319feb7 | aurel32 | uint16_t verreg; |
68 | b319feb7 | aurel32 | uint16_t inport; |
69 | b319feb7 | aurel32 | uint16_t outport; |
70 | b319feb7 | aurel32 | uint16_t bverreg; |
71 | d47ede60 | balrog | |
72 | d47ede60 | balrog | /* output pin */
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73 | d47ede60 | balrog | qemu_irq irl; |
74 | b319feb7 | aurel32 | } r2d_fpga_t; |
75 | b319feb7 | aurel32 | |
76 | d47ede60 | balrog | enum r2d_fpga_irq {
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77 | d47ede60 | balrog | PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, |
78 | d47ede60 | balrog | SDCARD, PCI_INTA, PCI_INTB, EXT, TP, |
79 | d47ede60 | balrog | NR_IRQS |
80 | d47ede60 | balrog | }; |
81 | d47ede60 | balrog | |
82 | d47ede60 | balrog | static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { |
83 | d47ede60 | balrog | [CF_IDE] = { 1, 1<<9 }, |
84 | d47ede60 | balrog | [CF_CD] = { 2, 1<<8 }, |
85 | d47ede60 | balrog | [PCI_INTA] = { 9, 1<<14 }, |
86 | d47ede60 | balrog | [PCI_INTB] = { 10, 1<<13 }, |
87 | d47ede60 | balrog | [PCI_INTC] = { 3, 1<<12 }, |
88 | d47ede60 | balrog | [PCI_INTD] = { 0, 1<<11 }, |
89 | d47ede60 | balrog | [SM501] = { 4, 1<<10 }, |
90 | d47ede60 | balrog | [KEY] = { 5, 1<<6 }, |
91 | d47ede60 | balrog | [RTC_A] = { 6, 1<<5 }, |
92 | d47ede60 | balrog | [RTC_T] = { 7, 1<<4 }, |
93 | d47ede60 | balrog | [SDCARD] = { 8, 1<<7 }, |
94 | d47ede60 | balrog | [EXT] = { 11, 1<<0 }, |
95 | d47ede60 | balrog | [TP] = { 12, 1<<15 }, |
96 | d47ede60 | balrog | }; |
97 | d47ede60 | balrog | |
98 | d47ede60 | balrog | static void update_irl(r2d_fpga_t *fpga) |
99 | d47ede60 | balrog | { |
100 | d47ede60 | balrog | int i, irl = 15; |
101 | d47ede60 | balrog | for (i = 0; i < NR_IRQS; i++) |
102 | d47ede60 | balrog | if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
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103 | d47ede60 | balrog | if (irqtab[i].irl < irl)
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104 | d47ede60 | balrog | irl = irqtab[i].irl; |
105 | d47ede60 | balrog | qemu_set_irq(fpga->irl, irl ^ 15);
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106 | d47ede60 | balrog | } |
107 | d47ede60 | balrog | |
108 | d47ede60 | balrog | static void r2d_fpga_irq_set(void *opaque, int n, int level) |
109 | d47ede60 | balrog | { |
110 | d47ede60 | balrog | r2d_fpga_t *fpga = opaque; |
111 | d47ede60 | balrog | if (level)
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112 | d47ede60 | balrog | fpga->irlmon |= irqtab[n].msk; |
113 | d47ede60 | balrog | else
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114 | d47ede60 | balrog | fpga->irlmon &= ~irqtab[n].msk; |
115 | d47ede60 | balrog | update_irl(fpga); |
116 | d47ede60 | balrog | } |
117 | d47ede60 | balrog | |
118 | b319feb7 | aurel32 | static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr) |
119 | b319feb7 | aurel32 | { |
120 | b319feb7 | aurel32 | r2d_fpga_t *s = opaque; |
121 | b319feb7 | aurel32 | |
122 | b319feb7 | aurel32 | switch (addr) {
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123 | d47ede60 | balrog | case PA_IRLMSK:
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124 | d47ede60 | balrog | return s->irlmsk;
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125 | b319feb7 | aurel32 | case PA_OUTPORT:
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126 | b319feb7 | aurel32 | return s->outport;
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127 | b319feb7 | aurel32 | case PA_POWOFF:
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128 | b319feb7 | aurel32 | return s->powoff;
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129 | b319feb7 | aurel32 | case PA_VERREG:
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130 | b319feb7 | aurel32 | return 0x10; |
131 | b319feb7 | aurel32 | } |
132 | b319feb7 | aurel32 | |
133 | b319feb7 | aurel32 | return 0; |
134 | b319feb7 | aurel32 | } |
135 | b319feb7 | aurel32 | |
136 | b319feb7 | aurel32 | static void |
137 | b319feb7 | aurel32 | r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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138 | b319feb7 | aurel32 | { |
139 | b319feb7 | aurel32 | r2d_fpga_t *s = opaque; |
140 | b319feb7 | aurel32 | |
141 | b319feb7 | aurel32 | switch (addr) {
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142 | d47ede60 | balrog | case PA_IRLMSK:
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143 | d47ede60 | balrog | s->irlmsk = value; |
144 | d47ede60 | balrog | update_irl(s); |
145 | d47ede60 | balrog | break;
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146 | b319feb7 | aurel32 | case PA_OUTPORT:
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147 | b319feb7 | aurel32 | s->outport = value; |
148 | b319feb7 | aurel32 | break;
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149 | b319feb7 | aurel32 | case PA_POWOFF:
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150 | b319feb7 | aurel32 | s->powoff = value; |
151 | b319feb7 | aurel32 | break;
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152 | b319feb7 | aurel32 | case PA_VERREG:
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153 | b319feb7 | aurel32 | /* Discard writes */
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154 | b319feb7 | aurel32 | break;
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155 | b319feb7 | aurel32 | } |
156 | b319feb7 | aurel32 | } |
157 | b319feb7 | aurel32 | |
158 | b319feb7 | aurel32 | static CPUReadMemoryFunc *r2d_fpga_readfn[] = {
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159 | b319feb7 | aurel32 | r2d_fpga_read, |
160 | b319feb7 | aurel32 | r2d_fpga_read, |
161 | b2463a64 | aurel32 | NULL,
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162 | b319feb7 | aurel32 | }; |
163 | b319feb7 | aurel32 | |
164 | b319feb7 | aurel32 | static CPUWriteMemoryFunc *r2d_fpga_writefn[] = {
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165 | b319feb7 | aurel32 | r2d_fpga_write, |
166 | b319feb7 | aurel32 | r2d_fpga_write, |
167 | b2463a64 | aurel32 | NULL,
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168 | b319feb7 | aurel32 | }; |
169 | b319feb7 | aurel32 | |
170 | d47ede60 | balrog | static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
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171 | b319feb7 | aurel32 | { |
172 | b319feb7 | aurel32 | int iomemtype;
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173 | b319feb7 | aurel32 | r2d_fpga_t *s; |
174 | b319feb7 | aurel32 | |
175 | b319feb7 | aurel32 | s = qemu_mallocz(sizeof(r2d_fpga_t));
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176 | d47ede60 | balrog | |
177 | d47ede60 | balrog | s->irl = irl; |
178 | b319feb7 | aurel32 | |
179 | b319feb7 | aurel32 | iomemtype = cpu_register_io_memory(0, r2d_fpga_readfn,
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180 | b319feb7 | aurel32 | r2d_fpga_writefn, s); |
181 | b319feb7 | aurel32 | cpu_register_physical_memory(base, 0x40, iomemtype);
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182 | d47ede60 | balrog | return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
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183 | b319feb7 | aurel32 | } |
184 | b319feb7 | aurel32 | |
185 | c2f01775 | balrog | static void r2d_pci_set_irq(qemu_irq *p, int n, int l) |
186 | c2f01775 | balrog | { |
187 | c2f01775 | balrog | qemu_set_irq(p[n], l); |
188 | c2f01775 | balrog | } |
189 | c2f01775 | balrog | |
190 | c2f01775 | balrog | static int r2d_pci_map_irq(PCIDevice *d, int irq_num) |
191 | c2f01775 | balrog | { |
192 | c2f01775 | balrog | const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD }; |
193 | c2f01775 | balrog | return intx[d->devfn >> 3]; |
194 | c2f01775 | balrog | } |
195 | c2f01775 | balrog | |
196 | 00f82b8a | aurel32 | static void r2d_init(ram_addr_t ram_size, int vga_ram_size, |
197 | 3023f332 | aliguori | const char *boot_device, |
198 | 0d78f544 | ths | const char *kernel_filename, const char *kernel_cmdline, |
199 | 0d78f544 | ths | const char *initrd_filename, const char *cpu_model) |
200 | 0d78f544 | ths | { |
201 | 0d78f544 | ths | CPUState *env; |
202 | 0d78f544 | ths | struct SH7750State *s;
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203 | 44654490 | pbrook | ram_addr_t sdram_addr; |
204 | d47ede60 | balrog | qemu_irq *irq; |
205 | c2f01775 | balrog | PCIBus *pci; |
206 | c2f01775 | balrog | int i;
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207 | 0d78f544 | ths | |
208 | aaed909a | bellard | if (!cpu_model)
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209 | 0fd3ca30 | aurel32 | cpu_model = "SH7751R";
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210 | aaed909a | bellard | |
211 | aaed909a | bellard | env = cpu_init(cpu_model); |
212 | aaed909a | bellard | if (!env) {
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213 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
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214 | aaed909a | bellard | exit(1);
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215 | aaed909a | bellard | } |
216 | 0d78f544 | ths | |
217 | 0d78f544 | ths | /* Allocate memory space */
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218 | ffd39257 | blueswir1 | sdram_addr = qemu_ram_alloc(SDRAM_SIZE); |
219 | ffd39257 | blueswir1 | cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr); |
220 | 0d78f544 | ths | /* Register peripherals */
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221 | 0d78f544 | ths | s = sh7750_init(env); |
222 | d47ede60 | balrog | irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
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223 | c2f01775 | balrog | pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4); |
224 | d47ede60 | balrog | |
225 | ac611340 | aurel32 | sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]); |
226 | a4a771c0 | balrog | |
227 | a4a771c0 | balrog | /* onboard CF (True IDE mode, Master only). */
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228 | ab2da564 | aurel32 | if ((i = drive_get_index(IF_IDE, 0, 0)) != -1) |
229 | ab2da564 | aurel32 | mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1, |
230 | ab2da564 | aurel32 | drives_table[i].bdrv, NULL);
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231 | a4a771c0 | balrog | |
232 | c2f01775 | balrog | /* NIC: rtl8139 on-board, and 2 slots. */
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233 | ab2da564 | aurel32 | for (i = 0; i < nb_nics; i++) |
234 | ab2da564 | aurel32 | pci_nic_init(pci, &nd_table[i], (i==0)? 2<<3: -1, "rtl8139"); |
235 | c2f01775 | balrog | |
236 | 0d78f544 | ths | /* Todo: register on board registers */
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237 | e8afa065 | aurel32 | if (kernel_filename) {
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238 | 0d78f544 | ths | int kernel_size;
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239 | c2f01775 | balrog | /* initialization which should be done by firmware */
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240 | 0ec3ff52 | aurel32 | stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */ |
241 | 0ec3ff52 | aurel32 | stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */ |
242 | 0d78f544 | ths | |
243 | e8afa065 | aurel32 | if (kernel_cmdline) {
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244 | e8afa065 | aurel32 | kernel_size = load_image_targphys(kernel_filename, |
245 | e8afa065 | aurel32 | SDRAM_BASE + LINUX_LOAD_OFFSET, |
246 | e8afa065 | aurel32 | SDRAM_SIZE - LINUX_LOAD_OFFSET); |
247 | e8afa065 | aurel32 | env->pc = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000;
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248 | e8afa065 | aurel32 | pstrcpy_targphys(SDRAM_BASE + 0x10100, 256, kernel_cmdline); |
249 | e8afa065 | aurel32 | } else {
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250 | f3e3aa8c | aurel32 | kernel_size = load_image_targphys(kernel_filename, SDRAM_BASE, SDRAM_SIZE); |
251 | e8afa065 | aurel32 | env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */ |
252 | e8afa065 | aurel32 | } |
253 | 0d78f544 | ths | |
254 | 0d78f544 | ths | if (kernel_size < 0) { |
255 | 0d78f544 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
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256 | 0d78f544 | ths | exit(1);
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257 | 0d78f544 | ths | } |
258 | 0d78f544 | ths | } |
259 | 0d78f544 | ths | } |
260 | 0d78f544 | ths | |
261 | 0d78f544 | ths | QEMUMachine r2d_machine = { |
262 | 4b32e168 | aliguori | .name = "r2d",
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263 | 4b32e168 | aliguori | .desc = "r2d-plus board",
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264 | 4b32e168 | aliguori | .init = r2d_init, |
265 | 0d78f544 | ths | }; |