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/*
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 *  i386 helpers
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#define CPU_NO_GLOBAL_REGS
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#include "exec.h"
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#include "exec-all.h"
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#include "host-utils.h"
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//#define DEBUG_PCALL
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#ifdef DEBUG_PCALL
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#  define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__)
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#  define LOG_PCALL_STATE(env) \
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          log_cpu_state_mask(CPU_LOG_PCALL, (env), X86_DUMP_CCOP)
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#else
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#  define LOG_PCALL(...) do { } while (0)
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#  define LOG_PCALL_STATE(env) do { } while (0)
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#endif
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#if 0
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#define raise_exception_err(a, b)\
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do {\
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    qemu_log("raise_exception line=%d\n", __LINE__);\
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    (raise_exception_err)(a, b);\
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} while (0)
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#endif
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static const uint8_t parity_table[256] = {
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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};
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/* modulo 17 table */
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static const uint8_t rclw_table[32] = {
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    0, 1, 2, 3, 4, 5, 6, 7,
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    8, 9,10,11,12,13,14,15,
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   16, 0, 1, 2, 3, 4, 5, 6,
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    7, 8, 9,10,11,12,13,14,
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};
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/* modulo 9 table */
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static const uint8_t rclb_table[32] = {
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    0, 1, 2, 3, 4, 5, 6, 7,
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    8, 0, 1, 2, 3, 4, 5, 6,
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    7, 8, 0, 1, 2, 3, 4, 5,
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    6, 7, 8, 0, 1, 2, 3, 4,
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};
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static const CPU86_LDouble f15rk[7] =
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{
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    0.00000000000000000000L,
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    1.00000000000000000000L,
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    3.14159265358979323851L,  /*pi*/
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    0.30102999566398119523L,  /*lg2*/
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    0.69314718055994530943L,  /*ln2*/
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    1.44269504088896340739L,  /*l2e*/
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    3.32192809488736234781L,  /*l2t*/
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};
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/* broken thread support */
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static spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
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void helper_lock(void)
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{
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    spin_lock(&global_cpu_lock);
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}
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void helper_unlock(void)
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{
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    spin_unlock(&global_cpu_lock);
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}
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void helper_write_eflags(target_ulong t0, uint32_t update_mask)
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{
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    load_eflags(t0, update_mask);
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}
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target_ulong helper_read_eflags(void)
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{
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    uint32_t eflags;
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    eflags = helper_cc_compute_all(CC_OP);
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    eflags |= (DF & DF_MASK);
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    eflags |= env->eflags & ~(VM_MASK | RF_MASK);
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    return eflags;
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}
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/* return non zero if error */
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static inline int load_segment(uint32_t *e1_ptr, uint32_t *e2_ptr,
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                               int selector)
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{
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    SegmentCache *dt;
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    int index;
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    target_ulong ptr;
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    if (selector & 0x4)
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        dt = &env->ldt;
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    else
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        dt = &env->gdt;
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    index = selector & ~7;
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    if ((index + 7) > dt->limit)
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        return -1;
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    ptr = dt->base + index;
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    *e1_ptr = ldl_kernel(ptr);
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    *e2_ptr = ldl_kernel(ptr + 4);
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    return 0;
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}
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static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
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{
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    unsigned int limit;
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    limit = (e1 & 0xffff) | (e2 & 0x000f0000);
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    if (e2 & DESC_G_MASK)
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        limit = (limit << 12) | 0xfff;
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    return limit;
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}
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static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
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{
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    return ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
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}
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static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)
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{
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    sc->base = get_seg_base(e1, e2);
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    sc->limit = get_seg_limit(e1, e2);
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    sc->flags = e2;
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}
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/* init the segment cache in vm86 mode. */
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static inline void load_seg_vm(int seg, int selector)
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{
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    selector &= 0xffff;
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    cpu_x86_load_seg_cache(env, seg, selector,
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                           (selector << 4), 0xffff, 0);
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}
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static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
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                                       uint32_t *esp_ptr, int dpl)
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{
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    int type, index, shift;
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#if 0
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    {
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        int i;
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        printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
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        for(i=0;i<env->tr.limit;i++) {
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            printf("%02x ", env->tr.base[i]);
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            if ((i & 7) == 7) printf("\n");
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        }
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        printf("\n");
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    }
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#endif
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    if (!(env->tr.flags & DESC_P_MASK))
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        cpu_abort(env, "invalid tss");
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    type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
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    if ((type & 7) != 1)
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        cpu_abort(env, "invalid tss type");
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    shift = type >> 3;
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    index = (dpl * 4 + 2) << shift;
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    if (index + (4 << shift) - 1 > env->tr.limit)
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        raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
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    if (shift == 0) {
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        *esp_ptr = lduw_kernel(env->tr.base + index);
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        *ss_ptr = lduw_kernel(env->tr.base + index + 2);
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    } else {
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        *esp_ptr = ldl_kernel(env->tr.base + index);
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        *ss_ptr = lduw_kernel(env->tr.base + index + 4);
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    }
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}
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/* XXX: merge with load_seg() */
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static void tss_load_seg(int seg_reg, int selector)
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{
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    uint32_t e1, e2;
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    int rpl, dpl, cpl;
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    if ((selector & 0xfffc) != 0) {
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        if (load_segment(&e1, &e2, selector) != 0)
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            raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
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        if (!(e2 & DESC_S_MASK))
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            raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
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        rpl = selector & 3;
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        dpl = (e2 >> DESC_DPL_SHIFT) & 3;
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        cpl = env->hflags & HF_CPL_MASK;
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        if (seg_reg == R_CS) {
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            if (!(e2 & DESC_CS_MASK))
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                raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
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            /* XXX: is it correct ? */
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            if (dpl != rpl)
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                raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
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            if ((e2 & DESC_C_MASK) && dpl > rpl)
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                raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
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        } else if (seg_reg == R_SS) {
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            /* SS must be writable data */
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            if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
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                raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
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            if (dpl != cpl || dpl != rpl)
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                raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
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        } else {
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            /* not readable code */
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            if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))
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                raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
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            /* if data or non conforming code, checks the rights */
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            if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
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                if (dpl < cpl || dpl < rpl)
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                    raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
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            }
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        }
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        if (!(e2 & DESC_P_MASK))
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            raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
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        cpu_x86_load_seg_cache(env, seg_reg, selector,
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                       get_seg_base(e1, e2),
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                       get_seg_limit(e1, e2),
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                       e2);
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    } else {
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        if (seg_reg == R_SS || seg_reg == R_CS)
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            raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
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    }
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}
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#define SWITCH_TSS_JMP  0
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#define SWITCH_TSS_IRET 1
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#define SWITCH_TSS_CALL 2
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/* XXX: restore CPU state in registers (PowerPC case) */
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static void switch_tss(int tss_selector,
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                       uint32_t e1, uint32_t e2, int source,
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                       uint32_t next_eip)
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{
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    int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
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    target_ulong tss_base;
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    uint32_t new_regs[8], new_segs[6];
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    uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
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    uint32_t old_eflags, eflags_mask;
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    SegmentCache *dt;
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    int index;
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    target_ulong ptr;
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    type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
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    LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
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    /* if task gate, we read the TSS segment and we load it */
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    if (type == 5) {
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        if (!(e2 & DESC_P_MASK))
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            raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
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        tss_selector = e1 >> 16;
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        if (tss_selector & 4)
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            raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
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        if (load_segment(&e1, &e2, tss_selector) != 0)
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            raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
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        if (e2 & DESC_S_MASK)
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            raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
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        type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
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        if ((type & 7) != 1)
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            raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
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    }
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    if (!(e2 & DESC_P_MASK))
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        raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
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    if (type & 8)
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        tss_limit_max = 103;
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    else
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        tss_limit_max = 43;
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    tss_limit = get_seg_limit(e1, e2);
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    tss_base = get_seg_base(e1, e2);
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    if ((tss_selector & 4) != 0 ||
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        tss_limit < tss_limit_max)
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        raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
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    old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
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    if (old_type & 8)
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        old_tss_limit_max = 103;
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    else
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        old_tss_limit_max = 43;
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    /* read all the registers from the new TSS */
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    if (type & 8) {
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        /* 32 bit */
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        new_cr3 = ldl_kernel(tss_base + 0x1c);
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        new_eip = ldl_kernel(tss_base + 0x20);
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        new_eflags = ldl_kernel(tss_base + 0x24);
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        for(i = 0; i < 8; i++)
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            new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));
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        for(i = 0; i < 6; i++)
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            new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));
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        new_ldt = lduw_kernel(tss_base + 0x60);
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        new_trap = ldl_kernel(tss_base + 0x64);
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    } else {
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        /* 16 bit */
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        new_cr3 = 0;
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        new_eip = lduw_kernel(tss_base + 0x0e);
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        new_eflags = lduw_kernel(tss_base + 0x10);
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        for(i = 0; i < 8; i++)
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            new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) | 0xffff0000;
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        for(i = 0; i < 4; i++)
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            new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));
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        new_ldt = lduw_kernel(tss_base + 0x2a);
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        new_segs[R_FS] = 0;
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        new_segs[R_GS] = 0;
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        new_trap = 0;
350 eaa728ee bellard
    }
351 eaa728ee bellard
352 eaa728ee bellard
    /* NOTE: we must avoid memory exceptions during the task switch,
353 eaa728ee bellard
       so we make dummy accesses before */
354 eaa728ee bellard
    /* XXX: it can still fail in some cases, so a bigger hack is
355 eaa728ee bellard
       necessary to valid the TLB after having done the accesses */
356 eaa728ee bellard
357 eaa728ee bellard
    v1 = ldub_kernel(env->tr.base);
358 eaa728ee bellard
    v2 = ldub_kernel(env->tr.base + old_tss_limit_max);
359 eaa728ee bellard
    stb_kernel(env->tr.base, v1);
360 eaa728ee bellard
    stb_kernel(env->tr.base + old_tss_limit_max, v2);
361 eaa728ee bellard
362 eaa728ee bellard
    /* clear busy bit (it is restartable) */
363 eaa728ee bellard
    if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
364 eaa728ee bellard
        target_ulong ptr;
365 eaa728ee bellard
        uint32_t e2;
366 eaa728ee bellard
        ptr = env->gdt.base + (env->tr.selector & ~7);
367 eaa728ee bellard
        e2 = ldl_kernel(ptr + 4);
368 eaa728ee bellard
        e2 &= ~DESC_TSS_BUSY_MASK;
369 eaa728ee bellard
        stl_kernel(ptr + 4, e2);
370 eaa728ee bellard
    }
371 eaa728ee bellard
    old_eflags = compute_eflags();
372 eaa728ee bellard
    if (source == SWITCH_TSS_IRET)
373 eaa728ee bellard
        old_eflags &= ~NT_MASK;
374 eaa728ee bellard
375 eaa728ee bellard
    /* save the current state in the old TSS */
376 eaa728ee bellard
    if (type & 8) {
377 eaa728ee bellard
        /* 32 bit */
378 eaa728ee bellard
        stl_kernel(env->tr.base + 0x20, next_eip);
379 eaa728ee bellard
        stl_kernel(env->tr.base + 0x24, old_eflags);
380 eaa728ee bellard
        stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);
381 eaa728ee bellard
        stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);
382 eaa728ee bellard
        stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);
383 eaa728ee bellard
        stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);
384 eaa728ee bellard
        stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);
385 eaa728ee bellard
        stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);
386 eaa728ee bellard
        stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);
387 eaa728ee bellard
        stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);
388 eaa728ee bellard
        for(i = 0; i < 6; i++)
389 eaa728ee bellard
            stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
390 eaa728ee bellard
    } else {
391 eaa728ee bellard
        /* 16 bit */
392 eaa728ee bellard
        stw_kernel(env->tr.base + 0x0e, next_eip);
393 eaa728ee bellard
        stw_kernel(env->tr.base + 0x10, old_eflags);
394 eaa728ee bellard
        stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);
395 eaa728ee bellard
        stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);
396 eaa728ee bellard
        stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);
397 eaa728ee bellard
        stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);
398 eaa728ee bellard
        stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);
399 eaa728ee bellard
        stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);
400 eaa728ee bellard
        stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);
401 eaa728ee bellard
        stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);
402 eaa728ee bellard
        for(i = 0; i < 4; i++)
403 eaa728ee bellard
            stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
404 eaa728ee bellard
    }
405 eaa728ee bellard
406 eaa728ee bellard
    /* now if an exception occurs, it will occurs in the next task
407 eaa728ee bellard
       context */
408 eaa728ee bellard
409 eaa728ee bellard
    if (source == SWITCH_TSS_CALL) {
410 eaa728ee bellard
        stw_kernel(tss_base, env->tr.selector);
411 eaa728ee bellard
        new_eflags |= NT_MASK;
412 eaa728ee bellard
    }
413 eaa728ee bellard
414 eaa728ee bellard
    /* set busy bit */
415 eaa728ee bellard
    if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
416 eaa728ee bellard
        target_ulong ptr;
417 eaa728ee bellard
        uint32_t e2;
418 eaa728ee bellard
        ptr = env->gdt.base + (tss_selector & ~7);
419 eaa728ee bellard
        e2 = ldl_kernel(ptr + 4);
420 eaa728ee bellard
        e2 |= DESC_TSS_BUSY_MASK;
421 eaa728ee bellard
        stl_kernel(ptr + 4, e2);
422 eaa728ee bellard
    }
423 eaa728ee bellard
424 eaa728ee bellard
    /* set the new CPU state */
425 eaa728ee bellard
    /* from this point, any exception which occurs can give problems */
426 eaa728ee bellard
    env->cr[0] |= CR0_TS_MASK;
427 eaa728ee bellard
    env->hflags |= HF_TS_MASK;
428 eaa728ee bellard
    env->tr.selector = tss_selector;
429 eaa728ee bellard
    env->tr.base = tss_base;
430 eaa728ee bellard
    env->tr.limit = tss_limit;
431 eaa728ee bellard
    env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
432 eaa728ee bellard
433 eaa728ee bellard
    if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
434 eaa728ee bellard
        cpu_x86_update_cr3(env, new_cr3);
435 eaa728ee bellard
    }
436 eaa728ee bellard
437 eaa728ee bellard
    /* load all registers without an exception, then reload them with
438 eaa728ee bellard
       possible exception */
439 eaa728ee bellard
    env->eip = new_eip;
440 eaa728ee bellard
    eflags_mask = TF_MASK | AC_MASK | ID_MASK |
441 eaa728ee bellard
        IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
442 eaa728ee bellard
    if (!(type & 8))
443 eaa728ee bellard
        eflags_mask &= 0xffff;
444 eaa728ee bellard
    load_eflags(new_eflags, eflags_mask);
445 eaa728ee bellard
    /* XXX: what to do in 16 bit case ? */
446 eaa728ee bellard
    EAX = new_regs[0];
447 eaa728ee bellard
    ECX = new_regs[1];
448 eaa728ee bellard
    EDX = new_regs[2];
449 eaa728ee bellard
    EBX = new_regs[3];
450 eaa728ee bellard
    ESP = new_regs[4];
451 eaa728ee bellard
    EBP = new_regs[5];
452 eaa728ee bellard
    ESI = new_regs[6];
453 eaa728ee bellard
    EDI = new_regs[7];
454 eaa728ee bellard
    if (new_eflags & VM_MASK) {
455 eaa728ee bellard
        for(i = 0; i < 6; i++)
456 eaa728ee bellard
            load_seg_vm(i, new_segs[i]);
457 eaa728ee bellard
        /* in vm86, CPL is always 3 */
458 eaa728ee bellard
        cpu_x86_set_cpl(env, 3);
459 eaa728ee bellard
    } else {
460 eaa728ee bellard
        /* CPL is set the RPL of CS */
461 eaa728ee bellard
        cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
462 eaa728ee bellard
        /* first just selectors as the rest may trigger exceptions */
463 eaa728ee bellard
        for(i = 0; i < 6; i++)
464 eaa728ee bellard
            cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
465 eaa728ee bellard
    }
466 eaa728ee bellard
467 eaa728ee bellard
    env->ldt.selector = new_ldt & ~4;
468 eaa728ee bellard
    env->ldt.base = 0;
469 eaa728ee bellard
    env->ldt.limit = 0;
470 eaa728ee bellard
    env->ldt.flags = 0;
471 eaa728ee bellard
472 eaa728ee bellard
    /* load the LDT */
473 eaa728ee bellard
    if (new_ldt & 4)
474 eaa728ee bellard
        raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
475 eaa728ee bellard
476 eaa728ee bellard
    if ((new_ldt & 0xfffc) != 0) {
477 eaa728ee bellard
        dt = &env->gdt;
478 eaa728ee bellard
        index = new_ldt & ~7;
479 eaa728ee bellard
        if ((index + 7) > dt->limit)
480 eaa728ee bellard
            raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
481 eaa728ee bellard
        ptr = dt->base + index;
482 eaa728ee bellard
        e1 = ldl_kernel(ptr);
483 eaa728ee bellard
        e2 = ldl_kernel(ptr + 4);
484 eaa728ee bellard
        if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
485 eaa728ee bellard
            raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
486 eaa728ee bellard
        if (!(e2 & DESC_P_MASK))
487 eaa728ee bellard
            raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
488 eaa728ee bellard
        load_seg_cache_raw_dt(&env->ldt, e1, e2);
489 eaa728ee bellard
    }
490 eaa728ee bellard
491 eaa728ee bellard
    /* load the segments */
492 eaa728ee bellard
    if (!(new_eflags & VM_MASK)) {
493 eaa728ee bellard
        tss_load_seg(R_CS, new_segs[R_CS]);
494 eaa728ee bellard
        tss_load_seg(R_SS, new_segs[R_SS]);
495 eaa728ee bellard
        tss_load_seg(R_ES, new_segs[R_ES]);
496 eaa728ee bellard
        tss_load_seg(R_DS, new_segs[R_DS]);
497 eaa728ee bellard
        tss_load_seg(R_FS, new_segs[R_FS]);
498 eaa728ee bellard
        tss_load_seg(R_GS, new_segs[R_GS]);
499 eaa728ee bellard
    }
500 eaa728ee bellard
501 eaa728ee bellard
    /* check that EIP is in the CS segment limits */
502 eaa728ee bellard
    if (new_eip > env->segs[R_CS].limit) {
503 eaa728ee bellard
        /* XXX: different exception if CALL ? */
504 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, 0);
505 eaa728ee bellard
    }
506 01df040b aliguori
507 01df040b aliguori
#ifndef CONFIG_USER_ONLY
508 01df040b aliguori
    /* reset local breakpoints */
509 01df040b aliguori
    if (env->dr[7] & 0x55) {
510 01df040b aliguori
        for (i = 0; i < 4; i++) {
511 01df040b aliguori
            if (hw_breakpoint_enabled(env->dr[7], i) == 0x1)
512 01df040b aliguori
                hw_breakpoint_remove(env, i);
513 01df040b aliguori
        }
514 01df040b aliguori
        env->dr[7] &= ~0x55;
515 01df040b aliguori
    }
516 01df040b aliguori
#endif
517 eaa728ee bellard
}
518 eaa728ee bellard
519 eaa728ee bellard
/* check if Port I/O is allowed in TSS */
520 eaa728ee bellard
static inline void check_io(int addr, int size)
521 eaa728ee bellard
{
522 eaa728ee bellard
    int io_offset, val, mask;
523 eaa728ee bellard
524 eaa728ee bellard
    /* TSS must be a valid 32 bit one */
525 eaa728ee bellard
    if (!(env->tr.flags & DESC_P_MASK) ||
526 eaa728ee bellard
        ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
527 eaa728ee bellard
        env->tr.limit < 103)
528 eaa728ee bellard
        goto fail;
529 eaa728ee bellard
    io_offset = lduw_kernel(env->tr.base + 0x66);
530 eaa728ee bellard
    io_offset += (addr >> 3);
531 eaa728ee bellard
    /* Note: the check needs two bytes */
532 eaa728ee bellard
    if ((io_offset + 1) > env->tr.limit)
533 eaa728ee bellard
        goto fail;
534 eaa728ee bellard
    val = lduw_kernel(env->tr.base + io_offset);
535 eaa728ee bellard
    val >>= (addr & 7);
536 eaa728ee bellard
    mask = (1 << size) - 1;
537 eaa728ee bellard
    /* all bits must be zero to allow the I/O */
538 eaa728ee bellard
    if ((val & mask) != 0) {
539 eaa728ee bellard
    fail:
540 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, 0);
541 eaa728ee bellard
    }
542 eaa728ee bellard
}
543 eaa728ee bellard
544 eaa728ee bellard
void helper_check_iob(uint32_t t0)
545 eaa728ee bellard
{
546 eaa728ee bellard
    check_io(t0, 1);
547 eaa728ee bellard
}
548 eaa728ee bellard
549 eaa728ee bellard
void helper_check_iow(uint32_t t0)
550 eaa728ee bellard
{
551 eaa728ee bellard
    check_io(t0, 2);
552 eaa728ee bellard
}
553 eaa728ee bellard
554 eaa728ee bellard
void helper_check_iol(uint32_t t0)
555 eaa728ee bellard
{
556 eaa728ee bellard
    check_io(t0, 4);
557 eaa728ee bellard
}
558 eaa728ee bellard
559 eaa728ee bellard
void helper_outb(uint32_t port, uint32_t data)
560 eaa728ee bellard
{
561 eaa728ee bellard
    cpu_outb(env, port, data & 0xff);
562 eaa728ee bellard
}
563 eaa728ee bellard
564 eaa728ee bellard
target_ulong helper_inb(uint32_t port)
565 eaa728ee bellard
{
566 eaa728ee bellard
    return cpu_inb(env, port);
567 eaa728ee bellard
}
568 eaa728ee bellard
569 eaa728ee bellard
void helper_outw(uint32_t port, uint32_t data)
570 eaa728ee bellard
{
571 eaa728ee bellard
    cpu_outw(env, port, data & 0xffff);
572 eaa728ee bellard
}
573 eaa728ee bellard
574 eaa728ee bellard
target_ulong helper_inw(uint32_t port)
575 eaa728ee bellard
{
576 eaa728ee bellard
    return cpu_inw(env, port);
577 eaa728ee bellard
}
578 eaa728ee bellard
579 eaa728ee bellard
void helper_outl(uint32_t port, uint32_t data)
580 eaa728ee bellard
{
581 eaa728ee bellard
    cpu_outl(env, port, data);
582 eaa728ee bellard
}
583 eaa728ee bellard
584 eaa728ee bellard
target_ulong helper_inl(uint32_t port)
585 eaa728ee bellard
{
586 eaa728ee bellard
    return cpu_inl(env, port);
587 eaa728ee bellard
}
588 eaa728ee bellard
589 eaa728ee bellard
static inline unsigned int get_sp_mask(unsigned int e2)
590 eaa728ee bellard
{
591 eaa728ee bellard
    if (e2 & DESC_B_MASK)
592 eaa728ee bellard
        return 0xffffffff;
593 eaa728ee bellard
    else
594 eaa728ee bellard
        return 0xffff;
595 eaa728ee bellard
}
596 eaa728ee bellard
597 2ed51f5b aliguori
static int exeption_has_error_code(int intno)
598 2ed51f5b aliguori
{
599 2ed51f5b aliguori
        switch(intno) {
600 2ed51f5b aliguori
        case 8:
601 2ed51f5b aliguori
        case 10:
602 2ed51f5b aliguori
        case 11:
603 2ed51f5b aliguori
        case 12:
604 2ed51f5b aliguori
        case 13:
605 2ed51f5b aliguori
        case 14:
606 2ed51f5b aliguori
        case 17:
607 2ed51f5b aliguori
            return 1;
608 2ed51f5b aliguori
        }
609 2ed51f5b aliguori
        return 0;
610 2ed51f5b aliguori
}
611 2ed51f5b aliguori
612 eaa728ee bellard
#ifdef TARGET_X86_64
613 eaa728ee bellard
#define SET_ESP(val, sp_mask)\
614 eaa728ee bellard
do {\
615 eaa728ee bellard
    if ((sp_mask) == 0xffff)\
616 eaa728ee bellard
        ESP = (ESP & ~0xffff) | ((val) & 0xffff);\
617 eaa728ee bellard
    else if ((sp_mask) == 0xffffffffLL)\
618 eaa728ee bellard
        ESP = (uint32_t)(val);\
619 eaa728ee bellard
    else\
620 eaa728ee bellard
        ESP = (val);\
621 eaa728ee bellard
} while (0)
622 eaa728ee bellard
#else
623 eaa728ee bellard
#define SET_ESP(val, sp_mask) ESP = (ESP & ~(sp_mask)) | ((val) & (sp_mask))
624 eaa728ee bellard
#endif
625 eaa728ee bellard
626 c0a04f0e aliguori
/* in 64-bit machines, this can overflow. So this segment addition macro
627 c0a04f0e aliguori
 * can be used to trim the value to 32-bit whenever needed */
628 c0a04f0e aliguori
#define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))
629 c0a04f0e aliguori
630 eaa728ee bellard
/* XXX: add a is_user flag to have proper security support */
631 eaa728ee bellard
#define PUSHW(ssp, sp, sp_mask, val)\
632 eaa728ee bellard
{\
633 eaa728ee bellard
    sp -= 2;\
634 eaa728ee bellard
    stw_kernel((ssp) + (sp & (sp_mask)), (val));\
635 eaa728ee bellard
}
636 eaa728ee bellard
637 eaa728ee bellard
#define PUSHL(ssp, sp, sp_mask, val)\
638 eaa728ee bellard
{\
639 eaa728ee bellard
    sp -= 4;\
640 c0a04f0e aliguori
    stl_kernel(SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val));\
641 eaa728ee bellard
}
642 eaa728ee bellard
643 eaa728ee bellard
#define POPW(ssp, sp, sp_mask, val)\
644 eaa728ee bellard
{\
645 eaa728ee bellard
    val = lduw_kernel((ssp) + (sp & (sp_mask)));\
646 eaa728ee bellard
    sp += 2;\
647 eaa728ee bellard
}
648 eaa728ee bellard
649 eaa728ee bellard
#define POPL(ssp, sp, sp_mask, val)\
650 eaa728ee bellard
{\
651 c0a04f0e aliguori
    val = (uint32_t)ldl_kernel(SEG_ADDL(ssp, sp, sp_mask));\
652 eaa728ee bellard
    sp += 4;\
653 eaa728ee bellard
}
654 eaa728ee bellard
655 eaa728ee bellard
/* protected mode interrupt */
656 eaa728ee bellard
static void do_interrupt_protected(int intno, int is_int, int error_code,
657 eaa728ee bellard
                                   unsigned int next_eip, int is_hw)
658 eaa728ee bellard
{
659 eaa728ee bellard
    SegmentCache *dt;
660 eaa728ee bellard
    target_ulong ptr, ssp;
661 eaa728ee bellard
    int type, dpl, selector, ss_dpl, cpl;
662 eaa728ee bellard
    int has_error_code, new_stack, shift;
663 1c918eba blueswir1
    uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0;
664 eaa728ee bellard
    uint32_t old_eip, sp_mask;
665 eaa728ee bellard
666 eaa728ee bellard
    has_error_code = 0;
667 2ed51f5b aliguori
    if (!is_int && !is_hw)
668 2ed51f5b aliguori
        has_error_code = exeption_has_error_code(intno);
669 eaa728ee bellard
    if (is_int)
670 eaa728ee bellard
        old_eip = next_eip;
671 eaa728ee bellard
    else
672 eaa728ee bellard
        old_eip = env->eip;
673 eaa728ee bellard
674 eaa728ee bellard
    dt = &env->idt;
675 eaa728ee bellard
    if (intno * 8 + 7 > dt->limit)
676 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
677 eaa728ee bellard
    ptr = dt->base + intno * 8;
678 eaa728ee bellard
    e1 = ldl_kernel(ptr);
679 eaa728ee bellard
    e2 = ldl_kernel(ptr + 4);
680 eaa728ee bellard
    /* check gate type */
681 eaa728ee bellard
    type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
682 eaa728ee bellard
    switch(type) {
683 eaa728ee bellard
    case 5: /* task gate */
684 eaa728ee bellard
        /* must do that check here to return the correct error code */
685 eaa728ee bellard
        if (!(e2 & DESC_P_MASK))
686 eaa728ee bellard
            raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
687 eaa728ee bellard
        switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
688 eaa728ee bellard
        if (has_error_code) {
689 eaa728ee bellard
            int type;
690 eaa728ee bellard
            uint32_t mask;
691 eaa728ee bellard
            /* push the error code */
692 eaa728ee bellard
            type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
693 eaa728ee bellard
            shift = type >> 3;
694 eaa728ee bellard
            if (env->segs[R_SS].flags & DESC_B_MASK)
695 eaa728ee bellard
                mask = 0xffffffff;
696 eaa728ee bellard
            else
697 eaa728ee bellard
                mask = 0xffff;
698 eaa728ee bellard
            esp = (ESP - (2 << shift)) & mask;
699 eaa728ee bellard
            ssp = env->segs[R_SS].base + esp;
700 eaa728ee bellard
            if (shift)
701 eaa728ee bellard
                stl_kernel(ssp, error_code);
702 eaa728ee bellard
            else
703 eaa728ee bellard
                stw_kernel(ssp, error_code);
704 eaa728ee bellard
            SET_ESP(esp, mask);
705 eaa728ee bellard
        }
706 eaa728ee bellard
        return;
707 eaa728ee bellard
    case 6: /* 286 interrupt gate */
708 eaa728ee bellard
    case 7: /* 286 trap gate */
709 eaa728ee bellard
    case 14: /* 386 interrupt gate */
710 eaa728ee bellard
    case 15: /* 386 trap gate */
711 eaa728ee bellard
        break;
712 eaa728ee bellard
    default:
713 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
714 eaa728ee bellard
        break;
715 eaa728ee bellard
    }
716 eaa728ee bellard
    dpl = (e2 >> DESC_DPL_SHIFT) & 3;
717 eaa728ee bellard
    cpl = env->hflags & HF_CPL_MASK;
718 1235fc06 ths
    /* check privilege if software int */
719 eaa728ee bellard
    if (is_int && dpl < cpl)
720 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
721 eaa728ee bellard
    /* check valid bit */
722 eaa728ee bellard
    if (!(e2 & DESC_P_MASK))
723 eaa728ee bellard
        raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
724 eaa728ee bellard
    selector = e1 >> 16;
725 eaa728ee bellard
    offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
726 eaa728ee bellard
    if ((selector & 0xfffc) == 0)
727 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, 0);
728 eaa728ee bellard
729 eaa728ee bellard
    if (load_segment(&e1, &e2, selector) != 0)
730 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
731 eaa728ee bellard
    if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
732 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
733 eaa728ee bellard
    dpl = (e2 >> DESC_DPL_SHIFT) & 3;
734 eaa728ee bellard
    if (dpl > cpl)
735 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
736 eaa728ee bellard
    if (!(e2 & DESC_P_MASK))
737 eaa728ee bellard
        raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
738 eaa728ee bellard
    if (!(e2 & DESC_C_MASK) && dpl < cpl) {
739 eaa728ee bellard
        /* to inner privilege */
740 eaa728ee bellard
        get_ss_esp_from_tss(&ss, &esp, dpl);
741 eaa728ee bellard
        if ((ss & 0xfffc) == 0)
742 eaa728ee bellard
            raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
743 eaa728ee bellard
        if ((ss & 3) != dpl)
744 eaa728ee bellard
            raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
745 eaa728ee bellard
        if (load_segment(&ss_e1, &ss_e2, ss) != 0)
746 eaa728ee bellard
            raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
747 eaa728ee bellard
        ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
748 eaa728ee bellard
        if (ss_dpl != dpl)
749 eaa728ee bellard
            raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
750 eaa728ee bellard
        if (!(ss_e2 & DESC_S_MASK) ||
751 eaa728ee bellard
            (ss_e2 & DESC_CS_MASK) ||
752 eaa728ee bellard
            !(ss_e2 & DESC_W_MASK))
753 eaa728ee bellard
            raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
754 eaa728ee bellard
        if (!(ss_e2 & DESC_P_MASK))
755 eaa728ee bellard
            raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
756 eaa728ee bellard
        new_stack = 1;
757 eaa728ee bellard
        sp_mask = get_sp_mask(ss_e2);
758 eaa728ee bellard
        ssp = get_seg_base(ss_e1, ss_e2);
759 eaa728ee bellard
    } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
760 eaa728ee bellard
        /* to same privilege */
761 eaa728ee bellard
        if (env->eflags & VM_MASK)
762 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
763 eaa728ee bellard
        new_stack = 0;
764 eaa728ee bellard
        sp_mask = get_sp_mask(env->segs[R_SS].flags);
765 eaa728ee bellard
        ssp = env->segs[R_SS].base;
766 eaa728ee bellard
        esp = ESP;
767 eaa728ee bellard
        dpl = cpl;
768 eaa728ee bellard
    } else {
769 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
770 eaa728ee bellard
        new_stack = 0; /* avoid warning */
771 eaa728ee bellard
        sp_mask = 0; /* avoid warning */
772 eaa728ee bellard
        ssp = 0; /* avoid warning */
773 eaa728ee bellard
        esp = 0; /* avoid warning */
774 eaa728ee bellard
    }
775 eaa728ee bellard
776 eaa728ee bellard
    shift = type >> 3;
777 eaa728ee bellard
778 eaa728ee bellard
#if 0
779 eaa728ee bellard
    /* XXX: check that enough room is available */
780 eaa728ee bellard
    push_size = 6 + (new_stack << 2) + (has_error_code << 1);
781 eaa728ee bellard
    if (env->eflags & VM_MASK)
782 eaa728ee bellard
        push_size += 8;
783 eaa728ee bellard
    push_size <<= shift;
784 eaa728ee bellard
#endif
785 eaa728ee bellard
    if (shift == 1) {
786 eaa728ee bellard
        if (new_stack) {
787 eaa728ee bellard
            if (env->eflags & VM_MASK) {
788 eaa728ee bellard
                PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
789 eaa728ee bellard
                PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
790 eaa728ee bellard
                PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
791 eaa728ee bellard
                PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
792 eaa728ee bellard
            }
793 eaa728ee bellard
            PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
794 eaa728ee bellard
            PUSHL(ssp, esp, sp_mask, ESP);
795 eaa728ee bellard
        }
796 eaa728ee bellard
        PUSHL(ssp, esp, sp_mask, compute_eflags());
797 eaa728ee bellard
        PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
798 eaa728ee bellard
        PUSHL(ssp, esp, sp_mask, old_eip);
799 eaa728ee bellard
        if (has_error_code) {
800 eaa728ee bellard
            PUSHL(ssp, esp, sp_mask, error_code);
801 eaa728ee bellard
        }
802 eaa728ee bellard
    } else {
803 eaa728ee bellard
        if (new_stack) {
804 eaa728ee bellard
            if (env->eflags & VM_MASK) {
805 eaa728ee bellard
                PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
806 eaa728ee bellard
                PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
807 eaa728ee bellard
                PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
808 eaa728ee bellard
                PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
809 eaa728ee bellard
            }
810 eaa728ee bellard
            PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
811 eaa728ee bellard
            PUSHW(ssp, esp, sp_mask, ESP);
812 eaa728ee bellard
        }
813 eaa728ee bellard
        PUSHW(ssp, esp, sp_mask, compute_eflags());
814 eaa728ee bellard
        PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
815 eaa728ee bellard
        PUSHW(ssp, esp, sp_mask, old_eip);
816 eaa728ee bellard
        if (has_error_code) {
817 eaa728ee bellard
            PUSHW(ssp, esp, sp_mask, error_code);
818 eaa728ee bellard
        }
819 eaa728ee bellard
    }
820 eaa728ee bellard
821 eaa728ee bellard
    if (new_stack) {
822 eaa728ee bellard
        if (env->eflags & VM_MASK) {
823 eaa728ee bellard
            cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
824 eaa728ee bellard
            cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
825 eaa728ee bellard
            cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
826 eaa728ee bellard
            cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
827 eaa728ee bellard
        }
828 eaa728ee bellard
        ss = (ss & ~3) | dpl;
829 eaa728ee bellard
        cpu_x86_load_seg_cache(env, R_SS, ss,
830 eaa728ee bellard
                               ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
831 eaa728ee bellard
    }
832 eaa728ee bellard
    SET_ESP(esp, sp_mask);
833 eaa728ee bellard
834 eaa728ee bellard
    selector = (selector & ~3) | dpl;
835 eaa728ee bellard
    cpu_x86_load_seg_cache(env, R_CS, selector,
836 eaa728ee bellard
                   get_seg_base(e1, e2),
837 eaa728ee bellard
                   get_seg_limit(e1, e2),
838 eaa728ee bellard
                   e2);
839 eaa728ee bellard
    cpu_x86_set_cpl(env, dpl);
840 eaa728ee bellard
    env->eip = offset;
841 eaa728ee bellard
842 eaa728ee bellard
    /* interrupt gate clear IF mask */
843 eaa728ee bellard
    if ((type & 1) == 0) {
844 eaa728ee bellard
        env->eflags &= ~IF_MASK;
845 eaa728ee bellard
    }
846 eaa728ee bellard
    env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
847 eaa728ee bellard
}
848 eaa728ee bellard
849 eaa728ee bellard
#ifdef TARGET_X86_64
850 eaa728ee bellard
851 eaa728ee bellard
#define PUSHQ(sp, val)\
852 eaa728ee bellard
{\
853 eaa728ee bellard
    sp -= 8;\
854 eaa728ee bellard
    stq_kernel(sp, (val));\
855 eaa728ee bellard
}
856 eaa728ee bellard
857 eaa728ee bellard
#define POPQ(sp, val)\
858 eaa728ee bellard
{\
859 eaa728ee bellard
    val = ldq_kernel(sp);\
860 eaa728ee bellard
    sp += 8;\
861 eaa728ee bellard
}
862 eaa728ee bellard
863 eaa728ee bellard
static inline target_ulong get_rsp_from_tss(int level)
864 eaa728ee bellard
{
865 eaa728ee bellard
    int index;
866 eaa728ee bellard
867 eaa728ee bellard
#if 0
868 eaa728ee bellard
    printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
869 eaa728ee bellard
           env->tr.base, env->tr.limit);
870 eaa728ee bellard
#endif
871 eaa728ee bellard
872 eaa728ee bellard
    if (!(env->tr.flags & DESC_P_MASK))
873 eaa728ee bellard
        cpu_abort(env, "invalid tss");
874 eaa728ee bellard
    index = 8 * level + 4;
875 eaa728ee bellard
    if ((index + 7) > env->tr.limit)
876 eaa728ee bellard
        raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
877 eaa728ee bellard
    return ldq_kernel(env->tr.base + index);
878 eaa728ee bellard
}
879 eaa728ee bellard
880 eaa728ee bellard
/* 64 bit interrupt */
881 eaa728ee bellard
static void do_interrupt64(int intno, int is_int, int error_code,
882 eaa728ee bellard
                           target_ulong next_eip, int is_hw)
883 eaa728ee bellard
{
884 eaa728ee bellard
    SegmentCache *dt;
885 eaa728ee bellard
    target_ulong ptr;
886 eaa728ee bellard
    int type, dpl, selector, cpl, ist;
887 eaa728ee bellard
    int has_error_code, new_stack;
888 eaa728ee bellard
    uint32_t e1, e2, e3, ss;
889 eaa728ee bellard
    target_ulong old_eip, esp, offset;
890 eaa728ee bellard
891 eaa728ee bellard
    has_error_code = 0;
892 2ed51f5b aliguori
    if (!is_int && !is_hw)
893 2ed51f5b aliguori
        has_error_code = exeption_has_error_code(intno);
894 eaa728ee bellard
    if (is_int)
895 eaa728ee bellard
        old_eip = next_eip;
896 eaa728ee bellard
    else
897 eaa728ee bellard
        old_eip = env->eip;
898 eaa728ee bellard
899 eaa728ee bellard
    dt = &env->idt;
900 eaa728ee bellard
    if (intno * 16 + 15 > dt->limit)
901 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
902 eaa728ee bellard
    ptr = dt->base + intno * 16;
903 eaa728ee bellard
    e1 = ldl_kernel(ptr);
904 eaa728ee bellard
    e2 = ldl_kernel(ptr + 4);
905 eaa728ee bellard
    e3 = ldl_kernel(ptr + 8);
906 eaa728ee bellard
    /* check gate type */
907 eaa728ee bellard
    type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
908 eaa728ee bellard
    switch(type) {
909 eaa728ee bellard
    case 14: /* 386 interrupt gate */
910 eaa728ee bellard
    case 15: /* 386 trap gate */
911 eaa728ee bellard
        break;
912 eaa728ee bellard
    default:
913 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
914 eaa728ee bellard
        break;
915 eaa728ee bellard
    }
916 eaa728ee bellard
    dpl = (e2 >> DESC_DPL_SHIFT) & 3;
917 eaa728ee bellard
    cpl = env->hflags & HF_CPL_MASK;
918 1235fc06 ths
    /* check privilege if software int */
919 eaa728ee bellard
    if (is_int && dpl < cpl)
920 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
921 eaa728ee bellard
    /* check valid bit */
922 eaa728ee bellard
    if (!(e2 & DESC_P_MASK))
923 eaa728ee bellard
        raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2);
924 eaa728ee bellard
    selector = e1 >> 16;
925 eaa728ee bellard
    offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
926 eaa728ee bellard
    ist = e2 & 7;
927 eaa728ee bellard
    if ((selector & 0xfffc) == 0)
928 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, 0);
929 eaa728ee bellard
930 eaa728ee bellard
    if (load_segment(&e1, &e2, selector) != 0)
931 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
932 eaa728ee bellard
    if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
933 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
934 eaa728ee bellard
    dpl = (e2 >> DESC_DPL_SHIFT) & 3;
935 eaa728ee bellard
    if (dpl > cpl)
936 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
937 eaa728ee bellard
    if (!(e2 & DESC_P_MASK))
938 eaa728ee bellard
        raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
939 eaa728ee bellard
    if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK))
940 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
941 eaa728ee bellard
    if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
942 eaa728ee bellard
        /* to inner privilege */
943 eaa728ee bellard
        if (ist != 0)
944 eaa728ee bellard
            esp = get_rsp_from_tss(ist + 3);
945 eaa728ee bellard
        else
946 eaa728ee bellard
            esp = get_rsp_from_tss(dpl);
947 eaa728ee bellard
        esp &= ~0xfLL; /* align stack */
948 eaa728ee bellard
        ss = 0;
949 eaa728ee bellard
        new_stack = 1;
950 eaa728ee bellard
    } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
951 eaa728ee bellard
        /* to same privilege */
952 eaa728ee bellard
        if (env->eflags & VM_MASK)
953 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
954 eaa728ee bellard
        new_stack = 0;
955 eaa728ee bellard
        if (ist != 0)
956 eaa728ee bellard
            esp = get_rsp_from_tss(ist + 3);
957 eaa728ee bellard
        else
958 eaa728ee bellard
            esp = ESP;
959 eaa728ee bellard
        esp &= ~0xfLL; /* align stack */
960 eaa728ee bellard
        dpl = cpl;
961 eaa728ee bellard
    } else {
962 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
963 eaa728ee bellard
        new_stack = 0; /* avoid warning */
964 eaa728ee bellard
        esp = 0; /* avoid warning */
965 eaa728ee bellard
    }
966 eaa728ee bellard
967 eaa728ee bellard
    PUSHQ(esp, env->segs[R_SS].selector);
968 eaa728ee bellard
    PUSHQ(esp, ESP);
969 eaa728ee bellard
    PUSHQ(esp, compute_eflags());
970 eaa728ee bellard
    PUSHQ(esp, env->segs[R_CS].selector);
971 eaa728ee bellard
    PUSHQ(esp, old_eip);
972 eaa728ee bellard
    if (has_error_code) {
973 eaa728ee bellard
        PUSHQ(esp, error_code);
974 eaa728ee bellard
    }
975 eaa728ee bellard
976 eaa728ee bellard
    if (new_stack) {
977 eaa728ee bellard
        ss = 0 | dpl;
978 eaa728ee bellard
        cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
979 eaa728ee bellard
    }
980 eaa728ee bellard
    ESP = esp;
981 eaa728ee bellard
982 eaa728ee bellard
    selector = (selector & ~3) | dpl;
983 eaa728ee bellard
    cpu_x86_load_seg_cache(env, R_CS, selector,
984 eaa728ee bellard
                   get_seg_base(e1, e2),
985 eaa728ee bellard
                   get_seg_limit(e1, e2),
986 eaa728ee bellard
                   e2);
987 eaa728ee bellard
    cpu_x86_set_cpl(env, dpl);
988 eaa728ee bellard
    env->eip = offset;
989 eaa728ee bellard
990 eaa728ee bellard
    /* interrupt gate clear IF mask */
991 eaa728ee bellard
    if ((type & 1) == 0) {
992 eaa728ee bellard
        env->eflags &= ~IF_MASK;
993 eaa728ee bellard
    }
994 eaa728ee bellard
    env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
995 eaa728ee bellard
}
996 eaa728ee bellard
#endif
997 eaa728ee bellard
998 d9957a8b blueswir1
#ifdef TARGET_X86_64
999 eaa728ee bellard
#if defined(CONFIG_USER_ONLY)
1000 eaa728ee bellard
void helper_syscall(int next_eip_addend)
1001 eaa728ee bellard
{
1002 eaa728ee bellard
    env->exception_index = EXCP_SYSCALL;
1003 eaa728ee bellard
    env->exception_next_eip = env->eip + next_eip_addend;
1004 eaa728ee bellard
    cpu_loop_exit();
1005 eaa728ee bellard
}
1006 eaa728ee bellard
#else
1007 eaa728ee bellard
void helper_syscall(int next_eip_addend)
1008 eaa728ee bellard
{
1009 eaa728ee bellard
    int selector;
1010 eaa728ee bellard
1011 eaa728ee bellard
    if (!(env->efer & MSR_EFER_SCE)) {
1012 eaa728ee bellard
        raise_exception_err(EXCP06_ILLOP, 0);
1013 eaa728ee bellard
    }
1014 eaa728ee bellard
    selector = (env->star >> 32) & 0xffff;
1015 eaa728ee bellard
    if (env->hflags & HF_LMA_MASK) {
1016 eaa728ee bellard
        int code64;
1017 eaa728ee bellard
1018 eaa728ee bellard
        ECX = env->eip + next_eip_addend;
1019 eaa728ee bellard
        env->regs[11] = compute_eflags();
1020 eaa728ee bellard
1021 eaa728ee bellard
        code64 = env->hflags & HF_CS64_MASK;
1022 eaa728ee bellard
1023 eaa728ee bellard
        cpu_x86_set_cpl(env, 0);
1024 eaa728ee bellard
        cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1025 eaa728ee bellard
                           0, 0xffffffff,
1026 eaa728ee bellard
                               DESC_G_MASK | DESC_P_MASK |
1027 eaa728ee bellard
                               DESC_S_MASK |
1028 eaa728ee bellard
                               DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK);
1029 eaa728ee bellard
        cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1030 eaa728ee bellard
                               0, 0xffffffff,
1031 eaa728ee bellard
                               DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1032 eaa728ee bellard
                               DESC_S_MASK |
1033 eaa728ee bellard
                               DESC_W_MASK | DESC_A_MASK);
1034 eaa728ee bellard
        env->eflags &= ~env->fmask;
1035 eaa728ee bellard
        load_eflags(env->eflags, 0);
1036 eaa728ee bellard
        if (code64)
1037 eaa728ee bellard
            env->eip = env->lstar;
1038 eaa728ee bellard
        else
1039 eaa728ee bellard
            env->eip = env->cstar;
1040 d9957a8b blueswir1
    } else {
1041 eaa728ee bellard
        ECX = (uint32_t)(env->eip + next_eip_addend);
1042 eaa728ee bellard
1043 eaa728ee bellard
        cpu_x86_set_cpl(env, 0);
1044 eaa728ee bellard
        cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1045 eaa728ee bellard
                           0, 0xffffffff,
1046 eaa728ee bellard
                               DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1047 eaa728ee bellard
                               DESC_S_MASK |
1048 eaa728ee bellard
                               DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1049 eaa728ee bellard
        cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1050 eaa728ee bellard
                               0, 0xffffffff,
1051 eaa728ee bellard
                               DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1052 eaa728ee bellard
                               DESC_S_MASK |
1053 eaa728ee bellard
                               DESC_W_MASK | DESC_A_MASK);
1054 eaa728ee bellard
        env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
1055 eaa728ee bellard
        env->eip = (uint32_t)env->star;
1056 eaa728ee bellard
    }
1057 eaa728ee bellard
}
1058 eaa728ee bellard
#endif
1059 d9957a8b blueswir1
#endif
1060 eaa728ee bellard
1061 d9957a8b blueswir1
#ifdef TARGET_X86_64
1062 eaa728ee bellard
void helper_sysret(int dflag)
1063 eaa728ee bellard
{
1064 eaa728ee bellard
    int cpl, selector;
1065 eaa728ee bellard
1066 eaa728ee bellard
    if (!(env->efer & MSR_EFER_SCE)) {
1067 eaa728ee bellard
        raise_exception_err(EXCP06_ILLOP, 0);
1068 eaa728ee bellard
    }
1069 eaa728ee bellard
    cpl = env->hflags & HF_CPL_MASK;
1070 eaa728ee bellard
    if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
1071 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, 0);
1072 eaa728ee bellard
    }
1073 eaa728ee bellard
    selector = (env->star >> 48) & 0xffff;
1074 eaa728ee bellard
    if (env->hflags & HF_LMA_MASK) {
1075 eaa728ee bellard
        if (dflag == 2) {
1076 eaa728ee bellard
            cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1077 eaa728ee bellard
                                   0, 0xffffffff,
1078 eaa728ee bellard
                                   DESC_G_MASK | DESC_P_MASK |
1079 eaa728ee bellard
                                   DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1080 eaa728ee bellard
                                   DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1081 eaa728ee bellard
                                   DESC_L_MASK);
1082 eaa728ee bellard
            env->eip = ECX;
1083 eaa728ee bellard
        } else {
1084 eaa728ee bellard
            cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1085 eaa728ee bellard
                                   0, 0xffffffff,
1086 eaa728ee bellard
                                   DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1087 eaa728ee bellard
                                   DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1088 eaa728ee bellard
                                   DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1089 eaa728ee bellard
            env->eip = (uint32_t)ECX;
1090 eaa728ee bellard
        }
1091 eaa728ee bellard
        cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1092 eaa728ee bellard
                               0, 0xffffffff,
1093 eaa728ee bellard
                               DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1094 eaa728ee bellard
                               DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1095 eaa728ee bellard
                               DESC_W_MASK | DESC_A_MASK);
1096 eaa728ee bellard
        load_eflags((uint32_t)(env->regs[11]), TF_MASK | AC_MASK | ID_MASK |
1097 eaa728ee bellard
                    IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK);
1098 eaa728ee bellard
        cpu_x86_set_cpl(env, 3);
1099 d9957a8b blueswir1
    } else {
1100 eaa728ee bellard
        cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1101 eaa728ee bellard
                               0, 0xffffffff,
1102 eaa728ee bellard
                               DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1103 eaa728ee bellard
                               DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1104 eaa728ee bellard
                               DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1105 eaa728ee bellard
        env->eip = (uint32_t)ECX;
1106 eaa728ee bellard
        cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1107 eaa728ee bellard
                               0, 0xffffffff,
1108 eaa728ee bellard
                               DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1109 eaa728ee bellard
                               DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1110 eaa728ee bellard
                               DESC_W_MASK | DESC_A_MASK);
1111 eaa728ee bellard
        env->eflags |= IF_MASK;
1112 eaa728ee bellard
        cpu_x86_set_cpl(env, 3);
1113 eaa728ee bellard
    }
1114 eaa728ee bellard
}
1115 d9957a8b blueswir1
#endif
1116 eaa728ee bellard
1117 eaa728ee bellard
/* real mode interrupt */
1118 eaa728ee bellard
static void do_interrupt_real(int intno, int is_int, int error_code,
1119 eaa728ee bellard
                              unsigned int next_eip)
1120 eaa728ee bellard
{
1121 eaa728ee bellard
    SegmentCache *dt;
1122 eaa728ee bellard
    target_ulong ptr, ssp;
1123 eaa728ee bellard
    int selector;
1124 eaa728ee bellard
    uint32_t offset, esp;
1125 eaa728ee bellard
    uint32_t old_cs, old_eip;
1126 eaa728ee bellard
1127 eaa728ee bellard
    /* real mode (simpler !) */
1128 eaa728ee bellard
    dt = &env->idt;
1129 eaa728ee bellard
    if (intno * 4 + 3 > dt->limit)
1130 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1131 eaa728ee bellard
    ptr = dt->base + intno * 4;
1132 eaa728ee bellard
    offset = lduw_kernel(ptr);
1133 eaa728ee bellard
    selector = lduw_kernel(ptr + 2);
1134 eaa728ee bellard
    esp = ESP;
1135 eaa728ee bellard
    ssp = env->segs[R_SS].base;
1136 eaa728ee bellard
    if (is_int)
1137 eaa728ee bellard
        old_eip = next_eip;
1138 eaa728ee bellard
    else
1139 eaa728ee bellard
        old_eip = env->eip;
1140 eaa728ee bellard
    old_cs = env->segs[R_CS].selector;
1141 eaa728ee bellard
    /* XXX: use SS segment size ? */
1142 eaa728ee bellard
    PUSHW(ssp, esp, 0xffff, compute_eflags());
1143 eaa728ee bellard
    PUSHW(ssp, esp, 0xffff, old_cs);
1144 eaa728ee bellard
    PUSHW(ssp, esp, 0xffff, old_eip);
1145 eaa728ee bellard
1146 eaa728ee bellard
    /* update processor state */
1147 eaa728ee bellard
    ESP = (ESP & ~0xffff) | (esp & 0xffff);
1148 eaa728ee bellard
    env->eip = offset;
1149 eaa728ee bellard
    env->segs[R_CS].selector = selector;
1150 eaa728ee bellard
    env->segs[R_CS].base = (selector << 4);
1151 eaa728ee bellard
    env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1152 eaa728ee bellard
}
1153 eaa728ee bellard
1154 eaa728ee bellard
/* fake user mode interrupt */
1155 eaa728ee bellard
void do_interrupt_user(int intno, int is_int, int error_code,
1156 eaa728ee bellard
                       target_ulong next_eip)
1157 eaa728ee bellard
{
1158 eaa728ee bellard
    SegmentCache *dt;
1159 eaa728ee bellard
    target_ulong ptr;
1160 eaa728ee bellard
    int dpl, cpl, shift;
1161 eaa728ee bellard
    uint32_t e2;
1162 eaa728ee bellard
1163 eaa728ee bellard
    dt = &env->idt;
1164 eaa728ee bellard
    if (env->hflags & HF_LMA_MASK) {
1165 eaa728ee bellard
        shift = 4;
1166 eaa728ee bellard
    } else {
1167 eaa728ee bellard
        shift = 3;
1168 eaa728ee bellard
    }
1169 eaa728ee bellard
    ptr = dt->base + (intno << shift);
1170 eaa728ee bellard
    e2 = ldl_kernel(ptr + 4);
1171 eaa728ee bellard
1172 eaa728ee bellard
    dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1173 eaa728ee bellard
    cpl = env->hflags & HF_CPL_MASK;
1174 1235fc06 ths
    /* check privilege if software int */
1175 eaa728ee bellard
    if (is_int && dpl < cpl)
1176 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, (intno << shift) + 2);
1177 eaa728ee bellard
1178 eaa728ee bellard
    /* Since we emulate only user space, we cannot do more than
1179 eaa728ee bellard
       exiting the emulation with the suitable exception and error
1180 eaa728ee bellard
       code */
1181 eaa728ee bellard
    if (is_int)
1182 eaa728ee bellard
        EIP = next_eip;
1183 eaa728ee bellard
}
1184 eaa728ee bellard
1185 00ea18d1 aliguori
#if !defined(CONFIG_USER_ONLY)
1186 2ed51f5b aliguori
static void handle_even_inj(int intno, int is_int, int error_code,
1187 2ed51f5b aliguori
                int is_hw, int rm)
1188 2ed51f5b aliguori
{
1189 2ed51f5b aliguori
    uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj));
1190 2ed51f5b aliguori
    if (!(event_inj & SVM_EVTINJ_VALID)) {
1191 2ed51f5b aliguori
            int type;
1192 2ed51f5b aliguori
            if (is_int)
1193 2ed51f5b aliguori
                    type = SVM_EVTINJ_TYPE_SOFT;
1194 2ed51f5b aliguori
            else
1195 2ed51f5b aliguori
                    type = SVM_EVTINJ_TYPE_EXEPT;
1196 2ed51f5b aliguori
            event_inj = intno | type | SVM_EVTINJ_VALID;
1197 2ed51f5b aliguori
            if (!rm && exeption_has_error_code(intno)) {
1198 2ed51f5b aliguori
                    event_inj |= SVM_EVTINJ_VALID_ERR;
1199 2ed51f5b aliguori
                    stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj_err), error_code);
1200 2ed51f5b aliguori
            }
1201 2ed51f5b aliguori
            stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), event_inj);
1202 2ed51f5b aliguori
    }
1203 2ed51f5b aliguori
}
1204 00ea18d1 aliguori
#endif
1205 2ed51f5b aliguori
1206 eaa728ee bellard
/*
1207 eaa728ee bellard
 * Begin execution of an interruption. is_int is TRUE if coming from
1208 eaa728ee bellard
 * the int instruction. next_eip is the EIP value AFTER the interrupt
1209 eaa728ee bellard
 * instruction. It is only relevant if is_int is TRUE.
1210 eaa728ee bellard
 */
1211 eaa728ee bellard
void do_interrupt(int intno, int is_int, int error_code,
1212 eaa728ee bellard
                  target_ulong next_eip, int is_hw)
1213 eaa728ee bellard
{
1214 8fec2b8c aliguori
    if (qemu_loglevel_mask(CPU_LOG_INT)) {
1215 eaa728ee bellard
        if ((env->cr[0] & CR0_PE_MASK)) {
1216 eaa728ee bellard
            static int count;
1217 93fcfe39 aliguori
            qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1218 eaa728ee bellard
                    count, intno, error_code, is_int,
1219 eaa728ee bellard
                    env->hflags & HF_CPL_MASK,
1220 eaa728ee bellard
                    env->segs[R_CS].selector, EIP,
1221 eaa728ee bellard
                    (int)env->segs[R_CS].base + EIP,
1222 eaa728ee bellard
                    env->segs[R_SS].selector, ESP);
1223 eaa728ee bellard
            if (intno == 0x0e) {
1224 93fcfe39 aliguori
                qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
1225 eaa728ee bellard
            } else {
1226 93fcfe39 aliguori
                qemu_log(" EAX=" TARGET_FMT_lx, EAX);
1227 eaa728ee bellard
            }
1228 93fcfe39 aliguori
            qemu_log("\n");
1229 93fcfe39 aliguori
            log_cpu_state(env, X86_DUMP_CCOP);
1230 eaa728ee bellard
#if 0
1231 eaa728ee bellard
            {
1232 eaa728ee bellard
                int i;
1233 eaa728ee bellard
                uint8_t *ptr;
1234 93fcfe39 aliguori
                qemu_log("       code=");
1235 eaa728ee bellard
                ptr = env->segs[R_CS].base + env->eip;
1236 eaa728ee bellard
                for(i = 0; i < 16; i++) {
1237 93fcfe39 aliguori
                    qemu_log(" %02x", ldub(ptr + i));
1238 eaa728ee bellard
                }
1239 93fcfe39 aliguori
                qemu_log("\n");
1240 eaa728ee bellard
            }
1241 eaa728ee bellard
#endif
1242 eaa728ee bellard
            count++;
1243 eaa728ee bellard
        }
1244 eaa728ee bellard
    }
1245 eaa728ee bellard
    if (env->cr[0] & CR0_PE_MASK) {
1246 00ea18d1 aliguori
#if !defined(CONFIG_USER_ONLY)
1247 2ed51f5b aliguori
        if (env->hflags & HF_SVMI_MASK)
1248 2ed51f5b aliguori
            handle_even_inj(intno, is_int, error_code, is_hw, 0);
1249 00ea18d1 aliguori
#endif
1250 eb38c52c blueswir1
#ifdef TARGET_X86_64
1251 eaa728ee bellard
        if (env->hflags & HF_LMA_MASK) {
1252 eaa728ee bellard
            do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1253 eaa728ee bellard
        } else
1254 eaa728ee bellard
#endif
1255 eaa728ee bellard
        {
1256 eaa728ee bellard
            do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1257 eaa728ee bellard
        }
1258 eaa728ee bellard
    } else {
1259 00ea18d1 aliguori
#if !defined(CONFIG_USER_ONLY)
1260 2ed51f5b aliguori
        if (env->hflags & HF_SVMI_MASK)
1261 2ed51f5b aliguori
            handle_even_inj(intno, is_int, error_code, is_hw, 1);
1262 00ea18d1 aliguori
#endif
1263 eaa728ee bellard
        do_interrupt_real(intno, is_int, error_code, next_eip);
1264 eaa728ee bellard
    }
1265 2ed51f5b aliguori
1266 00ea18d1 aliguori
#if !defined(CONFIG_USER_ONLY)
1267 2ed51f5b aliguori
    if (env->hflags & HF_SVMI_MASK) {
1268 2ed51f5b aliguori
            uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj));
1269 2ed51f5b aliguori
            stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), event_inj & ~SVM_EVTINJ_VALID);
1270 2ed51f5b aliguori
    }
1271 00ea18d1 aliguori
#endif
1272 eaa728ee bellard
}
1273 eaa728ee bellard
1274 f55761a0 aliguori
/* This should come from sysemu.h - if we could include it here... */
1275 f55761a0 aliguori
void qemu_system_reset_request(void);
1276 f55761a0 aliguori
1277 eaa728ee bellard
/*
1278 eaa728ee bellard
 * Check nested exceptions and change to double or triple fault if
1279 eaa728ee bellard
 * needed. It should only be called, if this is not an interrupt.
1280 eaa728ee bellard
 * Returns the new exception number.
1281 eaa728ee bellard
 */
1282 eaa728ee bellard
static int check_exception(int intno, int *error_code)
1283 eaa728ee bellard
{
1284 eaa728ee bellard
    int first_contributory = env->old_exception == 0 ||
1285 eaa728ee bellard
                              (env->old_exception >= 10 &&
1286 eaa728ee bellard
                               env->old_exception <= 13);
1287 eaa728ee bellard
    int second_contributory = intno == 0 ||
1288 eaa728ee bellard
                               (intno >= 10 && intno <= 13);
1289 eaa728ee bellard
1290 93fcfe39 aliguori
    qemu_log_mask(CPU_LOG_INT, "check_exception old: 0x%x new 0x%x\n",
1291 eaa728ee bellard
                env->old_exception, intno);
1292 eaa728ee bellard
1293 f55761a0 aliguori
#if !defined(CONFIG_USER_ONLY)
1294 f55761a0 aliguori
    if (env->old_exception == EXCP08_DBLE) {
1295 f55761a0 aliguori
        if (env->hflags & HF_SVMI_MASK)
1296 f55761a0 aliguori
            helper_vmexit(SVM_EXIT_SHUTDOWN, 0); /* does not return */
1297 f55761a0 aliguori
1298 680c3069 aliguori
        qemu_log_mask(CPU_LOG_RESET, "Triple fault\n");
1299 f55761a0 aliguori
1300 f55761a0 aliguori
        qemu_system_reset_request();
1301 f55761a0 aliguori
        return EXCP_HLT;
1302 f55761a0 aliguori
    }
1303 f55761a0 aliguori
#endif
1304 eaa728ee bellard
1305 eaa728ee bellard
    if ((first_contributory && second_contributory)
1306 eaa728ee bellard
        || (env->old_exception == EXCP0E_PAGE &&
1307 eaa728ee bellard
            (second_contributory || (intno == EXCP0E_PAGE)))) {
1308 eaa728ee bellard
        intno = EXCP08_DBLE;
1309 eaa728ee bellard
        *error_code = 0;
1310 eaa728ee bellard
    }
1311 eaa728ee bellard
1312 eaa728ee bellard
    if (second_contributory || (intno == EXCP0E_PAGE) ||
1313 eaa728ee bellard
        (intno == EXCP08_DBLE))
1314 eaa728ee bellard
        env->old_exception = intno;
1315 eaa728ee bellard
1316 eaa728ee bellard
    return intno;
1317 eaa728ee bellard
}
1318 eaa728ee bellard
1319 eaa728ee bellard
/*
1320 eaa728ee bellard
 * Signal an interruption. It is executed in the main CPU loop.
1321 eaa728ee bellard
 * is_int is TRUE if coming from the int instruction. next_eip is the
1322 eaa728ee bellard
 * EIP value AFTER the interrupt instruction. It is only relevant if
1323 eaa728ee bellard
 * is_int is TRUE.
1324 eaa728ee bellard
 */
1325 a5e50b26 malc
static void QEMU_NORETURN raise_interrupt(int intno, int is_int, int error_code,
1326 a5e50b26 malc
                                          int next_eip_addend)
1327 eaa728ee bellard
{
1328 eaa728ee bellard
    if (!is_int) {
1329 eaa728ee bellard
        helper_svm_check_intercept_param(SVM_EXIT_EXCP_BASE + intno, error_code);
1330 eaa728ee bellard
        intno = check_exception(intno, &error_code);
1331 872929aa bellard
    } else {
1332 872929aa bellard
        helper_svm_check_intercept_param(SVM_EXIT_SWINT, 0);
1333 eaa728ee bellard
    }
1334 eaa728ee bellard
1335 eaa728ee bellard
    env->exception_index = intno;
1336 eaa728ee bellard
    env->error_code = error_code;
1337 eaa728ee bellard
    env->exception_is_int = is_int;
1338 eaa728ee bellard
    env->exception_next_eip = env->eip + next_eip_addend;
1339 eaa728ee bellard
    cpu_loop_exit();
1340 eaa728ee bellard
}
1341 eaa728ee bellard
1342 eaa728ee bellard
/* shortcuts to generate exceptions */
1343 eaa728ee bellard
1344 d9957a8b blueswir1
void raise_exception_err(int exception_index, int error_code)
1345 eaa728ee bellard
{
1346 eaa728ee bellard
    raise_interrupt(exception_index, 0, error_code, 0);
1347 eaa728ee bellard
}
1348 eaa728ee bellard
1349 eaa728ee bellard
void raise_exception(int exception_index)
1350 eaa728ee bellard
{
1351 eaa728ee bellard
    raise_interrupt(exception_index, 0, 0, 0);
1352 eaa728ee bellard
}
1353 eaa728ee bellard
1354 eaa728ee bellard
/* SMM support */
1355 eaa728ee bellard
1356 eaa728ee bellard
#if defined(CONFIG_USER_ONLY)
1357 eaa728ee bellard
1358 eaa728ee bellard
void do_smm_enter(void)
1359 eaa728ee bellard
{
1360 eaa728ee bellard
}
1361 eaa728ee bellard
1362 eaa728ee bellard
void helper_rsm(void)
1363 eaa728ee bellard
{
1364 eaa728ee bellard
}
1365 eaa728ee bellard
1366 eaa728ee bellard
#else
1367 eaa728ee bellard
1368 eaa728ee bellard
#ifdef TARGET_X86_64
1369 eaa728ee bellard
#define SMM_REVISION_ID 0x00020064
1370 eaa728ee bellard
#else
1371 eaa728ee bellard
#define SMM_REVISION_ID 0x00020000
1372 eaa728ee bellard
#endif
1373 eaa728ee bellard
1374 eaa728ee bellard
void do_smm_enter(void)
1375 eaa728ee bellard
{
1376 eaa728ee bellard
    target_ulong sm_state;
1377 eaa728ee bellard
    SegmentCache *dt;
1378 eaa728ee bellard
    int i, offset;
1379 eaa728ee bellard
1380 93fcfe39 aliguori
    qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
1381 93fcfe39 aliguori
    log_cpu_state_mask(CPU_LOG_INT, env, X86_DUMP_CCOP);
1382 eaa728ee bellard
1383 eaa728ee bellard
    env->hflags |= HF_SMM_MASK;
1384 eaa728ee bellard
    cpu_smm_update(env);
1385 eaa728ee bellard
1386 eaa728ee bellard
    sm_state = env->smbase + 0x8000;
1387 eaa728ee bellard
1388 eaa728ee bellard
#ifdef TARGET_X86_64
1389 eaa728ee bellard
    for(i = 0; i < 6; i++) {
1390 eaa728ee bellard
        dt = &env->segs[i];
1391 eaa728ee bellard
        offset = 0x7e00 + i * 16;
1392 eaa728ee bellard
        stw_phys(sm_state + offset, dt->selector);
1393 eaa728ee bellard
        stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
1394 eaa728ee bellard
        stl_phys(sm_state + offset + 4, dt->limit);
1395 eaa728ee bellard
        stq_phys(sm_state + offset + 8, dt->base);
1396 eaa728ee bellard
    }
1397 eaa728ee bellard
1398 eaa728ee bellard
    stq_phys(sm_state + 0x7e68, env->gdt.base);
1399 eaa728ee bellard
    stl_phys(sm_state + 0x7e64, env->gdt.limit);
1400 eaa728ee bellard
1401 eaa728ee bellard
    stw_phys(sm_state + 0x7e70, env->ldt.selector);
1402 eaa728ee bellard
    stq_phys(sm_state + 0x7e78, env->ldt.base);
1403 eaa728ee bellard
    stl_phys(sm_state + 0x7e74, env->ldt.limit);
1404 eaa728ee bellard
    stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
1405 eaa728ee bellard
1406 eaa728ee bellard
    stq_phys(sm_state + 0x7e88, env->idt.base);
1407 eaa728ee bellard
    stl_phys(sm_state + 0x7e84, env->idt.limit);
1408 eaa728ee bellard
1409 eaa728ee bellard
    stw_phys(sm_state + 0x7e90, env->tr.selector);
1410 eaa728ee bellard
    stq_phys(sm_state + 0x7e98, env->tr.base);
1411 eaa728ee bellard
    stl_phys(sm_state + 0x7e94, env->tr.limit);
1412 eaa728ee bellard
    stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
1413 eaa728ee bellard
1414 eaa728ee bellard
    stq_phys(sm_state + 0x7ed0, env->efer);
1415 eaa728ee bellard
1416 eaa728ee bellard
    stq_phys(sm_state + 0x7ff8, EAX);
1417 eaa728ee bellard
    stq_phys(sm_state + 0x7ff0, ECX);
1418 eaa728ee bellard
    stq_phys(sm_state + 0x7fe8, EDX);
1419 eaa728ee bellard
    stq_phys(sm_state + 0x7fe0, EBX);
1420 eaa728ee bellard
    stq_phys(sm_state + 0x7fd8, ESP);
1421 eaa728ee bellard
    stq_phys(sm_state + 0x7fd0, EBP);
1422 eaa728ee bellard
    stq_phys(sm_state + 0x7fc8, ESI);
1423 eaa728ee bellard
    stq_phys(sm_state + 0x7fc0, EDI);
1424 eaa728ee bellard
    for(i = 8; i < 16; i++)
1425 eaa728ee bellard
        stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
1426 eaa728ee bellard
    stq_phys(sm_state + 0x7f78, env->eip);
1427 eaa728ee bellard
    stl_phys(sm_state + 0x7f70, compute_eflags());
1428 eaa728ee bellard
    stl_phys(sm_state + 0x7f68, env->dr[6]);
1429 eaa728ee bellard
    stl_phys(sm_state + 0x7f60, env->dr[7]);
1430 eaa728ee bellard
1431 eaa728ee bellard
    stl_phys(sm_state + 0x7f48, env->cr[4]);
1432 eaa728ee bellard
    stl_phys(sm_state + 0x7f50, env->cr[3]);
1433 eaa728ee bellard
    stl_phys(sm_state + 0x7f58, env->cr[0]);
1434 eaa728ee bellard
1435 eaa728ee bellard
    stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1436 eaa728ee bellard
    stl_phys(sm_state + 0x7f00, env->smbase);
1437 eaa728ee bellard
#else
1438 eaa728ee bellard
    stl_phys(sm_state + 0x7ffc, env->cr[0]);
1439 eaa728ee bellard
    stl_phys(sm_state + 0x7ff8, env->cr[3]);
1440 eaa728ee bellard
    stl_phys(sm_state + 0x7ff4, compute_eflags());
1441 eaa728ee bellard
    stl_phys(sm_state + 0x7ff0, env->eip);
1442 eaa728ee bellard
    stl_phys(sm_state + 0x7fec, EDI);
1443 eaa728ee bellard
    stl_phys(sm_state + 0x7fe8, ESI);
1444 eaa728ee bellard
    stl_phys(sm_state + 0x7fe4, EBP);
1445 eaa728ee bellard
    stl_phys(sm_state + 0x7fe0, ESP);
1446 eaa728ee bellard
    stl_phys(sm_state + 0x7fdc, EBX);
1447 eaa728ee bellard
    stl_phys(sm_state + 0x7fd8, EDX);
1448 eaa728ee bellard
    stl_phys(sm_state + 0x7fd4, ECX);
1449 eaa728ee bellard
    stl_phys(sm_state + 0x7fd0, EAX);
1450 eaa728ee bellard
    stl_phys(sm_state + 0x7fcc, env->dr[6]);
1451 eaa728ee bellard
    stl_phys(sm_state + 0x7fc8, env->dr[7]);
1452 eaa728ee bellard
1453 eaa728ee bellard
    stl_phys(sm_state + 0x7fc4, env->tr.selector);
1454 eaa728ee bellard
    stl_phys(sm_state + 0x7f64, env->tr.base);
1455 eaa728ee bellard
    stl_phys(sm_state + 0x7f60, env->tr.limit);
1456 eaa728ee bellard
    stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
1457 eaa728ee bellard
1458 eaa728ee bellard
    stl_phys(sm_state + 0x7fc0, env->ldt.selector);
1459 eaa728ee bellard
    stl_phys(sm_state + 0x7f80, env->ldt.base);
1460 eaa728ee bellard
    stl_phys(sm_state + 0x7f7c, env->ldt.limit);
1461 eaa728ee bellard
    stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
1462 eaa728ee bellard
1463 eaa728ee bellard
    stl_phys(sm_state + 0x7f74, env->gdt.base);
1464 eaa728ee bellard
    stl_phys(sm_state + 0x7f70, env->gdt.limit);
1465 eaa728ee bellard
1466 eaa728ee bellard
    stl_phys(sm_state + 0x7f58, env->idt.base);
1467 eaa728ee bellard
    stl_phys(sm_state + 0x7f54, env->idt.limit);
1468 eaa728ee bellard
1469 eaa728ee bellard
    for(i = 0; i < 6; i++) {
1470 eaa728ee bellard
        dt = &env->segs[i];
1471 eaa728ee bellard
        if (i < 3)
1472 eaa728ee bellard
            offset = 0x7f84 + i * 12;
1473 eaa728ee bellard
        else
1474 eaa728ee bellard
            offset = 0x7f2c + (i - 3) * 12;
1475 eaa728ee bellard
        stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
1476 eaa728ee bellard
        stl_phys(sm_state + offset + 8, dt->base);
1477 eaa728ee bellard
        stl_phys(sm_state + offset + 4, dt->limit);
1478 eaa728ee bellard
        stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
1479 eaa728ee bellard
    }
1480 eaa728ee bellard
    stl_phys(sm_state + 0x7f14, env->cr[4]);
1481 eaa728ee bellard
1482 eaa728ee bellard
    stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1483 eaa728ee bellard
    stl_phys(sm_state + 0x7ef8, env->smbase);
1484 eaa728ee bellard
#endif
1485 eaa728ee bellard
    /* init SMM cpu state */
1486 eaa728ee bellard
1487 eaa728ee bellard
#ifdef TARGET_X86_64
1488 5efc27bb bellard
    cpu_load_efer(env, 0);
1489 eaa728ee bellard
#endif
1490 eaa728ee bellard
    load_eflags(0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
1491 eaa728ee bellard
    env->eip = 0x00008000;
1492 eaa728ee bellard
    cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
1493 eaa728ee bellard
                           0xffffffff, 0);
1494 eaa728ee bellard
    cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
1495 eaa728ee bellard
    cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
1496 eaa728ee bellard
    cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
1497 eaa728ee bellard
    cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
1498 eaa728ee bellard
    cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
1499 eaa728ee bellard
1500 eaa728ee bellard
    cpu_x86_update_cr0(env,
1501 eaa728ee bellard
                       env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK | CR0_PG_MASK));
1502 eaa728ee bellard
    cpu_x86_update_cr4(env, 0);
1503 eaa728ee bellard
    env->dr[7] = 0x00000400;
1504 eaa728ee bellard
    CC_OP = CC_OP_EFLAGS;
1505 eaa728ee bellard
}
1506 eaa728ee bellard
1507 eaa728ee bellard
void helper_rsm(void)
1508 eaa728ee bellard
{
1509 eaa728ee bellard
    target_ulong sm_state;
1510 eaa728ee bellard
    int i, offset;
1511 eaa728ee bellard
    uint32_t val;
1512 eaa728ee bellard
1513 eaa728ee bellard
    sm_state = env->smbase + 0x8000;
1514 eaa728ee bellard
#ifdef TARGET_X86_64
1515 5efc27bb bellard
    cpu_load_efer(env, ldq_phys(sm_state + 0x7ed0));
1516 eaa728ee bellard
1517 eaa728ee bellard
    for(i = 0; i < 6; i++) {
1518 eaa728ee bellard
        offset = 0x7e00 + i * 16;
1519 eaa728ee bellard
        cpu_x86_load_seg_cache(env, i,
1520 eaa728ee bellard
                               lduw_phys(sm_state + offset),
1521 eaa728ee bellard
                               ldq_phys(sm_state + offset + 8),
1522 eaa728ee bellard
                               ldl_phys(sm_state + offset + 4),
1523 eaa728ee bellard
                               (lduw_phys(sm_state + offset + 2) & 0xf0ff) << 8);
1524 eaa728ee bellard
    }
1525 eaa728ee bellard
1526 eaa728ee bellard
    env->gdt.base = ldq_phys(sm_state + 0x7e68);
1527 eaa728ee bellard
    env->gdt.limit = ldl_phys(sm_state + 0x7e64);
1528 eaa728ee bellard
1529 eaa728ee bellard
    env->ldt.selector = lduw_phys(sm_state + 0x7e70);
1530 eaa728ee bellard
    env->ldt.base = ldq_phys(sm_state + 0x7e78);
1531 eaa728ee bellard
    env->ldt.limit = ldl_phys(sm_state + 0x7e74);
1532 eaa728ee bellard
    env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
1533 eaa728ee bellard
1534 eaa728ee bellard
    env->idt.base = ldq_phys(sm_state + 0x7e88);
1535 eaa728ee bellard
    env->idt.limit = ldl_phys(sm_state + 0x7e84);
1536 eaa728ee bellard
1537 eaa728ee bellard
    env->tr.selector = lduw_phys(sm_state + 0x7e90);
1538 eaa728ee bellard
    env->tr.base = ldq_phys(sm_state + 0x7e98);
1539 eaa728ee bellard
    env->tr.limit = ldl_phys(sm_state + 0x7e94);
1540 eaa728ee bellard
    env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
1541 eaa728ee bellard
1542 eaa728ee bellard
    EAX = ldq_phys(sm_state + 0x7ff8);
1543 eaa728ee bellard
    ECX = ldq_phys(sm_state + 0x7ff0);
1544 eaa728ee bellard
    EDX = ldq_phys(sm_state + 0x7fe8);
1545 eaa728ee bellard
    EBX = ldq_phys(sm_state + 0x7fe0);
1546 eaa728ee bellard
    ESP = ldq_phys(sm_state + 0x7fd8);
1547 eaa728ee bellard
    EBP = ldq_phys(sm_state + 0x7fd0);
1548 eaa728ee bellard
    ESI = ldq_phys(sm_state + 0x7fc8);
1549 eaa728ee bellard
    EDI = ldq_phys(sm_state + 0x7fc0);
1550 eaa728ee bellard
    for(i = 8; i < 16; i++)
1551 eaa728ee bellard
        env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
1552 eaa728ee bellard
    env->eip = ldq_phys(sm_state + 0x7f78);
1553 eaa728ee bellard
    load_eflags(ldl_phys(sm_state + 0x7f70),
1554 eaa728ee bellard
                ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
1555 eaa728ee bellard
    env->dr[6] = ldl_phys(sm_state + 0x7f68);
1556 eaa728ee bellard
    env->dr[7] = ldl_phys(sm_state + 0x7f60);
1557 eaa728ee bellard
1558 eaa728ee bellard
    cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
1559 eaa728ee bellard
    cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
1560 eaa728ee bellard
    cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
1561 eaa728ee bellard
1562 eaa728ee bellard
    val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1563 eaa728ee bellard
    if (val & 0x20000) {
1564 eaa728ee bellard
        env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
1565 eaa728ee bellard
    }
1566 eaa728ee bellard
#else
1567 eaa728ee bellard
    cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
1568 eaa728ee bellard
    cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
1569 eaa728ee bellard
    load_eflags(ldl_phys(sm_state + 0x7ff4),
1570 eaa728ee bellard
                ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
1571 eaa728ee bellard
    env->eip = ldl_phys(sm_state + 0x7ff0);
1572 eaa728ee bellard
    EDI = ldl_phys(sm_state + 0x7fec);
1573 eaa728ee bellard
    ESI = ldl_phys(sm_state + 0x7fe8);
1574 eaa728ee bellard
    EBP = ldl_phys(sm_state + 0x7fe4);
1575 eaa728ee bellard
    ESP = ldl_phys(sm_state + 0x7fe0);
1576 eaa728ee bellard
    EBX = ldl_phys(sm_state + 0x7fdc);
1577 eaa728ee bellard
    EDX = ldl_phys(sm_state + 0x7fd8);
1578 eaa728ee bellard
    ECX = ldl_phys(sm_state + 0x7fd4);
1579 eaa728ee bellard
    EAX = ldl_phys(sm_state + 0x7fd0);
1580 eaa728ee bellard
    env->dr[6] = ldl_phys(sm_state + 0x7fcc);
1581 eaa728ee bellard
    env->dr[7] = ldl_phys(sm_state + 0x7fc8);
1582 eaa728ee bellard
1583 eaa728ee bellard
    env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
1584 eaa728ee bellard
    env->tr.base = ldl_phys(sm_state + 0x7f64);
1585 eaa728ee bellard
    env->tr.limit = ldl_phys(sm_state + 0x7f60);
1586 eaa728ee bellard
    env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
1587 eaa728ee bellard
1588 eaa728ee bellard
    env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
1589 eaa728ee bellard
    env->ldt.base = ldl_phys(sm_state + 0x7f80);
1590 eaa728ee bellard
    env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
1591 eaa728ee bellard
    env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
1592 eaa728ee bellard
1593 eaa728ee bellard
    env->gdt.base = ldl_phys(sm_state + 0x7f74);
1594 eaa728ee bellard
    env->gdt.limit = ldl_phys(sm_state + 0x7f70);
1595 eaa728ee bellard
1596 eaa728ee bellard
    env->idt.base = ldl_phys(sm_state + 0x7f58);
1597 eaa728ee bellard
    env->idt.limit = ldl_phys(sm_state + 0x7f54);
1598 eaa728ee bellard
1599 eaa728ee bellard
    for(i = 0; i < 6; i++) {
1600 eaa728ee bellard
        if (i < 3)
1601 eaa728ee bellard
            offset = 0x7f84 + i * 12;
1602 eaa728ee bellard
        else
1603 eaa728ee bellard
            offset = 0x7f2c + (i - 3) * 12;
1604 eaa728ee bellard
        cpu_x86_load_seg_cache(env, i,
1605 eaa728ee bellard
                               ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
1606 eaa728ee bellard
                               ldl_phys(sm_state + offset + 8),
1607 eaa728ee bellard
                               ldl_phys(sm_state + offset + 4),
1608 eaa728ee bellard
                               (ldl_phys(sm_state + offset) & 0xf0ff) << 8);
1609 eaa728ee bellard
    }
1610 eaa728ee bellard
    cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
1611 eaa728ee bellard
1612 eaa728ee bellard
    val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1613 eaa728ee bellard
    if (val & 0x20000) {
1614 eaa728ee bellard
        env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
1615 eaa728ee bellard
    }
1616 eaa728ee bellard
#endif
1617 eaa728ee bellard
    CC_OP = CC_OP_EFLAGS;
1618 eaa728ee bellard
    env->hflags &= ~HF_SMM_MASK;
1619 eaa728ee bellard
    cpu_smm_update(env);
1620 eaa728ee bellard
1621 93fcfe39 aliguori
    qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
1622 93fcfe39 aliguori
    log_cpu_state_mask(CPU_LOG_INT, env, X86_DUMP_CCOP);
1623 eaa728ee bellard
}
1624 eaa728ee bellard
1625 eaa728ee bellard
#endif /* !CONFIG_USER_ONLY */
1626 eaa728ee bellard
1627 eaa728ee bellard
1628 eaa728ee bellard
/* division, flags are undefined */
1629 eaa728ee bellard
1630 eaa728ee bellard
void helper_divb_AL(target_ulong t0)
1631 eaa728ee bellard
{
1632 eaa728ee bellard
    unsigned int num, den, q, r;
1633 eaa728ee bellard
1634 eaa728ee bellard
    num = (EAX & 0xffff);
1635 eaa728ee bellard
    den = (t0 & 0xff);
1636 eaa728ee bellard
    if (den == 0) {
1637 eaa728ee bellard
        raise_exception(EXCP00_DIVZ);
1638 eaa728ee bellard
    }
1639 eaa728ee bellard
    q = (num / den);
1640 eaa728ee bellard
    if (q > 0xff)
1641 eaa728ee bellard
        raise_exception(EXCP00_DIVZ);
1642 eaa728ee bellard
    q &= 0xff;
1643 eaa728ee bellard
    r = (num % den) & 0xff;
1644 eaa728ee bellard
    EAX = (EAX & ~0xffff) | (r << 8) | q;
1645 eaa728ee bellard
}
1646 eaa728ee bellard
1647 eaa728ee bellard
void helper_idivb_AL(target_ulong t0)
1648 eaa728ee bellard
{
1649 eaa728ee bellard
    int num, den, q, r;
1650 eaa728ee bellard
1651 eaa728ee bellard
    num = (int16_t)EAX;
1652 eaa728ee bellard
    den = (int8_t)t0;
1653 eaa728ee bellard
    if (den == 0) {
1654 eaa728ee bellard
        raise_exception(EXCP00_DIVZ);
1655 eaa728ee bellard
    }
1656 eaa728ee bellard
    q = (num / den);
1657 eaa728ee bellard
    if (q != (int8_t)q)
1658 eaa728ee bellard
        raise_exception(EXCP00_DIVZ);
1659 eaa728ee bellard
    q &= 0xff;
1660 eaa728ee bellard
    r = (num % den) & 0xff;
1661 eaa728ee bellard
    EAX = (EAX & ~0xffff) | (r << 8) | q;
1662 eaa728ee bellard
}
1663 eaa728ee bellard
1664 eaa728ee bellard
void helper_divw_AX(target_ulong t0)
1665 eaa728ee bellard
{
1666 eaa728ee bellard
    unsigned int num, den, q, r;
1667 eaa728ee bellard
1668 eaa728ee bellard
    num = (EAX & 0xffff) | ((EDX & 0xffff) << 16);
1669 eaa728ee bellard
    den = (t0 & 0xffff);
1670 eaa728ee bellard
    if (den == 0) {
1671 eaa728ee bellard
        raise_exception(EXCP00_DIVZ);
1672 eaa728ee bellard
    }
1673 eaa728ee bellard
    q = (num / den);
1674 eaa728ee bellard
    if (q > 0xffff)
1675 eaa728ee bellard
        raise_exception(EXCP00_DIVZ);
1676 eaa728ee bellard
    q &= 0xffff;
1677 eaa728ee bellard
    r = (num % den) & 0xffff;
1678 eaa728ee bellard
    EAX = (EAX & ~0xffff) | q;
1679 eaa728ee bellard
    EDX = (EDX & ~0xffff) | r;
1680 eaa728ee bellard
}
1681 eaa728ee bellard
1682 eaa728ee bellard
void helper_idivw_AX(target_ulong t0)
1683 eaa728ee bellard
{
1684 eaa728ee bellard
    int num, den, q, r;
1685 eaa728ee bellard
1686 eaa728ee bellard
    num = (EAX & 0xffff) | ((EDX & 0xffff) << 16);
1687 eaa728ee bellard
    den = (int16_t)t0;
1688 eaa728ee bellard
    if (den == 0) {
1689 eaa728ee bellard
        raise_exception(EXCP00_DIVZ);
1690 eaa728ee bellard
    }
1691 eaa728ee bellard
    q = (num / den);
1692 eaa728ee bellard
    if (q != (int16_t)q)
1693 eaa728ee bellard
        raise_exception(EXCP00_DIVZ);
1694 eaa728ee bellard
    q &= 0xffff;
1695 eaa728ee bellard
    r = (num % den) & 0xffff;
1696 eaa728ee bellard
    EAX = (EAX & ~0xffff) | q;
1697 eaa728ee bellard
    EDX = (EDX & ~0xffff) | r;
1698 eaa728ee bellard
}
1699 eaa728ee bellard
1700 eaa728ee bellard
void helper_divl_EAX(target_ulong t0)
1701 eaa728ee bellard
{
1702 eaa728ee bellard
    unsigned int den, r;
1703 eaa728ee bellard
    uint64_t num, q;
1704 eaa728ee bellard
1705 eaa728ee bellard
    num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
1706 eaa728ee bellard
    den = t0;
1707 eaa728ee bellard
    if (den == 0) {
1708 eaa728ee bellard
        raise_exception(EXCP00_DIVZ);
1709 eaa728ee bellard
    }
1710 eaa728ee bellard
    q = (num / den);
1711 eaa728ee bellard
    r = (num % den);
1712 eaa728ee bellard
    if (q > 0xffffffff)
1713 eaa728ee bellard
        raise_exception(EXCP00_DIVZ);
1714 eaa728ee bellard
    EAX = (uint32_t)q;
1715 eaa728ee bellard
    EDX = (uint32_t)r;
1716 eaa728ee bellard
}
1717 eaa728ee bellard
1718 eaa728ee bellard
void helper_idivl_EAX(target_ulong t0)
1719 eaa728ee bellard
{
1720 eaa728ee bellard
    int den, r;
1721 eaa728ee bellard
    int64_t num, q;
1722 eaa728ee bellard
1723 eaa728ee bellard
    num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
1724 eaa728ee bellard
    den = t0;
1725 eaa728ee bellard
    if (den == 0) {
1726 eaa728ee bellard
        raise_exception(EXCP00_DIVZ);
1727 eaa728ee bellard
    }
1728 eaa728ee bellard
    q = (num / den);
1729 eaa728ee bellard
    r = (num % den);
1730 eaa728ee bellard
    if (q != (int32_t)q)
1731 eaa728ee bellard
        raise_exception(EXCP00_DIVZ);
1732 eaa728ee bellard
    EAX = (uint32_t)q;
1733 eaa728ee bellard
    EDX = (uint32_t)r;
1734 eaa728ee bellard
}
1735 eaa728ee bellard
1736 eaa728ee bellard
/* bcd */
1737 eaa728ee bellard
1738 eaa728ee bellard
/* XXX: exception */
1739 eaa728ee bellard
void helper_aam(int base)
1740 eaa728ee bellard
{
1741 eaa728ee bellard
    int al, ah;
1742 eaa728ee bellard
    al = EAX & 0xff;
1743 eaa728ee bellard
    ah = al / base;
1744 eaa728ee bellard
    al = al % base;
1745 eaa728ee bellard
    EAX = (EAX & ~0xffff) | al | (ah << 8);
1746 eaa728ee bellard
    CC_DST = al;
1747 eaa728ee bellard
}
1748 eaa728ee bellard
1749 eaa728ee bellard
void helper_aad(int base)
1750 eaa728ee bellard
{
1751 eaa728ee bellard
    int al, ah;
1752 eaa728ee bellard
    al = EAX & 0xff;
1753 eaa728ee bellard
    ah = (EAX >> 8) & 0xff;
1754 eaa728ee bellard
    al = ((ah * base) + al) & 0xff;
1755 eaa728ee bellard
    EAX = (EAX & ~0xffff) | al;
1756 eaa728ee bellard
    CC_DST = al;
1757 eaa728ee bellard
}
1758 eaa728ee bellard
1759 eaa728ee bellard
void helper_aaa(void)
1760 eaa728ee bellard
{
1761 eaa728ee bellard
    int icarry;
1762 eaa728ee bellard
    int al, ah, af;
1763 eaa728ee bellard
    int eflags;
1764 eaa728ee bellard
1765 a7812ae4 pbrook
    eflags = helper_cc_compute_all(CC_OP);
1766 eaa728ee bellard
    af = eflags & CC_A;
1767 eaa728ee bellard
    al = EAX & 0xff;
1768 eaa728ee bellard
    ah = (EAX >> 8) & 0xff;
1769 eaa728ee bellard
1770 eaa728ee bellard
    icarry = (al > 0xf9);
1771 eaa728ee bellard
    if (((al & 0x0f) > 9 ) || af) {
1772 eaa728ee bellard
        al = (al + 6) & 0x0f;
1773 eaa728ee bellard
        ah = (ah + 1 + icarry) & 0xff;
1774 eaa728ee bellard
        eflags |= CC_C | CC_A;
1775 eaa728ee bellard
    } else {
1776 eaa728ee bellard
        eflags &= ~(CC_C | CC_A);
1777 eaa728ee bellard
        al &= 0x0f;
1778 eaa728ee bellard
    }
1779 eaa728ee bellard
    EAX = (EAX & ~0xffff) | al | (ah << 8);
1780 eaa728ee bellard
    CC_SRC = eflags;
1781 eaa728ee bellard
}
1782 eaa728ee bellard
1783 eaa728ee bellard
void helper_aas(void)
1784 eaa728ee bellard
{
1785 eaa728ee bellard
    int icarry;
1786 eaa728ee bellard
    int al, ah, af;
1787 eaa728ee bellard
    int eflags;
1788 eaa728ee bellard
1789 a7812ae4 pbrook
    eflags = helper_cc_compute_all(CC_OP);
1790 eaa728ee bellard
    af = eflags & CC_A;
1791 eaa728ee bellard
    al = EAX & 0xff;
1792 eaa728ee bellard
    ah = (EAX >> 8) & 0xff;
1793 eaa728ee bellard
1794 eaa728ee bellard
    icarry = (al < 6);
1795 eaa728ee bellard
    if (((al & 0x0f) > 9 ) || af) {
1796 eaa728ee bellard
        al = (al - 6) & 0x0f;
1797 eaa728ee bellard
        ah = (ah - 1 - icarry) & 0xff;
1798 eaa728ee bellard
        eflags |= CC_C | CC_A;
1799 eaa728ee bellard
    } else {
1800 eaa728ee bellard
        eflags &= ~(CC_C | CC_A);
1801 eaa728ee bellard
        al &= 0x0f;
1802 eaa728ee bellard
    }
1803 eaa728ee bellard
    EAX = (EAX & ~0xffff) | al | (ah << 8);
1804 eaa728ee bellard
    CC_SRC = eflags;
1805 eaa728ee bellard
}
1806 eaa728ee bellard
1807 eaa728ee bellard
void helper_daa(void)
1808 eaa728ee bellard
{
1809 eaa728ee bellard
    int al, af, cf;
1810 eaa728ee bellard
    int eflags;
1811 eaa728ee bellard
1812 a7812ae4 pbrook
    eflags = helper_cc_compute_all(CC_OP);
1813 eaa728ee bellard
    cf = eflags & CC_C;
1814 eaa728ee bellard
    af = eflags & CC_A;
1815 eaa728ee bellard
    al = EAX & 0xff;
1816 eaa728ee bellard
1817 eaa728ee bellard
    eflags = 0;
1818 eaa728ee bellard
    if (((al & 0x0f) > 9 ) || af) {
1819 eaa728ee bellard
        al = (al + 6) & 0xff;
1820 eaa728ee bellard
        eflags |= CC_A;
1821 eaa728ee bellard
    }
1822 eaa728ee bellard
    if ((al > 0x9f) || cf) {
1823 eaa728ee bellard
        al = (al + 0x60) & 0xff;
1824 eaa728ee bellard
        eflags |= CC_C;
1825 eaa728ee bellard
    }
1826 eaa728ee bellard
    EAX = (EAX & ~0xff) | al;
1827 eaa728ee bellard
    /* well, speed is not an issue here, so we compute the flags by hand */
1828 eaa728ee bellard
    eflags |= (al == 0) << 6; /* zf */
1829 eaa728ee bellard
    eflags |= parity_table[al]; /* pf */
1830 eaa728ee bellard
    eflags |= (al & 0x80); /* sf */
1831 eaa728ee bellard
    CC_SRC = eflags;
1832 eaa728ee bellard
}
1833 eaa728ee bellard
1834 eaa728ee bellard
void helper_das(void)
1835 eaa728ee bellard
{
1836 eaa728ee bellard
    int al, al1, af, cf;
1837 eaa728ee bellard
    int eflags;
1838 eaa728ee bellard
1839 a7812ae4 pbrook
    eflags = helper_cc_compute_all(CC_OP);
1840 eaa728ee bellard
    cf = eflags & CC_C;
1841 eaa728ee bellard
    af = eflags & CC_A;
1842 eaa728ee bellard
    al = EAX & 0xff;
1843 eaa728ee bellard
1844 eaa728ee bellard
    eflags = 0;
1845 eaa728ee bellard
    al1 = al;
1846 eaa728ee bellard
    if (((al & 0x0f) > 9 ) || af) {
1847 eaa728ee bellard
        eflags |= CC_A;
1848 eaa728ee bellard
        if (al < 6 || cf)
1849 eaa728ee bellard
            eflags |= CC_C;
1850 eaa728ee bellard
        al = (al - 6) & 0xff;
1851 eaa728ee bellard
    }
1852 eaa728ee bellard
    if ((al1 > 0x99) || cf) {
1853 eaa728ee bellard
        al = (al - 0x60) & 0xff;
1854 eaa728ee bellard
        eflags |= CC_C;
1855 eaa728ee bellard
    }
1856 eaa728ee bellard
    EAX = (EAX & ~0xff) | al;
1857 eaa728ee bellard
    /* well, speed is not an issue here, so we compute the flags by hand */
1858 eaa728ee bellard
    eflags |= (al == 0) << 6; /* zf */
1859 eaa728ee bellard
    eflags |= parity_table[al]; /* pf */
1860 eaa728ee bellard
    eflags |= (al & 0x80); /* sf */
1861 eaa728ee bellard
    CC_SRC = eflags;
1862 eaa728ee bellard
}
1863 eaa728ee bellard
1864 eaa728ee bellard
void helper_into(int next_eip_addend)
1865 eaa728ee bellard
{
1866 eaa728ee bellard
    int eflags;
1867 a7812ae4 pbrook
    eflags = helper_cc_compute_all(CC_OP);
1868 eaa728ee bellard
    if (eflags & CC_O) {
1869 eaa728ee bellard
        raise_interrupt(EXCP04_INTO, 1, 0, next_eip_addend);
1870 eaa728ee bellard
    }
1871 eaa728ee bellard
}
1872 eaa728ee bellard
1873 eaa728ee bellard
void helper_cmpxchg8b(target_ulong a0)
1874 eaa728ee bellard
{
1875 eaa728ee bellard
    uint64_t d;
1876 eaa728ee bellard
    int eflags;
1877 eaa728ee bellard
1878 a7812ae4 pbrook
    eflags = helper_cc_compute_all(CC_OP);
1879 eaa728ee bellard
    d = ldq(a0);
1880 eaa728ee bellard
    if (d == (((uint64_t)EDX << 32) | (uint32_t)EAX)) {
1881 eaa728ee bellard
        stq(a0, ((uint64_t)ECX << 32) | (uint32_t)EBX);
1882 eaa728ee bellard
        eflags |= CC_Z;
1883 eaa728ee bellard
    } else {
1884 278ed7c3 bellard
        /* always do the store */
1885 278ed7c3 bellard
        stq(a0, d); 
1886 eaa728ee bellard
        EDX = (uint32_t)(d >> 32);
1887 eaa728ee bellard
        EAX = (uint32_t)d;
1888 eaa728ee bellard
        eflags &= ~CC_Z;
1889 eaa728ee bellard
    }
1890 eaa728ee bellard
    CC_SRC = eflags;
1891 eaa728ee bellard
}
1892 eaa728ee bellard
1893 eaa728ee bellard
#ifdef TARGET_X86_64
1894 eaa728ee bellard
void helper_cmpxchg16b(target_ulong a0)
1895 eaa728ee bellard
{
1896 eaa728ee bellard
    uint64_t d0, d1;
1897 eaa728ee bellard
    int eflags;
1898 eaa728ee bellard
1899 278ed7c3 bellard
    if ((a0 & 0xf) != 0)
1900 278ed7c3 bellard
        raise_exception(EXCP0D_GPF);
1901 a7812ae4 pbrook
    eflags = helper_cc_compute_all(CC_OP);
1902 eaa728ee bellard
    d0 = ldq(a0);
1903 eaa728ee bellard
    d1 = ldq(a0 + 8);
1904 eaa728ee bellard
    if (d0 == EAX && d1 == EDX) {
1905 eaa728ee bellard
        stq(a0, EBX);
1906 eaa728ee bellard
        stq(a0 + 8, ECX);
1907 eaa728ee bellard
        eflags |= CC_Z;
1908 eaa728ee bellard
    } else {
1909 278ed7c3 bellard
        /* always do the store */
1910 278ed7c3 bellard
        stq(a0, d0); 
1911 278ed7c3 bellard
        stq(a0 + 8, d1); 
1912 eaa728ee bellard
        EDX = d1;
1913 eaa728ee bellard
        EAX = d0;
1914 eaa728ee bellard
        eflags &= ~CC_Z;
1915 eaa728ee bellard
    }
1916 eaa728ee bellard
    CC_SRC = eflags;
1917 eaa728ee bellard
}
1918 eaa728ee bellard
#endif
1919 eaa728ee bellard
1920 eaa728ee bellard
void helper_single_step(void)
1921 eaa728ee bellard
{
1922 01df040b aliguori
#ifndef CONFIG_USER_ONLY
1923 01df040b aliguori
    check_hw_breakpoints(env, 1);
1924 01df040b aliguori
    env->dr[6] |= DR6_BS;
1925 01df040b aliguori
#endif
1926 01df040b aliguori
    raise_exception(EXCP01_DB);
1927 eaa728ee bellard
}
1928 eaa728ee bellard
1929 eaa728ee bellard
void helper_cpuid(void)
1930 eaa728ee bellard
{
1931 6fd805e1 aliguori
    uint32_t eax, ebx, ecx, edx;
1932 eaa728ee bellard
1933 872929aa bellard
    helper_svm_check_intercept_param(SVM_EXIT_CPUID, 0);
1934 e737b32a balrog
1935 e00b6f80 aliguori
    cpu_x86_cpuid(env, (uint32_t)EAX, (uint32_t)ECX, &eax, &ebx, &ecx, &edx);
1936 6fd805e1 aliguori
    EAX = eax;
1937 6fd805e1 aliguori
    EBX = ebx;
1938 6fd805e1 aliguori
    ECX = ecx;
1939 6fd805e1 aliguori
    EDX = edx;
1940 eaa728ee bellard
}
1941 eaa728ee bellard
1942 eaa728ee bellard
void helper_enter_level(int level, int data32, target_ulong t1)
1943 eaa728ee bellard
{
1944 eaa728ee bellard
    target_ulong ssp;
1945 eaa728ee bellard
    uint32_t esp_mask, esp, ebp;
1946 eaa728ee bellard
1947 eaa728ee bellard
    esp_mask = get_sp_mask(env->segs[R_SS].flags);
1948 eaa728ee bellard
    ssp = env->segs[R_SS].base;
1949 eaa728ee bellard
    ebp = EBP;
1950 eaa728ee bellard
    esp = ESP;
1951 eaa728ee bellard
    if (data32) {
1952 eaa728ee bellard
        /* 32 bit */
1953 eaa728ee bellard
        esp -= 4;
1954 eaa728ee bellard
        while (--level) {
1955 eaa728ee bellard
            esp -= 4;
1956 eaa728ee bellard
            ebp -= 4;
1957 eaa728ee bellard
            stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask)));
1958 eaa728ee bellard
        }
1959 eaa728ee bellard
        esp -= 4;
1960 eaa728ee bellard
        stl(ssp + (esp & esp_mask), t1);
1961 eaa728ee bellard
    } else {
1962 eaa728ee bellard
        /* 16 bit */
1963 eaa728ee bellard
        esp -= 2;
1964 eaa728ee bellard
        while (--level) {
1965 eaa728ee bellard
            esp -= 2;
1966 eaa728ee bellard
            ebp -= 2;
1967 eaa728ee bellard
            stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask)));
1968 eaa728ee bellard
        }
1969 eaa728ee bellard
        esp -= 2;
1970 eaa728ee bellard
        stw(ssp + (esp & esp_mask), t1);
1971 eaa728ee bellard
    }
1972 eaa728ee bellard
}
1973 eaa728ee bellard
1974 eaa728ee bellard
#ifdef TARGET_X86_64
1975 eaa728ee bellard
void helper_enter64_level(int level, int data64, target_ulong t1)
1976 eaa728ee bellard
{
1977 eaa728ee bellard
    target_ulong esp, ebp;
1978 eaa728ee bellard
    ebp = EBP;
1979 eaa728ee bellard
    esp = ESP;
1980 eaa728ee bellard
1981 eaa728ee bellard
    if (data64) {
1982 eaa728ee bellard
        /* 64 bit */
1983 eaa728ee bellard
        esp -= 8;
1984 eaa728ee bellard
        while (--level) {
1985 eaa728ee bellard
            esp -= 8;
1986 eaa728ee bellard
            ebp -= 8;
1987 eaa728ee bellard
            stq(esp, ldq(ebp));
1988 eaa728ee bellard
        }
1989 eaa728ee bellard
        esp -= 8;
1990 eaa728ee bellard
        stq(esp, t1);
1991 eaa728ee bellard
    } else {
1992 eaa728ee bellard
        /* 16 bit */
1993 eaa728ee bellard
        esp -= 2;
1994 eaa728ee bellard
        while (--level) {
1995 eaa728ee bellard
            esp -= 2;
1996 eaa728ee bellard
            ebp -= 2;
1997 eaa728ee bellard
            stw(esp, lduw(ebp));
1998 eaa728ee bellard
        }
1999 eaa728ee bellard
        esp -= 2;
2000 eaa728ee bellard
        stw(esp, t1);
2001 eaa728ee bellard
    }
2002 eaa728ee bellard
}
2003 eaa728ee bellard
#endif
2004 eaa728ee bellard
2005 eaa728ee bellard
void helper_lldt(int selector)
2006 eaa728ee bellard
{
2007 eaa728ee bellard
    SegmentCache *dt;
2008 eaa728ee bellard
    uint32_t e1, e2;
2009 eaa728ee bellard
    int index, entry_limit;
2010 eaa728ee bellard
    target_ulong ptr;
2011 eaa728ee bellard
2012 eaa728ee bellard
    selector &= 0xffff;
2013 eaa728ee bellard
    if ((selector & 0xfffc) == 0) {
2014 eaa728ee bellard
        /* XXX: NULL selector case: invalid LDT */
2015 eaa728ee bellard
        env->ldt.base = 0;
2016 eaa728ee bellard
        env->ldt.limit = 0;
2017 eaa728ee bellard
    } else {
2018 eaa728ee bellard
        if (selector & 0x4)
2019 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2020 eaa728ee bellard
        dt = &env->gdt;
2021 eaa728ee bellard
        index = selector & ~7;
2022 eaa728ee bellard
#ifdef TARGET_X86_64
2023 eaa728ee bellard
        if (env->hflags & HF_LMA_MASK)
2024 eaa728ee bellard
            entry_limit = 15;
2025 eaa728ee bellard
        else
2026 eaa728ee bellard
#endif
2027 eaa728ee bellard
            entry_limit = 7;
2028 eaa728ee bellard
        if ((index + entry_limit) > dt->limit)
2029 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2030 eaa728ee bellard
        ptr = dt->base + index;
2031 eaa728ee bellard
        e1 = ldl_kernel(ptr);
2032 eaa728ee bellard
        e2 = ldl_kernel(ptr + 4);
2033 eaa728ee bellard
        if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
2034 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2035 eaa728ee bellard
        if (!(e2 & DESC_P_MASK))
2036 eaa728ee bellard
            raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2037 eaa728ee bellard
#ifdef TARGET_X86_64
2038 eaa728ee bellard
        if (env->hflags & HF_LMA_MASK) {
2039 eaa728ee bellard
            uint32_t e3;
2040 eaa728ee bellard
            e3 = ldl_kernel(ptr + 8);
2041 eaa728ee bellard
            load_seg_cache_raw_dt(&env->ldt, e1, e2);
2042 eaa728ee bellard
            env->ldt.base |= (target_ulong)e3 << 32;
2043 eaa728ee bellard
        } else
2044 eaa728ee bellard
#endif
2045 eaa728ee bellard
        {
2046 eaa728ee bellard
            load_seg_cache_raw_dt(&env->ldt, e1, e2);
2047 eaa728ee bellard
        }
2048 eaa728ee bellard
    }
2049 eaa728ee bellard
    env->ldt.selector = selector;
2050 eaa728ee bellard
}
2051 eaa728ee bellard
2052 eaa728ee bellard
void helper_ltr(int selector)
2053 eaa728ee bellard
{
2054 eaa728ee bellard
    SegmentCache *dt;
2055 eaa728ee bellard
    uint32_t e1, e2;
2056 eaa728ee bellard
    int index, type, entry_limit;
2057 eaa728ee bellard
    target_ulong ptr;
2058 eaa728ee bellard
2059 eaa728ee bellard
    selector &= 0xffff;
2060 eaa728ee bellard
    if ((selector & 0xfffc) == 0) {
2061 eaa728ee bellard
        /* NULL selector case: invalid TR */
2062 eaa728ee bellard
        env->tr.base = 0;
2063 eaa728ee bellard
        env->tr.limit = 0;
2064 eaa728ee bellard
        env->tr.flags = 0;
2065 eaa728ee bellard
    } else {
2066 eaa728ee bellard
        if (selector & 0x4)
2067 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2068 eaa728ee bellard
        dt = &env->gdt;
2069 eaa728ee bellard
        index = selector & ~7;
2070 eaa728ee bellard
#ifdef TARGET_X86_64
2071 eaa728ee bellard
        if (env->hflags & HF_LMA_MASK)
2072 eaa728ee bellard
            entry_limit = 15;
2073 eaa728ee bellard
        else
2074 eaa728ee bellard
#endif
2075 eaa728ee bellard
            entry_limit = 7;
2076 eaa728ee bellard
        if ((index + entry_limit) > dt->limit)
2077 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2078 eaa728ee bellard
        ptr = dt->base + index;
2079 eaa728ee bellard
        e1 = ldl_kernel(ptr);
2080 eaa728ee bellard
        e2 = ldl_kernel(ptr + 4);
2081 eaa728ee bellard
        type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2082 eaa728ee bellard
        if ((e2 & DESC_S_MASK) ||
2083 eaa728ee bellard
            (type != 1 && type != 9))
2084 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2085 eaa728ee bellard
        if (!(e2 & DESC_P_MASK))
2086 eaa728ee bellard
            raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2087 eaa728ee bellard
#ifdef TARGET_X86_64
2088 eaa728ee bellard
        if (env->hflags & HF_LMA_MASK) {
2089 eaa728ee bellard
            uint32_t e3, e4;
2090 eaa728ee bellard
            e3 = ldl_kernel(ptr + 8);
2091 eaa728ee bellard
            e4 = ldl_kernel(ptr + 12);
2092 eaa728ee bellard
            if ((e4 >> DESC_TYPE_SHIFT) & 0xf)
2093 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2094 eaa728ee bellard
            load_seg_cache_raw_dt(&env->tr, e1, e2);
2095 eaa728ee bellard
            env->tr.base |= (target_ulong)e3 << 32;
2096 eaa728ee bellard
        } else
2097 eaa728ee bellard
#endif
2098 eaa728ee bellard
        {
2099 eaa728ee bellard
            load_seg_cache_raw_dt(&env->tr, e1, e2);
2100 eaa728ee bellard
        }
2101 eaa728ee bellard
        e2 |= DESC_TSS_BUSY_MASK;
2102 eaa728ee bellard
        stl_kernel(ptr + 4, e2);
2103 eaa728ee bellard
    }
2104 eaa728ee bellard
    env->tr.selector = selector;
2105 eaa728ee bellard
}
2106 eaa728ee bellard
2107 eaa728ee bellard
/* only works if protected mode and not VM86. seg_reg must be != R_CS */
2108 eaa728ee bellard
void helper_load_seg(int seg_reg, int selector)
2109 eaa728ee bellard
{
2110 eaa728ee bellard
    uint32_t e1, e2;
2111 eaa728ee bellard
    int cpl, dpl, rpl;
2112 eaa728ee bellard
    SegmentCache *dt;
2113 eaa728ee bellard
    int index;
2114 eaa728ee bellard
    target_ulong ptr;
2115 eaa728ee bellard
2116 eaa728ee bellard
    selector &= 0xffff;
2117 eaa728ee bellard
    cpl = env->hflags & HF_CPL_MASK;
2118 eaa728ee bellard
    if ((selector & 0xfffc) == 0) {
2119 eaa728ee bellard
        /* null selector case */
2120 eaa728ee bellard
        if (seg_reg == R_SS
2121 eaa728ee bellard
#ifdef TARGET_X86_64
2122 eaa728ee bellard
            && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
2123 eaa728ee bellard
#endif
2124 eaa728ee bellard
            )
2125 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, 0);
2126 eaa728ee bellard
        cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
2127 eaa728ee bellard
    } else {
2128 eaa728ee bellard
2129 eaa728ee bellard
        if (selector & 0x4)
2130 eaa728ee bellard
            dt = &env->ldt;
2131 eaa728ee bellard
        else
2132 eaa728ee bellard
            dt = &env->gdt;
2133 eaa728ee bellard
        index = selector & ~7;
2134 eaa728ee bellard
        if ((index + 7) > dt->limit)
2135 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2136 eaa728ee bellard
        ptr = dt->base + index;
2137 eaa728ee bellard
        e1 = ldl_kernel(ptr);
2138 eaa728ee bellard
        e2 = ldl_kernel(ptr + 4);
2139 eaa728ee bellard
2140 eaa728ee bellard
        if (!(e2 & DESC_S_MASK))
2141 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2142 eaa728ee bellard
        rpl = selector & 3;
2143 eaa728ee bellard
        dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2144 eaa728ee bellard
        if (seg_reg == R_SS) {
2145 eaa728ee bellard
            /* must be writable segment */
2146 eaa728ee bellard
            if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
2147 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2148 eaa728ee bellard
            if (rpl != cpl || dpl != cpl)
2149 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2150 eaa728ee bellard
        } else {
2151 eaa728ee bellard
            /* must be readable segment */
2152 eaa728ee bellard
            if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK)
2153 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2154 eaa728ee bellard
2155 eaa728ee bellard
            if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
2156 eaa728ee bellard
                /* if not conforming code, test rights */
2157 eaa728ee bellard
                if (dpl < cpl || dpl < rpl)
2158 eaa728ee bellard
                    raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2159 eaa728ee bellard
            }
2160 eaa728ee bellard
        }
2161 eaa728ee bellard
2162 eaa728ee bellard
        if (!(e2 & DESC_P_MASK)) {
2163 eaa728ee bellard
            if (seg_reg == R_SS)
2164 eaa728ee bellard
                raise_exception_err(EXCP0C_STACK, selector & 0xfffc);
2165 eaa728ee bellard
            else
2166 eaa728ee bellard
                raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2167 eaa728ee bellard
        }
2168 eaa728ee bellard
2169 eaa728ee bellard
        /* set the access bit if not already set */
2170 eaa728ee bellard
        if (!(e2 & DESC_A_MASK)) {
2171 eaa728ee bellard
            e2 |= DESC_A_MASK;
2172 eaa728ee bellard
            stl_kernel(ptr + 4, e2);
2173 eaa728ee bellard
        }
2174 eaa728ee bellard
2175 eaa728ee bellard
        cpu_x86_load_seg_cache(env, seg_reg, selector,
2176 eaa728ee bellard
                       get_seg_base(e1, e2),
2177 eaa728ee bellard
                       get_seg_limit(e1, e2),
2178 eaa728ee bellard
                       e2);
2179 eaa728ee bellard
#if 0
2180 93fcfe39 aliguori
        qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
2181 eaa728ee bellard
                selector, (unsigned long)sc->base, sc->limit, sc->flags);
2182 eaa728ee bellard
#endif
2183 eaa728ee bellard
    }
2184 eaa728ee bellard
}
2185 eaa728ee bellard
2186 eaa728ee bellard
/* protected mode jump */
2187 eaa728ee bellard
void helper_ljmp_protected(int new_cs, target_ulong new_eip,
2188 eaa728ee bellard
                           int next_eip_addend)
2189 eaa728ee bellard
{
2190 eaa728ee bellard
    int gate_cs, type;
2191 eaa728ee bellard
    uint32_t e1, e2, cpl, dpl, rpl, limit;
2192 eaa728ee bellard
    target_ulong next_eip;
2193 eaa728ee bellard
2194 eaa728ee bellard
    if ((new_cs & 0xfffc) == 0)
2195 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, 0);
2196 eaa728ee bellard
    if (load_segment(&e1, &e2, new_cs) != 0)
2197 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2198 eaa728ee bellard
    cpl = env->hflags & HF_CPL_MASK;
2199 eaa728ee bellard
    if (e2 & DESC_S_MASK) {
2200 eaa728ee bellard
        if (!(e2 & DESC_CS_MASK))
2201 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2202 eaa728ee bellard
        dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2203 eaa728ee bellard
        if (e2 & DESC_C_MASK) {
2204 eaa728ee bellard
            /* conforming code segment */
2205 eaa728ee bellard
            if (dpl > cpl)
2206 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2207 eaa728ee bellard
        } else {
2208 eaa728ee bellard
            /* non conforming code segment */
2209 eaa728ee bellard
            rpl = new_cs & 3;
2210 eaa728ee bellard
            if (rpl > cpl)
2211 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2212 eaa728ee bellard
            if (dpl != cpl)
2213 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2214 eaa728ee bellard
        }
2215 eaa728ee bellard
        if (!(e2 & DESC_P_MASK))
2216 eaa728ee bellard
            raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2217 eaa728ee bellard
        limit = get_seg_limit(e1, e2);
2218 eaa728ee bellard
        if (new_eip > limit &&
2219 eaa728ee bellard
            !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
2220 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2221 eaa728ee bellard
        cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
2222 eaa728ee bellard
                       get_seg_base(e1, e2), limit, e2);
2223 eaa728ee bellard
        EIP = new_eip;
2224 eaa728ee bellard
    } else {
2225 eaa728ee bellard
        /* jump to call or task gate */
2226 eaa728ee bellard
        dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2227 eaa728ee bellard
        rpl = new_cs & 3;
2228 eaa728ee bellard
        cpl = env->hflags & HF_CPL_MASK;
2229 eaa728ee bellard
        type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2230 eaa728ee bellard
        switch(type) {
2231 eaa728ee bellard
        case 1: /* 286 TSS */
2232 eaa728ee bellard
        case 9: /* 386 TSS */
2233 eaa728ee bellard
        case 5: /* task gate */
2234 eaa728ee bellard
            if (dpl < cpl || dpl < rpl)
2235 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2236 eaa728ee bellard
            next_eip = env->eip + next_eip_addend;
2237 eaa728ee bellard
            switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
2238 eaa728ee bellard
            CC_OP = CC_OP_EFLAGS;
2239 eaa728ee bellard
            break;
2240 eaa728ee bellard
        case 4: /* 286 call gate */
2241 eaa728ee bellard
        case 12: /* 386 call gate */
2242 eaa728ee bellard
            if ((dpl < cpl) || (dpl < rpl))
2243 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2244 eaa728ee bellard
            if (!(e2 & DESC_P_MASK))
2245 eaa728ee bellard
                raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2246 eaa728ee bellard
            gate_cs = e1 >> 16;
2247 eaa728ee bellard
            new_eip = (e1 & 0xffff);
2248 eaa728ee bellard
            if (type == 12)
2249 eaa728ee bellard
                new_eip |= (e2 & 0xffff0000);
2250 eaa728ee bellard
            if (load_segment(&e1, &e2, gate_cs) != 0)
2251 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2252 eaa728ee bellard
            dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2253 eaa728ee bellard
            /* must be code segment */
2254 eaa728ee bellard
            if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
2255 eaa728ee bellard
                 (DESC_S_MASK | DESC_CS_MASK)))
2256 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2257 eaa728ee bellard
            if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
2258 eaa728ee bellard
                (!(e2 & DESC_C_MASK) && (dpl != cpl)))
2259 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2260 eaa728ee bellard
            if (!(e2 & DESC_P_MASK))
2261 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2262 eaa728ee bellard
            limit = get_seg_limit(e1, e2);
2263 eaa728ee bellard
            if (new_eip > limit)
2264 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, 0);
2265 eaa728ee bellard
            cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
2266 eaa728ee bellard
                                   get_seg_base(e1, e2), limit, e2);
2267 eaa728ee bellard
            EIP = new_eip;
2268 eaa728ee bellard
            break;
2269 eaa728ee bellard
        default:
2270 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2271 eaa728ee bellard
            break;
2272 eaa728ee bellard
        }
2273 eaa728ee bellard
    }
2274 eaa728ee bellard
}
2275 eaa728ee bellard
2276 eaa728ee bellard
/* real mode call */
2277 eaa728ee bellard
void helper_lcall_real(int new_cs, target_ulong new_eip1,
2278 eaa728ee bellard
                       int shift, int next_eip)
2279 eaa728ee bellard
{
2280 eaa728ee bellard
    int new_eip;
2281 eaa728ee bellard
    uint32_t esp, esp_mask;
2282 eaa728ee bellard
    target_ulong ssp;
2283 eaa728ee bellard
2284 eaa728ee bellard
    new_eip = new_eip1;
2285 eaa728ee bellard
    esp = ESP;
2286 eaa728ee bellard
    esp_mask = get_sp_mask(env->segs[R_SS].flags);
2287 eaa728ee bellard
    ssp = env->segs[R_SS].base;
2288 eaa728ee bellard
    if (shift) {
2289 eaa728ee bellard
        PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
2290 eaa728ee bellard
        PUSHL(ssp, esp, esp_mask, next_eip);
2291 eaa728ee bellard
    } else {
2292 eaa728ee bellard
        PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
2293 eaa728ee bellard
        PUSHW(ssp, esp, esp_mask, next_eip);
2294 eaa728ee bellard
    }
2295 eaa728ee bellard
2296 eaa728ee bellard
    SET_ESP(esp, esp_mask);
2297 eaa728ee bellard
    env->eip = new_eip;
2298 eaa728ee bellard
    env->segs[R_CS].selector = new_cs;
2299 eaa728ee bellard
    env->segs[R_CS].base = (new_cs << 4);
2300 eaa728ee bellard
}
2301 eaa728ee bellard
2302 eaa728ee bellard
/* protected mode call */
2303 eaa728ee bellard
void helper_lcall_protected(int new_cs, target_ulong new_eip, 
2304 eaa728ee bellard
                            int shift, int next_eip_addend)
2305 eaa728ee bellard
{
2306 eaa728ee bellard
    int new_stack, i;
2307 eaa728ee bellard
    uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
2308 1c918eba blueswir1
    uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, sp, type, ss_dpl, sp_mask;
2309 eaa728ee bellard
    uint32_t val, limit, old_sp_mask;
2310 eaa728ee bellard
    target_ulong ssp, old_ssp, next_eip;
2311 eaa728ee bellard
2312 eaa728ee bellard
    next_eip = env->eip + next_eip_addend;
2313 d12d51d5 aliguori
    LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
2314 d12d51d5 aliguori
    LOG_PCALL_STATE(env);
2315 eaa728ee bellard
    if ((new_cs & 0xfffc) == 0)
2316 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, 0);
2317 eaa728ee bellard
    if (load_segment(&e1, &e2, new_cs) != 0)
2318 eaa728ee bellard
        raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2319 eaa728ee bellard
    cpl = env->hflags & HF_CPL_MASK;
2320 d12d51d5 aliguori
    LOG_PCALL("desc=%08x:%08x\n", e1, e2);
2321 eaa728ee bellard
    if (e2 & DESC_S_MASK) {
2322 eaa728ee bellard
        if (!(e2 & DESC_CS_MASK))
2323 eaa728ee bellard
            raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2324 eaa728ee bellard
        dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2325 eaa728ee bellard
        if (e2 & DESC_C_MASK) {
2326 eaa728ee bellard
            /* conforming code segment */
2327 eaa728ee bellard
            if (dpl > cpl)
2328 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2329 eaa728ee bellard
        } else {
2330 eaa728ee bellard
            /* non conforming code segment */
2331 eaa728ee bellard
            rpl = new_cs & 3;
2332 eaa728ee bellard
            if (rpl > cpl)
2333 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2334 eaa728ee bellard
            if (dpl != cpl)
2335 eaa728ee bellard
                raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2336 eaa728ee bellard
        }
2337 eaa728ee bellard
        if (!(e2 & DESC_P_MASK))
2338 eaa728ee bellard
            raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2339 eaa728ee bellard
2340 eaa728ee bellard
#ifdef TARGET_X86_64
2341 eaa728ee bellard
        /* XXX: check 16/32 bit cases in long mode */
2342 eaa728ee bellard
        if (shift == 2) {
2343 eaa728ee bellard
            target_ulong rsp;
2344 eaa728ee bellard
            /* 64 bit case */
2345 eaa728ee bellard
            rsp = ESP;
2346 eaa728ee bellard
            PUSHQ(rsp, env->segs[R_CS].selector);
2347 eaa728ee bellard
            PUSHQ(rsp, next_eip);
2348 eaa728ee bellard
            /* from this point, not restartable */
2349 eaa728ee bellard
            ESP = rsp;
2350 eaa728ee bellard
            cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
2351 eaa728ee bellard
                                   get_seg_base(e1, e2),
2352 eaa728ee bellard
                                   get_seg_limit(e1, e2), e2);
2353 eaa728ee bellard
            EIP = new_eip;
2354 eaa728ee bellard
        } else
2355 eaa728ee bellard
#endif
2356 eaa728ee bellard
        {
2357 eaa728ee bellard
            sp = ESP;
2358 eaa728ee bellard
            sp_mask = get_sp_mask(env->segs[R_SS].flags);
2359 eaa728ee bellard
            ssp = env->segs[R_SS].base;
2360<