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/*
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 *  i386 execution defines
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "config.h"
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#include "dyngen-exec.h"
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/* XXX: factorize this mess */
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#ifdef TARGET_X86_64
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#define TARGET_LONG_BITS 64
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#else
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#define TARGET_LONG_BITS 32
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#endif
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#include "cpu-defs.h"
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register struct CPUX86State *env asm(AREG0);
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#include "qemu-common.h"
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#include "qemu-log.h"
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#define EAX (env->regs[R_EAX])
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#define ECX (env->regs[R_ECX])
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#define EDX (env->regs[R_EDX])
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#define EBX (env->regs[R_EBX])
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#define ESP (env->regs[R_ESP])
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#define EBP (env->regs[R_EBP])
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#define ESI (env->regs[R_ESI])
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#define EDI (env->regs[R_EDI])
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#define EIP (env->eip)
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#define DF  (env->df)
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#define CC_SRC (env->cc_src)
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#define CC_DST (env->cc_dst)
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#define CC_OP  (env->cc_op)
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/* float macros */
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#define FT0    (env->ft0)
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#define ST0    (env->fpregs[env->fpstt].d)
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#define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7].d)
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#define ST1    ST(1)
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#include "cpu.h"
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#include "exec-all.h"
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/* op_helper.c */
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void do_interrupt(int intno, int is_int, int error_code,
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                  target_ulong next_eip, int is_hw);
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void do_interrupt_user(int intno, int is_int, int error_code,
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                       target_ulong next_eip);
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void QEMU_NORETURN raise_exception_err(int exception_index, int error_code);
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void QEMU_NORETURN raise_exception(int exception_index);
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void do_smm_enter(void);
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/* n must be a constant to be efficient */
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static inline target_long lshift(target_long x, int n)
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{
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    if (n >= 0)
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        return x << n;
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    else
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        return x >> (-n);
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}
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#include "helper.h"
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static inline void svm_check_intercept(uint32_t type)
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{
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    helper_svm_check_intercept_param(type, 0);
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}
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#if !defined(CONFIG_USER_ONLY)
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#include "softmmu_exec.h"
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#endif /* !defined(CONFIG_USER_ONLY) */
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#ifdef USE_X86LDOUBLE
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/* use long double functions */
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#define floatx_to_int32 floatx80_to_int32
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#define floatx_to_int64 floatx80_to_int64
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#define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
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#define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
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#define int32_to_floatx int32_to_floatx80
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#define int64_to_floatx int64_to_floatx80
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#define float32_to_floatx float32_to_floatx80
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#define float64_to_floatx float64_to_floatx80
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#define floatx_to_float32 floatx80_to_float32
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#define floatx_to_float64 floatx80_to_float64
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#define floatx_abs floatx80_abs
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#define floatx_chs floatx80_chs
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#define floatx_round_to_int floatx80_round_to_int
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#define floatx_compare floatx80_compare
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#define floatx_compare_quiet floatx80_compare_quiet
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#else
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#define floatx_to_int32 float64_to_int32
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#define floatx_to_int64 float64_to_int64
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#define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
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#define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
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#define int32_to_floatx int32_to_float64
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#define int64_to_floatx int64_to_float64
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#define float32_to_floatx float32_to_float64
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#define float64_to_floatx(x, e) (x)
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#define floatx_to_float32 float64_to_float32
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#define floatx_to_float64(x, e) (x)
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#define floatx_abs float64_abs
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#define floatx_chs float64_chs
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#define floatx_round_to_int float64_round_to_int
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#define floatx_compare float64_compare
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#define floatx_compare_quiet float64_compare_quiet
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#endif
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#define RC_MASK         0xc00
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#define RC_NEAR                0x000
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#define RC_DOWN                0x400
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#define RC_UP                0x800
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#define RC_CHOP                0xc00
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#define MAXTAN 9223372036854775808.0
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#ifdef USE_X86LDOUBLE
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/* only for x86 */
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typedef union {
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    long double d;
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    struct {
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        unsigned long long lower;
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        unsigned short upper;
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    } l;
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} CPU86_LDoubleU;
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/* the following deal with x86 long double-precision numbers */
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#define MAXEXPD 0x7fff
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#define EXPBIAS 16383
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#define EXPD(fp)        (fp.l.upper & 0x7fff)
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#define SIGND(fp)        ((fp.l.upper) & 0x8000)
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#define MANTD(fp)       (fp.l.lower)
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#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
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#else
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/* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
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typedef union {
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    double d;
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#if !defined(HOST_WORDS_BIGENDIAN) && !defined(__arm__)
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    struct {
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        uint32_t lower;
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        int32_t upper;
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    } l;
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#else
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    struct {
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        int32_t upper;
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        uint32_t lower;
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    } l;
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#endif
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#ifndef __arm__
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    int64_t ll;
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#endif
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} CPU86_LDoubleU;
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/* the following deal with IEEE double-precision numbers */
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#define MAXEXPD 0x7ff
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#define EXPBIAS 1023
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#define EXPD(fp)        (((fp.l.upper) >> 20) & 0x7FF)
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#define SIGND(fp)        ((fp.l.upper) & 0x80000000)
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#ifdef __arm__
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#define MANTD(fp)        (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32))
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#else
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#define MANTD(fp)        (fp.ll & ((1LL << 52) - 1))
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#endif
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#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20)
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#endif
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static inline void fpush(void)
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{
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    env->fpstt = (env->fpstt - 1) & 7;
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    env->fptags[env->fpstt] = 0; /* validate stack entry */
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}
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static inline void fpop(void)
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{
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    env->fptags[env->fpstt] = 1; /* invvalidate stack entry */
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    env->fpstt = (env->fpstt + 1) & 7;
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}
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#ifndef USE_X86LDOUBLE
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static inline CPU86_LDouble helper_fldt(target_ulong ptr)
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{
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    CPU86_LDoubleU temp;
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    int upper, e;
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    uint64_t ll;
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    /* mantissa */
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    upper = lduw(ptr + 8);
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    /* XXX: handle overflow ? */
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    e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
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    e |= (upper >> 4) & 0x800; /* sign */
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    ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1);
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#ifdef __arm__
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    temp.l.upper = (e << 20) | (ll >> 32);
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    temp.l.lower = ll;
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#else
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    temp.ll = ll | ((uint64_t)e << 52);
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#endif
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    return temp.d;
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}
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static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
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{
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    CPU86_LDoubleU temp;
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    int e;
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    temp.d = f;
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    /* mantissa */
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    stq(ptr, (MANTD(temp) << 11) | (1LL << 63));
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    /* exponent + sign */
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    e = EXPD(temp) - EXPBIAS + 16383;
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    e |= SIGND(temp) >> 16;
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    stw(ptr + 8, e);
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}
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#else
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/* we use memory access macros */
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static inline CPU86_LDouble helper_fldt(target_ulong ptr)
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{
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    CPU86_LDoubleU temp;
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    temp.l.lower = ldq(ptr);
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    temp.l.upper = lduw(ptr + 8);
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    return temp.d;
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}
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static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
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{
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    CPU86_LDoubleU temp;
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    temp.d = f;
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    stq(ptr, temp.l.lower);
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    stw(ptr + 8, temp.l.upper);
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}
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#endif /* USE_X86LDOUBLE */
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#define FPUS_IE (1 << 0)
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#define FPUS_DE (1 << 1)
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#define FPUS_ZE (1 << 2)
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#define FPUS_OE (1 << 3)
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#define FPUS_UE (1 << 4)
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#define FPUS_PE (1 << 5)
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#define FPUS_SF (1 << 6)
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#define FPUS_SE (1 << 7)
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#define FPUS_B  (1 << 15)
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#define FPUC_EM 0x3f
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static inline uint32_t compute_eflags(void)
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{
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    return env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
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}
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/* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
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static inline void load_eflags(int eflags, int update_mask)
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{
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    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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    DF = 1 - (2 * ((eflags >> 10) & 1));
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    env->eflags = (env->eflags & ~update_mask) |
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        (eflags & update_mask) | 0x2;
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}
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static inline void env_to_regs(void)
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{
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#ifdef reg_EAX
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    EAX = env->regs[R_EAX];
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#endif
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#ifdef reg_ECX
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    ECX = env->regs[R_ECX];
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#endif
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#ifdef reg_EDX
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    EDX = env->regs[R_EDX];
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#endif
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#ifdef reg_EBX
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    EBX = env->regs[R_EBX];
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#endif
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#ifdef reg_ESP
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    ESP = env->regs[R_ESP];
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#endif
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#ifdef reg_EBP
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    EBP = env->regs[R_EBP];
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#endif
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#ifdef reg_ESI
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    ESI = env->regs[R_ESI];
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#endif
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#ifdef reg_EDI
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    EDI = env->regs[R_EDI];
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#endif
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}
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static inline void regs_to_env(void)
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{
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#ifdef reg_EAX
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    env->regs[R_EAX] = EAX;
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#endif
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#ifdef reg_ECX
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    env->regs[R_ECX] = ECX;
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#endif
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#ifdef reg_EDX
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    env->regs[R_EDX] = EDX;
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#endif
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#ifdef reg_EBX
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    env->regs[R_EBX] = EBX;
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#endif
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#ifdef reg_ESP
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    env->regs[R_ESP] = ESP;
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#endif
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#ifdef reg_EBP
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    env->regs[R_EBP] = EBP;
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#endif
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#ifdef reg_ESI
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    env->regs[R_ESI] = ESI;
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#endif
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#ifdef reg_EDI
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    env->regs[R_EDI] = EDI;
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#endif
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}
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static inline int cpu_has_work(CPUState *env)
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{
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    int work;
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    work = (env->interrupt_request & CPU_INTERRUPT_HARD) &&
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           (env->eflags & IF_MASK);
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    work |= env->interrupt_request & CPU_INTERRUPT_NMI;
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    work |= env->interrupt_request & CPU_INTERRUPT_INIT;
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    work |= env->interrupt_request & CPU_INTERRUPT_SIPI;
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    return work;
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}
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static inline int cpu_halted(CPUState *env) {
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    /* handle exit of HALTED state */
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    if (!env->halted)
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        return 0;
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    /* disable halt condition */
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    if (cpu_has_work(env)) {
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        env->halted = 0;
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        return 0;
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    }
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    return EXCP_HALTED;
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}
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/* load efer and update the corresponding hflags. XXX: do consistency
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   checks with cpuid bits ? */
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static inline void cpu_load_efer(CPUState *env, uint64_t val)
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{
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    env->efer = val;
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    env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
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    if (env->efer & MSR_EFER_LMA)
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        env->hflags |= HF_LMA_MASK;
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    if (env->efer & MSR_EFER_SVME)
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        env->hflags |= HF_SVME_MASK;
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}