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1
/*
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 * QEMU KVM support
3
 *
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 * Copyright (C) 2006-2008 Qumranet Technologies
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 * Copyright IBM, Corp. 2008
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 *
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 * Authors:
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 *  Anthony Liguori   <aliguori@us.ibm.com>
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 *
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 * This work is licensed under the terms of the GNU GPL, version 2 or later.
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 * See the COPYING file in the top-level directory.
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 *
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 */
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#include <sys/types.h>
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#include <sys/ioctl.h>
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#include <sys/mman.h>
18

    
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#include <linux/kvm.h>
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#include "qemu-common.h"
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#include "sysemu.h"
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#include "kvm.h"
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#include "cpu.h"
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#include "gdbstub.h"
26

    
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//#define DEBUG_KVM
28

    
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#ifdef DEBUG_KVM
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#define dprintf(fmt, ...) \
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    do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
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#else
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#define dprintf(fmt, ...) \
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    do { } while (0)
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#endif
36

    
37
#ifdef KVM_CAP_EXT_CPUID
38

    
39
static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
40
{
41
    struct kvm_cpuid2 *cpuid;
42
    int r, size;
43

    
44
    size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
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    cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
46
    cpuid->nent = max;
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    r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
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    if (r == 0 && cpuid->nent >= max) {
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        r = -E2BIG;
50
    }
51
    if (r < 0) {
52
        if (r == -E2BIG) {
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            qemu_free(cpuid);
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            return NULL;
55
        } else {
56
            fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
57
                    strerror(-r));
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            exit(1);
59
        }
60
    }
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    return cpuid;
62
}
63

    
64
uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
65
{
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    struct kvm_cpuid2 *cpuid;
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    int i, max;
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    uint32_t ret = 0;
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    uint32_t cpuid_1_edx;
70

    
71
    if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
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        return -1U;
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    }
74

    
75
    max = 1;
76
    while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
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        max *= 2;
78
    }
79

    
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    for (i = 0; i < cpuid->nent; ++i) {
81
        if (cpuid->entries[i].function == function) {
82
            switch (reg) {
83
            case R_EAX:
84
                ret = cpuid->entries[i].eax;
85
                break;
86
            case R_EBX:
87
                ret = cpuid->entries[i].ebx;
88
                break;
89
            case R_ECX:
90
                ret = cpuid->entries[i].ecx;
91
                break;
92
            case R_EDX:
93
                ret = cpuid->entries[i].edx;
94
                if (function == 0x80000001) {
95
                    /* On Intel, kvm returns cpuid according to the Intel spec,
96
                     * so add missing bits according to the AMD spec:
97
                     */
98
                    cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
99
                    ret |= cpuid_1_edx & 0xdfeff7ff;
100
                }
101
                break;
102
            }
103
        }
104
    }
105

    
106
    qemu_free(cpuid);
107

    
108
    return ret;
109
}
110

    
111
#else
112

    
113
uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
114
{
115
    return -1U;
116
}
117

    
118
#endif
119

    
120
static void kvm_trim_features(uint32_t *features, uint32_t supported)
121
{
122
    int i;
123
    uint32_t mask;
124

    
125
    for (i = 0; i < 32; ++i) {
126
        mask = 1U << i;
127
        if ((*features & mask) && !(supported & mask)) {
128
            *features &= ~mask;
129
        }
130
    }
131
}
132

    
133
int kvm_arch_init_vcpu(CPUState *env)
134
{
135
    struct {
136
        struct kvm_cpuid2 cpuid;
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        struct kvm_cpuid_entry2 entries[100];
138
    } __attribute__((packed)) cpuid_data;
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    uint32_t limit, i, j, cpuid_i;
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    uint32_t unused;
141

    
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    env->mp_state = KVM_MP_STATE_RUNNABLE;
143

    
144
    kvm_trim_features(&env->cpuid_features,
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        kvm_arch_get_supported_cpuid(env, 1, R_EDX));
146

    
147
    i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
148
    kvm_trim_features(&env->cpuid_ext_features,
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        kvm_arch_get_supported_cpuid(env, 1, R_ECX));
150
    env->cpuid_ext_features |= i;
151

    
152
    kvm_trim_features(&env->cpuid_ext2_features,
153
        kvm_arch_get_supported_cpuid(env, 0x80000001, R_EDX));
154
    kvm_trim_features(&env->cpuid_ext3_features,
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        kvm_arch_get_supported_cpuid(env, 0x80000001, R_ECX));
156

    
157
    cpuid_i = 0;
158

    
159
    cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
160

    
161
    for (i = 0; i <= limit; i++) {
162
        struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
163

    
164
        switch (i) {
165
        case 2: {
166
            /* Keep reading function 2 till all the input is received */
167
            int times;
168

    
169
            c->function = i;
170
            c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
171
                       KVM_CPUID_FLAG_STATE_READ_NEXT;
172
            cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
173
            times = c->eax & 0xff;
174

    
175
            for (j = 1; j < times; ++j) {
176
                c = &cpuid_data.entries[cpuid_i++];
177
                c->function = i;
178
                c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
179
                cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
180
            }
181
            break;
182
        }
183
        case 4:
184
        case 0xb:
185
        case 0xd:
186
            for (j = 0; ; j++) {
187
                c->function = i;
188
                c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
189
                c->index = j;
190
                cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
191

    
192
                if (i == 4 && c->eax == 0)
193
                    break;
194
                if (i == 0xb && !(c->ecx & 0xff00))
195
                    break;
196
                if (i == 0xd && c->eax == 0)
197
                    break;
198

    
199
                c = &cpuid_data.entries[cpuid_i++];
200
            }
201
            break;
202
        default:
203
            c->function = i;
204
            c->flags = 0;
205
            cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
206
            break;
207
        }
208
    }
209
    cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
210

    
211
    for (i = 0x80000000; i <= limit; i++) {
212
        struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
213

    
214
        c->function = i;
215
        c->flags = 0;
216
        cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
217
    }
218

    
219
    cpuid_data.cpuid.nent = cpuid_i;
220

    
221
    return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
222
}
223

    
224
static int kvm_has_msr_star(CPUState *env)
225
{
226
    static int has_msr_star;
227
    int ret;
228

    
229
    /* first time */
230
    if (has_msr_star == 0) {        
231
        struct kvm_msr_list msr_list, *kvm_msr_list;
232

    
233
        has_msr_star = -1;
234

    
235
        /* Obtain MSR list from KVM.  These are the MSRs that we must
236
         * save/restore */
237
        msr_list.nmsrs = 0;
238
        ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
239
        if (ret < 0)
240
            return 0;
241

    
242
        /* Old kernel modules had a bug and could write beyond the provided
243
           memory. Allocate at least a safe amount of 1K. */
244
        kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
245
                                              msr_list.nmsrs *
246
                                              sizeof(msr_list.indices[0])));
247

    
248
        kvm_msr_list->nmsrs = msr_list.nmsrs;
249
        ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
250
        if (ret >= 0) {
251
            int i;
252

    
253
            for (i = 0; i < kvm_msr_list->nmsrs; i++) {
254
                if (kvm_msr_list->indices[i] == MSR_STAR) {
255
                    has_msr_star = 1;
256
                    break;
257
                }
258
            }
259
        }
260

    
261
        free(kvm_msr_list);
262
    }
263

    
264
    if (has_msr_star == 1)
265
        return 1;
266
    return 0;
267
}
268

    
269
int kvm_arch_init(KVMState *s, int smp_cpus)
270
{
271
    int ret;
272

    
273
    /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
274
     * directly.  In order to use vm86 mode, a TSS is needed.  Since this
275
     * must be part of guest physical memory, we need to allocate it.  Older
276
     * versions of KVM just assumed that it would be at the end of physical
277
     * memory but that doesn't work with more than 4GB of memory.  We simply
278
     * refuse to work with those older versions of KVM. */
279
    ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
280
    if (ret <= 0) {
281
        fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
282
        return ret;
283
    }
284

    
285
    /* this address is 3 pages before the bios, and the bios should present
286
     * as unavaible memory.  FIXME, need to ensure the e820 map deals with
287
     * this?
288
     */
289
    return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
290
}
291
                    
292
static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
293
{
294
    lhs->selector = rhs->selector;
295
    lhs->base = rhs->base;
296
    lhs->limit = rhs->limit;
297
    lhs->type = 3;
298
    lhs->present = 1;
299
    lhs->dpl = 3;
300
    lhs->db = 0;
301
    lhs->s = 1;
302
    lhs->l = 0;
303
    lhs->g = 0;
304
    lhs->avl = 0;
305
    lhs->unusable = 0;
306
}
307

    
308
static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
309
{
310
    unsigned flags = rhs->flags;
311
    lhs->selector = rhs->selector;
312
    lhs->base = rhs->base;
313
    lhs->limit = rhs->limit;
314
    lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
315
    lhs->present = (flags & DESC_P_MASK) != 0;
316
    lhs->dpl = rhs->selector & 3;
317
    lhs->db = (flags >> DESC_B_SHIFT) & 1;
318
    lhs->s = (flags & DESC_S_MASK) != 0;
319
    lhs->l = (flags >> DESC_L_SHIFT) & 1;
320
    lhs->g = (flags & DESC_G_MASK) != 0;
321
    lhs->avl = (flags & DESC_AVL_MASK) != 0;
322
    lhs->unusable = 0;
323
}
324

    
325
static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
326
{
327
    lhs->selector = rhs->selector;
328
    lhs->base = rhs->base;
329
    lhs->limit = rhs->limit;
330
    lhs->flags =
331
        (rhs->type << DESC_TYPE_SHIFT)
332
        | (rhs->present * DESC_P_MASK)
333
        | (rhs->dpl << DESC_DPL_SHIFT)
334
        | (rhs->db << DESC_B_SHIFT)
335
        | (rhs->s * DESC_S_MASK)
336
        | (rhs->l << DESC_L_SHIFT)
337
        | (rhs->g * DESC_G_MASK)
338
        | (rhs->avl * DESC_AVL_MASK);
339
}
340

    
341
static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
342
{
343
    if (set)
344
        *kvm_reg = *qemu_reg;
345
    else
346
        *qemu_reg = *kvm_reg;
347
}
348

    
349
static int kvm_getput_regs(CPUState *env, int set)
350
{
351
    struct kvm_regs regs;
352
    int ret = 0;
353

    
354
    if (!set) {
355
        ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
356
        if (ret < 0)
357
            return ret;
358
    }
359

    
360
    kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
361
    kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
362
    kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
363
    kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
364
    kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
365
    kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
366
    kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
367
    kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
368
#ifdef TARGET_X86_64
369
    kvm_getput_reg(&regs.r8, &env->regs[8], set);
370
    kvm_getput_reg(&regs.r9, &env->regs[9], set);
371
    kvm_getput_reg(&regs.r10, &env->regs[10], set);
372
    kvm_getput_reg(&regs.r11, &env->regs[11], set);
373
    kvm_getput_reg(&regs.r12, &env->regs[12], set);
374
    kvm_getput_reg(&regs.r13, &env->regs[13], set);
375
    kvm_getput_reg(&regs.r14, &env->regs[14], set);
376
    kvm_getput_reg(&regs.r15, &env->regs[15], set);
377
#endif
378

    
379
    kvm_getput_reg(&regs.rflags, &env->eflags, set);
380
    kvm_getput_reg(&regs.rip, &env->eip, set);
381

    
382
    if (set)
383
        ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
384

    
385
    return ret;
386
}
387

    
388
static int kvm_put_fpu(CPUState *env)
389
{
390
    struct kvm_fpu fpu;
391
    int i;
392

    
393
    memset(&fpu, 0, sizeof fpu);
394
    fpu.fsw = env->fpus & ~(7 << 11);
395
    fpu.fsw |= (env->fpstt & 7) << 11;
396
    fpu.fcw = env->fpuc;
397
    for (i = 0; i < 8; ++i)
398
        fpu.ftwx |= (!env->fptags[i]) << i;
399
    memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
400
    memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
401
    fpu.mxcsr = env->mxcsr;
402

    
403
    return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
404
}
405

    
406
static int kvm_put_sregs(CPUState *env)
407
{
408
    struct kvm_sregs sregs;
409

    
410
    memcpy(sregs.interrupt_bitmap,
411
           env->interrupt_bitmap,
412
           sizeof(sregs.interrupt_bitmap));
413

    
414
    if ((env->eflags & VM_MASK)) {
415
            set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
416
            set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
417
            set_v8086_seg(&sregs.es, &env->segs[R_ES]);
418
            set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
419
            set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
420
            set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
421
    } else {
422
            set_seg(&sregs.cs, &env->segs[R_CS]);
423
            set_seg(&sregs.ds, &env->segs[R_DS]);
424
            set_seg(&sregs.es, &env->segs[R_ES]);
425
            set_seg(&sregs.fs, &env->segs[R_FS]);
426
            set_seg(&sregs.gs, &env->segs[R_GS]);
427
            set_seg(&sregs.ss, &env->segs[R_SS]);
428

    
429
            if (env->cr[0] & CR0_PE_MASK) {
430
                /* force ss cpl to cs cpl */
431
                sregs.ss.selector = (sregs.ss.selector & ~3) |
432
                        (sregs.cs.selector & 3);
433
                sregs.ss.dpl = sregs.ss.selector & 3;
434
            }
435
    }
436

    
437
    set_seg(&sregs.tr, &env->tr);
438
    set_seg(&sregs.ldt, &env->ldt);
439

    
440
    sregs.idt.limit = env->idt.limit;
441
    sregs.idt.base = env->idt.base;
442
    sregs.gdt.limit = env->gdt.limit;
443
    sregs.gdt.base = env->gdt.base;
444

    
445
    sregs.cr0 = env->cr[0];
446
    sregs.cr2 = env->cr[2];
447
    sregs.cr3 = env->cr[3];
448
    sregs.cr4 = env->cr[4];
449

    
450
    sregs.cr8 = cpu_get_apic_tpr(env);
451
    sregs.apic_base = cpu_get_apic_base(env);
452

    
453
    sregs.efer = env->efer;
454

    
455
    return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
456
}
457

    
458
static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
459
                              uint32_t index, uint64_t value)
460
{
461
    entry->index = index;
462
    entry->data = value;
463
}
464

    
465
static int kvm_put_msrs(CPUState *env)
466
{
467
    struct {
468
        struct kvm_msrs info;
469
        struct kvm_msr_entry entries[100];
470
    } msr_data;
471
    struct kvm_msr_entry *msrs = msr_data.entries;
472
    int n = 0;
473

    
474
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
475
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
476
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
477
    if (kvm_has_msr_star(env))
478
        kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
479
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
480
#ifdef TARGET_X86_64
481
    /* FIXME if lm capable */
482
    kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
483
    kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
484
    kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
485
    kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
486
#endif
487
    msr_data.info.nmsrs = n;
488

    
489
    return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
490

    
491
}
492

    
493

    
494
static int kvm_get_fpu(CPUState *env)
495
{
496
    struct kvm_fpu fpu;
497
    int i, ret;
498

    
499
    ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
500
    if (ret < 0)
501
        return ret;
502

    
503
    env->fpstt = (fpu.fsw >> 11) & 7;
504
    env->fpus = fpu.fsw;
505
    env->fpuc = fpu.fcw;
506
    for (i = 0; i < 8; ++i)
507
        env->fptags[i] = !((fpu.ftwx >> i) & 1);
508
    memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
509
    memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
510
    env->mxcsr = fpu.mxcsr;
511

    
512
    return 0;
513
}
514

    
515
static int kvm_get_sregs(CPUState *env)
516
{
517
    struct kvm_sregs sregs;
518
    uint32_t hflags;
519
    int ret;
520

    
521
    ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
522
    if (ret < 0)
523
        return ret;
524

    
525
    memcpy(env->interrupt_bitmap, 
526
           sregs.interrupt_bitmap,
527
           sizeof(sregs.interrupt_bitmap));
528

    
529
    get_seg(&env->segs[R_CS], &sregs.cs);
530
    get_seg(&env->segs[R_DS], &sregs.ds);
531
    get_seg(&env->segs[R_ES], &sregs.es);
532
    get_seg(&env->segs[R_FS], &sregs.fs);
533
    get_seg(&env->segs[R_GS], &sregs.gs);
534
    get_seg(&env->segs[R_SS], &sregs.ss);
535

    
536
    get_seg(&env->tr, &sregs.tr);
537
    get_seg(&env->ldt, &sregs.ldt);
538

    
539
    env->idt.limit = sregs.idt.limit;
540
    env->idt.base = sregs.idt.base;
541
    env->gdt.limit = sregs.gdt.limit;
542
    env->gdt.base = sregs.gdt.base;
543

    
544
    env->cr[0] = sregs.cr0;
545
    env->cr[2] = sregs.cr2;
546
    env->cr[3] = sregs.cr3;
547
    env->cr[4] = sregs.cr4;
548

    
549
    cpu_set_apic_base(env, sregs.apic_base);
550

    
551
    env->efer = sregs.efer;
552
    //cpu_set_apic_tpr(env, sregs.cr8);
553

    
554
#define HFLAG_COPY_MASK ~( \
555
                        HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
556
                        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
557
                        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
558
                        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
559

    
560

    
561

    
562
    hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
563
    hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
564
    hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
565
            (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
566
    hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
567
    hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
568
            (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
569

    
570
    if (env->efer & MSR_EFER_LMA) {
571
        hflags |= HF_LMA_MASK;
572
    }
573

    
574
    if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
575
        hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
576
    } else {
577
        hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
578
                (DESC_B_SHIFT - HF_CS32_SHIFT);
579
        hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
580
                (DESC_B_SHIFT - HF_SS32_SHIFT);
581
        if (!(env->cr[0] & CR0_PE_MASK) ||
582
                   (env->eflags & VM_MASK) ||
583
                   !(hflags & HF_CS32_MASK)) {
584
                hflags |= HF_ADDSEG_MASK;
585
            } else {
586
                hflags |= ((env->segs[R_DS].base |
587
                                env->segs[R_ES].base |
588
                                env->segs[R_SS].base) != 0) <<
589
                    HF_ADDSEG_SHIFT;
590
            }
591
    }
592
    env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
593

    
594
    return 0;
595
}
596

    
597
static int kvm_get_msrs(CPUState *env)
598
{
599
    struct {
600
        struct kvm_msrs info;
601
        struct kvm_msr_entry entries[100];
602
    } msr_data;
603
    struct kvm_msr_entry *msrs = msr_data.entries;
604
    int ret, i, n;
605

    
606
    n = 0;
607
    msrs[n++].index = MSR_IA32_SYSENTER_CS;
608
    msrs[n++].index = MSR_IA32_SYSENTER_ESP;
609
    msrs[n++].index = MSR_IA32_SYSENTER_EIP;
610
    if (kvm_has_msr_star(env))
611
        msrs[n++].index = MSR_STAR;
612
    msrs[n++].index = MSR_IA32_TSC;
613
#ifdef TARGET_X86_64
614
    /* FIXME lm_capable_kernel */
615
    msrs[n++].index = MSR_CSTAR;
616
    msrs[n++].index = MSR_KERNELGSBASE;
617
    msrs[n++].index = MSR_FMASK;
618
    msrs[n++].index = MSR_LSTAR;
619
#endif
620
    msr_data.info.nmsrs = n;
621
    ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
622
    if (ret < 0)
623
        return ret;
624

    
625
    for (i = 0; i < ret; i++) {
626
        switch (msrs[i].index) {
627
        case MSR_IA32_SYSENTER_CS:
628
            env->sysenter_cs = msrs[i].data;
629
            break;
630
        case MSR_IA32_SYSENTER_ESP:
631
            env->sysenter_esp = msrs[i].data;
632
            break;
633
        case MSR_IA32_SYSENTER_EIP:
634
            env->sysenter_eip = msrs[i].data;
635
            break;
636
        case MSR_STAR:
637
            env->star = msrs[i].data;
638
            break;
639
#ifdef TARGET_X86_64
640
        case MSR_CSTAR:
641
            env->cstar = msrs[i].data;
642
            break;
643
        case MSR_KERNELGSBASE:
644
            env->kernelgsbase = msrs[i].data;
645
            break;
646
        case MSR_FMASK:
647
            env->fmask = msrs[i].data;
648
            break;
649
        case MSR_LSTAR:
650
            env->lstar = msrs[i].data;
651
            break;
652
#endif
653
        case MSR_IA32_TSC:
654
            env->tsc = msrs[i].data;
655
            break;
656
        }
657
    }
658

    
659
    return 0;
660
}
661

    
662
int kvm_arch_put_registers(CPUState *env)
663
{
664
    int ret;
665

    
666
    ret = kvm_getput_regs(env, 1);
667
    if (ret < 0)
668
        return ret;
669

    
670
    ret = kvm_put_fpu(env);
671
    if (ret < 0)
672
        return ret;
673

    
674
    ret = kvm_put_sregs(env);
675
    if (ret < 0)
676
        return ret;
677

    
678
    ret = kvm_put_msrs(env);
679
    if (ret < 0)
680
        return ret;
681

    
682
    ret = kvm_put_mp_state(env);
683
    if (ret < 0)
684
        return ret;
685

    
686
    ret = kvm_get_mp_state(env);
687
    if (ret < 0)
688
        return ret;
689

    
690
    return 0;
691
}
692

    
693
int kvm_arch_get_registers(CPUState *env)
694
{
695
    int ret;
696

    
697
    ret = kvm_getput_regs(env, 0);
698
    if (ret < 0)
699
        return ret;
700

    
701
    ret = kvm_get_fpu(env);
702
    if (ret < 0)
703
        return ret;
704

    
705
    ret = kvm_get_sregs(env);
706
    if (ret < 0)
707
        return ret;
708

    
709
    ret = kvm_get_msrs(env);
710
    if (ret < 0)
711
        return ret;
712

    
713
    return 0;
714
}
715

    
716
int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
717
{
718
    /* Try to inject an interrupt if the guest can accept it */
719
    if (run->ready_for_interrupt_injection &&
720
        (env->interrupt_request & CPU_INTERRUPT_HARD) &&
721
        (env->eflags & IF_MASK)) {
722
        int irq;
723

    
724
        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
725
        irq = cpu_get_pic_interrupt(env);
726
        if (irq >= 0) {
727
            struct kvm_interrupt intr;
728
            intr.irq = irq;
729
            /* FIXME: errors */
730
            dprintf("injected interrupt %d\n", irq);
731
            kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
732
        }
733
    }
734

    
735
    /* If we have an interrupt but the guest is not ready to receive an
736
     * interrupt, request an interrupt window exit.  This will
737
     * cause a return to userspace as soon as the guest is ready to
738
     * receive interrupts. */
739
    if ((env->interrupt_request & CPU_INTERRUPT_HARD))
740
        run->request_interrupt_window = 1;
741
    else
742
        run->request_interrupt_window = 0;
743

    
744
    dprintf("setting tpr\n");
745
    run->cr8 = cpu_get_apic_tpr(env);
746

    
747
    return 0;
748
}
749

    
750
int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
751
{
752
    if (run->if_flag)
753
        env->eflags |= IF_MASK;
754
    else
755
        env->eflags &= ~IF_MASK;
756
    
757
    cpu_set_apic_tpr(env, run->cr8);
758
    cpu_set_apic_base(env, run->apic_base);
759

    
760
    return 0;
761
}
762

    
763
static int kvm_handle_halt(CPUState *env)
764
{
765
    if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
766
          (env->eflags & IF_MASK)) &&
767
        !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
768
        env->halted = 1;
769
        env->exception_index = EXCP_HLT;
770
        return 0;
771
    }
772

    
773
    return 1;
774
}
775

    
776
int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
777
{
778
    int ret = 0;
779

    
780
    switch (run->exit_reason) {
781
    case KVM_EXIT_HLT:
782
        dprintf("handle_hlt\n");
783
        ret = kvm_handle_halt(env);
784
        break;
785
    }
786

    
787
    return ret;
788
}
789

    
790
#ifdef KVM_CAP_SET_GUEST_DEBUG
791
int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
792
{
793
    const static uint8_t int3 = 0xcc;
794

    
795
    if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
796
        cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
797
        return -EINVAL;
798
    return 0;
799
}
800

    
801
int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
802
{
803
    uint8_t int3;
804

    
805
    if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
806
        cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
807
        return -EINVAL;
808
    return 0;
809
}
810

    
811
static struct {
812
    target_ulong addr;
813
    int len;
814
    int type;
815
} hw_breakpoint[4];
816

    
817
static int nb_hw_breakpoint;
818

    
819
static int find_hw_breakpoint(target_ulong addr, int len, int type)
820
{
821
    int n;
822

    
823
    for (n = 0; n < nb_hw_breakpoint; n++)
824
        if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
825
            (hw_breakpoint[n].len == len || len == -1))
826
            return n;
827
    return -1;
828
}
829

    
830
int kvm_arch_insert_hw_breakpoint(target_ulong addr,
831
                                  target_ulong len, int type)
832
{
833
    switch (type) {
834
    case GDB_BREAKPOINT_HW:
835
        len = 1;
836
        break;
837
    case GDB_WATCHPOINT_WRITE:
838
    case GDB_WATCHPOINT_ACCESS:
839
        switch (len) {
840
        case 1:
841
            break;
842
        case 2:
843
        case 4:
844
        case 8:
845
            if (addr & (len - 1))
846
                return -EINVAL;
847
            break;
848
        default:
849
            return -EINVAL;
850
        }
851
        break;
852
    default:
853
        return -ENOSYS;
854
    }
855

    
856
    if (nb_hw_breakpoint == 4)
857
        return -ENOBUFS;
858

    
859
    if (find_hw_breakpoint(addr, len, type) >= 0)
860
        return -EEXIST;
861

    
862
    hw_breakpoint[nb_hw_breakpoint].addr = addr;
863
    hw_breakpoint[nb_hw_breakpoint].len = len;
864
    hw_breakpoint[nb_hw_breakpoint].type = type;
865
    nb_hw_breakpoint++;
866

    
867
    return 0;
868
}
869

    
870
int kvm_arch_remove_hw_breakpoint(target_ulong addr,
871
                                  target_ulong len, int type)
872
{
873
    int n;
874

    
875
    n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
876
    if (n < 0)
877
        return -ENOENT;
878

    
879
    nb_hw_breakpoint--;
880
    hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
881

    
882
    return 0;
883
}
884

    
885
void kvm_arch_remove_all_hw_breakpoints(void)
886
{
887
    nb_hw_breakpoint = 0;
888
}
889

    
890
static CPUWatchpoint hw_watchpoint;
891

    
892
int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
893
{
894
    int handle = 0;
895
    int n;
896

    
897
    if (arch_info->exception == 1) {
898
        if (arch_info->dr6 & (1 << 14)) {
899
            if (cpu_single_env->singlestep_enabled)
900
                handle = 1;
901
        } else {
902
            for (n = 0; n < 4; n++)
903
                if (arch_info->dr6 & (1 << n))
904
                    switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
905
                    case 0x0:
906
                        handle = 1;
907
                        break;
908
                    case 0x1:
909
                        handle = 1;
910
                        cpu_single_env->watchpoint_hit = &hw_watchpoint;
911
                        hw_watchpoint.vaddr = hw_breakpoint[n].addr;
912
                        hw_watchpoint.flags = BP_MEM_WRITE;
913
                        break;
914
                    case 0x3:
915
                        handle = 1;
916
                        cpu_single_env->watchpoint_hit = &hw_watchpoint;
917
                        hw_watchpoint.vaddr = hw_breakpoint[n].addr;
918
                        hw_watchpoint.flags = BP_MEM_ACCESS;
919
                        break;
920
                    }
921
        }
922
    } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
923
        handle = 1;
924

    
925
    if (!handle)
926
        kvm_update_guest_debug(cpu_single_env,
927
                        (arch_info->exception == 1) ?
928
                        KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
929

    
930
    return handle;
931
}
932

    
933
void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
934
{
935
    const uint8_t type_code[] = {
936
        [GDB_BREAKPOINT_HW] = 0x0,
937
        [GDB_WATCHPOINT_WRITE] = 0x1,
938
        [GDB_WATCHPOINT_ACCESS] = 0x3
939
    };
940
    const uint8_t len_code[] = {
941
        [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
942
    };
943
    int n;
944

    
945
    if (kvm_sw_breakpoints_active(env))
946
        dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
947

    
948
    if (nb_hw_breakpoint > 0) {
949
        dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
950
        dbg->arch.debugreg[7] = 0x0600;
951
        for (n = 0; n < nb_hw_breakpoint; n++) {
952
            dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
953
            dbg->arch.debugreg[7] |= (2 << (n * 2)) |
954
                (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
955
                (len_code[hw_breakpoint[n].len] << (18 + n*4));
956
        }
957
    }
958
}
959
#endif /* KVM_CAP_SET_GUEST_DEBUG */