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/*
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 *  PPC emulation helpers for qemu.
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 * 
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 *  Copyright (c) 2003 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <sys/mman.h>
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#include "exec.h"
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#if defined (USE_OPEN_FIRMWARE)
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#include "of.h"
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#endif
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//#define DEBUG_MMU
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//#define DEBUG_BATS
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//#define DEBUG_EXCEPTIONS
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extern FILE *logfile, *stderr;
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void exit (int);
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void abort (void);
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int phys_ram_size;
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int phys_ram_fd;
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uint8_t *phys_ram_base;
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void cpu_loop_exit(void)
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{
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    longjmp(env->jmp_env, 1);
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}
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void do_process_exceptions (void)
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{
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    cpu_loop_exit();
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}
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int check_exception_state (CPUState *env)
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{
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    int i;
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    /* Process PPC exceptions */
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    for (i = 1; i  < EXCP_PPC_MAX; i++) {
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        if (env->exceptions & (1 << i)) {
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            switch (i) {
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            case EXCP_EXTERNAL:
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            case EXCP_DECR:
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                if (msr_ee == 0)
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                    return 0;
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                break;
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            case EXCP_PROGRAM:
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                if (env->errors[EXCP_PROGRAM] == EXCP_FP &&
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                    msr_fe0 == 0 && msr_fe1 == 0)
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                    return 0;
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                break;
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            default:
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                break;
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            }
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            env->exception_index = i;
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            env->error_code = env->errors[i];
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            return 1;
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        }
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    }
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    return 0;
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}
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/*****************************************************************************/
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/* PPC MMU emulation */
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/* Perform BAT hit & translation */
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static int get_bat (CPUState *env, uint32_t *real, int *prot,
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                    uint32_t virtual, int rw, int type)
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{
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    uint32_t *BATlt, *BATut, *BATu, *BATl;
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    uint32_t base, BEPIl, BEPIu, bl;
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    int i;
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    int ret = -1;
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#if defined (DEBUG_BATS)
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    if (loglevel > 0) {
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        fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
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               type == ACCESS_CODE ? 'I' : 'D', virtual);
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    }
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    printf("%s: %cBAT v 0x%08x\n", __func__,
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           type == ACCESS_CODE ? 'I' : 'D', virtual);
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#endif
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    switch (type) {
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    case ACCESS_CODE:
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        BATlt = env->IBAT[1];
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        BATut = env->IBAT[0];
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        break;
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    default:
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        BATlt = env->DBAT[1];
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        BATut = env->DBAT[0];
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        break;
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    }
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#if defined (DEBUG_BATS)
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    if (loglevel > 0) {
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        fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
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               type == ACCESS_CODE ? 'I' : 'D', virtual);
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    }
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    printf("%s...: %cBAT v 0x%08x\n", __func__,
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           type == ACCESS_CODE ? 'I' : 'D', virtual);
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#endif
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    base = virtual & 0xFFFC0000;
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    for (i = 0; i < 4; i++) {
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        BATu = &BATut[i];
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        BATl = &BATlt[i];
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        BEPIu = *BATu & 0xF0000000;
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        BEPIl = *BATu & 0x0FFE0000;
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        bl = (*BATu & 0x00001FFC) << 15;
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#if defined (DEBUG_BATS)
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        if (loglevel > 0) {
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            fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
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                    __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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                    *BATu, *BATl);
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        } else {
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            printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
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                   __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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                   *BATu, *BATl);
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        }
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#endif
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        if ((virtual & 0xF0000000) == BEPIu &&
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            ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
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            /* BAT matches */
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            if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
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                (msr_pr == 1 && (*BATu & 0x00000001))) {
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                /* Get physical address */
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                *real = (*BATl & 0xF0000000) |
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                    ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
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                    (virtual & 0x0001FFFF);
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                if (*BATl & 0x00000001)
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                    *prot = PROT_READ;
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                if (*BATl & 0x00000002)
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                    *prot = PROT_WRITE | PROT_READ;
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#if defined (DEBUG_BATS)
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                if (loglevel > 0) {
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                    fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
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                            i, *real, *prot & PROT_READ ? 'R' : '-',
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                            *prot & PROT_WRITE ? 'W' : '-');
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                } else {
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                    printf("BAT %d match: 0x%08x => 0x%08x prot=%c%c\n",
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                           i, virtual, *real, *prot & PROT_READ ? 'R' : '-',
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                           *prot & PROT_WRITE ? 'W' : '-');
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                }
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#endif
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                ret = 0;
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                break;
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            }
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        }
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    }
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    if (ret < 0) {
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#if defined (DEBUG_BATS)
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        printf("no BAT match for 0x%08x:\n", virtual);
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        for (i = 0; i < 4; i++) {
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            BATu = &BATut[i];
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            BATl = &BATlt[i];
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            BEPIu = *BATu & 0xF0000000;
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            BEPIl = *BATu & 0x0FFE0000;
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            bl = (*BATu & 0x00001FFC) << 15;
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            printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
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                   "0x%08x 0x%08x 0x%08x\n",
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                   __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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                   *BATu, *BATl, BEPIu, BEPIl, bl);
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        }
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#endif
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        env->spr[DAR] = virtual;
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    }
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    /* No hit */
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    return ret;
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}
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/* PTE table lookup */
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static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
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                     int h, int key, int rw)
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{
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    uint32_t pte0, pte1, keep = 0;
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    int i, good = -1, store = 0;
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    int ret = -1; /* No entry found */
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    for (i = 0; i < 8; i++) {
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        pte0 = ldl_raw((void *)((uint32_t)phys_ram_base + base + (i * 8)));
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        pte1 =  ldl_raw((void *)((uint32_t)phys_ram_base + base + (i * 8) + 4));
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#if defined (DEBUG_MMU)
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        printf("Load pte from 0x%08x => 0x%08x 0x%08x\n", base + (i * 8),
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               pte0, pte1);
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#endif
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        /* Check validity and table match */
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        if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
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#if defined (DEBUG_MMU)
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            printf("PTE is valid and table matches... compare 0x%08x:%08x\n",
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                   pte0 & 0x7FFFFFBF, va);
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#endif
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            /* Check vsid & api */
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            if ((pte0 & 0x7FFFFFBF) == va) {
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#if defined (DEBUG_MMU)
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                printf("PTE match !\n");
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#endif
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                if (good == -1) {
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                    good = i;
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                    keep = pte1;
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                } else {
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                    /* All matches should have equal RPN, WIMG & PP */
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                    if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
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                        printf("Bad RPN/WIMG/PP\n");
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                        return -1;
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                    }
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                }
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                /* Check access rights */
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                if (key == 0) {
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                    *prot = PROT_READ;
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                    if ((pte1 & 0x00000003) != 0x3)
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                        *prot |= PROT_WRITE;
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                } else {
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                    switch (pte1 & 0x00000003) {
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                    case 0x0:
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                        *prot = 0;
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                        break;
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                    case 0x1:
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                    case 0x3:
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                        *prot = PROT_READ;
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                        break;
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                    case 0x2:
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                        *prot = PROT_READ | PROT_WRITE;
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                        break;
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                    }
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                }
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                if ((rw == 0 && *prot != 0) ||
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                    (rw == 1 && (*prot & PROT_WRITE))) {
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#if defined (DEBUG_MMU)
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                    printf("PTE access granted !\n");
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#endif
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                    good = i;
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                    keep = pte1;
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                    ret = 0;
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                } else if (ret == -1) {
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                    ret = -2; /* Access right violation */
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#if defined (DEBUG_MMU)
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                    printf("PTE access rejected\n");
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#endif
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                }
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            }
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        }
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    }
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    if (good != -1) {
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        *RPN = keep & 0xFFFFF000;
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#if defined (DEBUG_MMU)
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        printf("found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
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               *RPN, *prot, ret);
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#endif
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        /* Update page flags */
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        if (!(keep & 0x00000100)) {
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            keep |= 0x00000100;
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            store = 1;
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        }
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        if (rw) {
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            if (!(keep & 0x00000080)) {
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                keep |= 0x00000080;
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                store = 1;
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            }
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        }
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        if (store)
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            stl_raw((void *)(base + (good * 2) + 1), keep);
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    }
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    return ret;
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}
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static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
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{
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    return (sdr1 & 0xFFFF0000) | (hash & mask);
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}
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/* Perform segment based translation */
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static int get_segment (CPUState *env, uint32_t *real, int *prot,
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                        uint32_t virtual, int rw, int type)
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{
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    uint32_t pg_addr, sdr, ptem, vsid, pgidx;
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    uint32_t hash, mask;
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    uint32_t sr;
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    int key;
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    int ret = -1, ret2;
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    sr = env->sr[virtual >> 28];
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#if defined (DEBUG_MMU)
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    printf("Check segment v=0x%08x %d 0x%08x nip=0x%08x lr=0x%08x ir=%d dr=%d "
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           "pr=%d t=%d\n", virtual, virtual >> 28, sr, env->nip,
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           env->lr, msr_ir, msr_dr, msr_pr, type);
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#endif
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    key = ((sr & 0x20000000) && msr_pr == 1) ||
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        ((sr & 0x40000000) && msr_pr == 0) ? 1 : 0;
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    if ((sr & 0x80000000) == 0) {
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#if defined (DEBUG_MMU)
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        printf("pte segment: key=%d n=0x%08x\n", key, sr & 0x10000000);
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#endif
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        /* Check if instruction fetch is allowed, if needed */
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        if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
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            /* Page address translation */
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            vsid = sr & 0x00FFFFFF;
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            pgidx = (virtual >> 12) & 0xFFFF;
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            sdr = env->spr[SDR1];
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            hash = ((vsid ^ pgidx) & 0x07FFFF) << 6;
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            mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
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            pg_addr = get_pgaddr(sdr, hash, mask);
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            ptem = (vsid << 7) | (pgidx >> 10);
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#if defined (DEBUG_MMU)
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            printf("0 sdr1=0x%08x vsid=0x%06x api=0x%04x hash=0x%07x "
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                   "pg_addr=0x%08x\n", sdr, vsid, pgidx, hash, pg_addr);
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#endif
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            /* Primary table lookup */
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            ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
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            if (ret < 0) {
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                /* Secondary table lookup */
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                hash = (~hash) & 0x01FFFFC0;
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                pg_addr = get_pgaddr(sdr, hash, mask);
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#if defined (DEBUG_MMU)
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                printf("1 sdr1=0x%08x vsid=0x%06x api=0x%04x hash=0x%05x "
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                       "pg_addr=0x%08x\n", sdr, vsid, pgidx, hash, pg_addr);
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#endif
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                ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
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                if (ret2 != -1)
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                    ret = ret2;
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            }
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            if (ret != -1)
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                *real |= (virtual & 0x00000FFF);
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            if (ret == -2 && type == ACCESS_CODE && (sr & 0x10000000))
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                ret = -3;
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        } else {
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#if defined (DEBUG_MMU)
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            printf("No access allowed\n");
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#endif
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        }
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    } else {
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#if defined (DEBUG_MMU)
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        printf("direct store...\n");
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#endif
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        /* Direct-store segment : absolutely *BUGGY* for now */
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        switch (type) {
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        case ACCESS_INT:
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            /* Integer load/store : only access allowed */
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            break;
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        case ACCESS_CODE:
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            /* No code fetch is allowed in direct-store areas */
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            return -4;
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        case ACCESS_FLOAT:
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            /* Floating point load/store */
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            return -4;
359 9a64fbe4 bellard
        case ACCESS_RES:
360 9a64fbe4 bellard
            /* lwarx, ldarx or srwcx. */
361 9a64fbe4 bellard
            return -4;
362 9a64fbe4 bellard
        case ACCESS_CACHE:
363 9a64fbe4 bellard
            /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
364 9a64fbe4 bellard
            /* Should make the instruction do no-op.
365 9a64fbe4 bellard
             * As it already do no-op, it's quite easy :-)
366 9a64fbe4 bellard
             */
367 9a64fbe4 bellard
            *real = virtual;
368 9a64fbe4 bellard
            return 0;
369 9a64fbe4 bellard
        case ACCESS_EXT:
370 9a64fbe4 bellard
            /* eciwx or ecowx */
371 9a64fbe4 bellard
            return -4;
372 9a64fbe4 bellard
        default:
373 9a64fbe4 bellard
            if (logfile) {
374 9a64fbe4 bellard
                fprintf(logfile, "ERROR: instruction should not need "
375 9a64fbe4 bellard
                        "address translation\n");
376 9a64fbe4 bellard
            }
377 9a64fbe4 bellard
            printf("ERROR: instruction should not need "
378 9a64fbe4 bellard
                   "address translation\n");
379 9a64fbe4 bellard
            return -4;
380 9a64fbe4 bellard
        }
381 9a64fbe4 bellard
        if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
382 9a64fbe4 bellard
            *real = virtual;
383 9a64fbe4 bellard
            ret = 2;
384 9a64fbe4 bellard
        } else {
385 9a64fbe4 bellard
            ret = -2;
386 9a64fbe4 bellard
        }
387 79aceca5 bellard
    }
388 9a64fbe4 bellard
389 9a64fbe4 bellard
    return ret;
390 79aceca5 bellard
}
391 79aceca5 bellard
392 9a64fbe4 bellard
int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
393 9a64fbe4 bellard
                          uint32_t address, int rw, int access_type)
394 9a64fbe4 bellard
{
395 9a64fbe4 bellard
    int ret;
396 9a64fbe4 bellard
397 9a64fbe4 bellard
    if (loglevel > 0) {
398 9a64fbe4 bellard
        fprintf(logfile, "%s\n", __func__);
399 9a64fbe4 bellard
    }
400 9a64fbe4 bellard
    if ((access_type == ACCESS_CODE && msr_ir == 0) || msr_dr == 0) {
401 9a64fbe4 bellard
        /* No address translation */
402 9a64fbe4 bellard
        *physical = address;
403 9a64fbe4 bellard
        *prot = PROT_READ | PROT_WRITE;
404 9a64fbe4 bellard
        ret = 0;
405 9a64fbe4 bellard
    } else {
406 9a64fbe4 bellard
        /* Try to find a BAT */
407 9a64fbe4 bellard
        ret = get_bat(env, physical, prot, address, rw, access_type);
408 9a64fbe4 bellard
        if (ret < 0) {
409 9a64fbe4 bellard
            /* We didn't match any BAT entry */
410 9a64fbe4 bellard
            ret = get_segment(env, physical, prot, address, rw, access_type);
411 9a64fbe4 bellard
        }
412 9a64fbe4 bellard
    }
413 9a64fbe4 bellard
    
414 9a64fbe4 bellard
    return ret;
415 9a64fbe4 bellard
}
416 9a64fbe4 bellard
417 9a64fbe4 bellard
418 9a64fbe4 bellard
#if !defined(CONFIG_USER_ONLY) 
419 9a64fbe4 bellard
420 9a64fbe4 bellard
#define MMUSUFFIX _mmu
421 9a64fbe4 bellard
#define GETPC() (__builtin_return_address(0))
422 9a64fbe4 bellard
423 9a64fbe4 bellard
#define SHIFT 0
424 9a64fbe4 bellard
#include "softmmu_template.h"
425 9a64fbe4 bellard
426 9a64fbe4 bellard
#define SHIFT 1
427 9a64fbe4 bellard
#include "softmmu_template.h"
428 9a64fbe4 bellard
429 9a64fbe4 bellard
#define SHIFT 2
430 9a64fbe4 bellard
#include "softmmu_template.h"
431 9a64fbe4 bellard
432 9a64fbe4 bellard
#define SHIFT 3
433 9a64fbe4 bellard
#include "softmmu_template.h"
434 9a64fbe4 bellard
435 9a64fbe4 bellard
/* try to fill the TLB and return an exception if error. If retaddr is
436 9a64fbe4 bellard
   NULL, it means that the function was called in C code (i.e. not
437 9a64fbe4 bellard
   from generated code or from helper.c) */
438 9a64fbe4 bellard
/* XXX: fix it to restore all registers */
439 9a64fbe4 bellard
void tlb_fill(unsigned long addr, int is_write, int flags, void *retaddr)
440 9a64fbe4 bellard
{
441 9a64fbe4 bellard
    TranslationBlock *tb;
442 9a64fbe4 bellard
    int ret, is_user;
443 9a64fbe4 bellard
    unsigned long pc;
444 9a64fbe4 bellard
    CPUState *saved_env;
445 9a64fbe4 bellard
446 9a64fbe4 bellard
    /* XXX: hack to restore env in all cases, even if not called from
447 9a64fbe4 bellard
       generated code */
448 9a64fbe4 bellard
    saved_env = env;
449 9a64fbe4 bellard
    env = cpu_single_env;
450 9a64fbe4 bellard
    is_user = flags & 0x01;
451 9a64fbe4 bellard
    {
452 9a64fbe4 bellard
        unsigned long tlb_addrr, tlb_addrw;
453 9a64fbe4 bellard
        int index;
454 9a64fbe4 bellard
        index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
455 9a64fbe4 bellard
        tlb_addrr = env->tlb_read[is_user][index].address;
456 9a64fbe4 bellard
        tlb_addrw = env->tlb_write[is_user][index].address;
457 9a64fbe4 bellard
#if 0
458 9a64fbe4 bellard
        printf("%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
459 9a64fbe4 bellard
               "(0x%08lx 0x%08lx)\n", __func__, env,
460 9a64fbe4 bellard
               &env->tlb_read[is_user][index], index, addr,
461 9a64fbe4 bellard
               tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
462 9a64fbe4 bellard
               tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
463 9a64fbe4 bellard
#endif
464 9a64fbe4 bellard
    }
465 9a64fbe4 bellard
    ret = cpu_handle_mmu_fault(env, addr, is_write, flags, 1);
466 9a64fbe4 bellard
    if (ret) {
467 9a64fbe4 bellard
        if (retaddr) {
468 9a64fbe4 bellard
            /* now we have a real cpu fault */
469 9a64fbe4 bellard
            pc = (unsigned long)retaddr;
470 9a64fbe4 bellard
            tb = tb_find_pc(pc);
471 9a64fbe4 bellard
            if (tb) {
472 9a64fbe4 bellard
                /* the PC is inside the translated code. It means that we have
473 9a64fbe4 bellard
                   a virtual CPU fault */
474 9a64fbe4 bellard
                cpu_restore_state(tb, env, pc);
475 9a64fbe4 bellard
            }
476 9a64fbe4 bellard
        }
477 9a64fbe4 bellard
        do_queue_exception_err(env->exception_index, env->error_code);
478 9a64fbe4 bellard
        do_process_exceptions();
479 9a64fbe4 bellard
    }
480 9a64fbe4 bellard
    {
481 9a64fbe4 bellard
        unsigned long tlb_addrr, tlb_addrw;
482 9a64fbe4 bellard
        int index;
483 9a64fbe4 bellard
        index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
484 9a64fbe4 bellard
        tlb_addrr = env->tlb_read[is_user][index].address;
485 9a64fbe4 bellard
        tlb_addrw = env->tlb_write[is_user][index].address;
486 9a64fbe4 bellard
#if 0
487 9a64fbe4 bellard
        printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
488 9a64fbe4 bellard
               "(0x%08lx 0x%08lx)\n", __func__, env,
489 9a64fbe4 bellard
               &env->tlb_read[is_user][index], index, addr,
490 9a64fbe4 bellard
               tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
491 9a64fbe4 bellard
               tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
492 9a64fbe4 bellard
#endif
493 9a64fbe4 bellard
    }
494 9a64fbe4 bellard
    env = saved_env;
495 9a64fbe4 bellard
}
496 9a64fbe4 bellard
497 9a64fbe4 bellard
void cpu_ppc_init_mmu(CPUPPCState *env)
498 9a64fbe4 bellard
{
499 9a64fbe4 bellard
    /* Nothing to do: all translation are disabled */
500 9a64fbe4 bellard
}
501 9a64fbe4 bellard
#endif
502 9a64fbe4 bellard
503 9a64fbe4 bellard
/* Perform address translation */
504 9a64fbe4 bellard
int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
505 9a64fbe4 bellard
                              int flags, int is_softmmu)
506 9a64fbe4 bellard
{
507 9a64fbe4 bellard
    uint32_t physical;
508 9a64fbe4 bellard
    int prot;
509 9a64fbe4 bellard
    int exception = 0, error_code = 0;
510 9a64fbe4 bellard
    int is_user, access_type;
511 9a64fbe4 bellard
    int ret = 0;
512 9a64fbe4 bellard
513 9a64fbe4 bellard
//    printf("%s 0\n", __func__);
514 9a64fbe4 bellard
    is_user = flags & 0x01;
515 ac9eb073 bellard
    access_type = env->access_type;
516 9a64fbe4 bellard
    if (env->user_mode_only) {
517 9a64fbe4 bellard
        /* user mode only emulation */
518 9a64fbe4 bellard
        ret = -1;
519 9a64fbe4 bellard
        goto do_fault;
520 9a64fbe4 bellard
    }
521 9a64fbe4 bellard
    ret = get_physical_address(env, &physical, &prot,
522 9a64fbe4 bellard
                               address, rw, access_type);
523 9a64fbe4 bellard
    if (ret == 0) {
524 9a64fbe4 bellard
        ret = tlb_set_page(env, address, physical, prot, is_user, is_softmmu);
525 9a64fbe4 bellard
    } else if (ret < 0) {
526 9a64fbe4 bellard
    do_fault:
527 9a64fbe4 bellard
#if defined (DEBUG_MMU)
528 9a64fbe4 bellard
        printf("%s 5\n", __func__);
529 9a64fbe4 bellard
        printf("nip=0x%08x LR=0x%08x CTR=0x%08x MSR=0x%08x TBL=0x%08x\n",
530 9a64fbe4 bellard
               env->nip, env->lr, env->ctr, /*msr*/0, env->tb[0]);
531 9a64fbe4 bellard
        {
532 9a64fbe4 bellard
            int  i;
533 9a64fbe4 bellard
            for (i = 0; i < 32; i++) {
534 9a64fbe4 bellard
                if ((i & 7) == 0)
535 9a64fbe4 bellard
                    printf("GPR%02d:", i);
536 9a64fbe4 bellard
                printf(" %08x", env->gpr[i]);
537 9a64fbe4 bellard
                if ((i & 7) == 7)
538 9a64fbe4 bellard
                    printf("\n");
539 9a64fbe4 bellard
            }
540 9a64fbe4 bellard
            printf("CR: 0x");
541 9a64fbe4 bellard
            for (i = 0; i < 8; i++)
542 9a64fbe4 bellard
                printf("%01x", env->crf[i]);
543 9a64fbe4 bellard
            printf("  [");
544 9a64fbe4 bellard
            for (i = 0; i < 8; i++) {
545 9a64fbe4 bellard
                char a = '-';
546 9a64fbe4 bellard
                if (env->crf[i] & 0x08)
547 9a64fbe4 bellard
                    a = 'L';
548 9a64fbe4 bellard
                else if (env->crf[i] & 0x04)
549 9a64fbe4 bellard
                    a = 'G';
550 9a64fbe4 bellard
                else if (env->crf[i] & 0x02)
551 9a64fbe4 bellard
                    a = 'E';
552 9a64fbe4 bellard
                printf(" %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
553 9a64fbe4 bellard
            }
554 9a64fbe4 bellard
            printf(" ] ");
555 9a64fbe4 bellard
        }
556 9a64fbe4 bellard
        printf("TB: 0x%08x %08x\n", env->tb[1], env->tb[0]);
557 9a64fbe4 bellard
        printf("SRR0 0x%08x SRR1 0x%08x\n", env->spr[SRR0], env->spr[SRR1]);
558 9a64fbe4 bellard
#endif
559 9a64fbe4 bellard
        if (access_type == ACCESS_CODE) {
560 9a64fbe4 bellard
            exception = EXCP_ISI;
561 9a64fbe4 bellard
            switch (ret) {
562 9a64fbe4 bellard
            case -1:
563 9a64fbe4 bellard
                /* No matches in page tables */
564 9a64fbe4 bellard
                error_code = EXCP_ISI_TRANSLATE;
565 9a64fbe4 bellard
                break;
566 9a64fbe4 bellard
            case -2:
567 9a64fbe4 bellard
                /* Access rights violation */
568 9a64fbe4 bellard
                error_code = EXCP_ISI_PROT;
569 9a64fbe4 bellard
                break;
570 9a64fbe4 bellard
            case -3:
571 9a64fbe4 bellard
                error_code = EXCP_ISI_NOEXEC;
572 9a64fbe4 bellard
                break;
573 9a64fbe4 bellard
            case -4:
574 9a64fbe4 bellard
                /* Direct store exception */
575 9a64fbe4 bellard
                /* No code fetch is allowed in direct-store areas */
576 9a64fbe4 bellard
                exception = EXCP_ISI;
577 9a64fbe4 bellard
                error_code = EXCP_ISI_NOEXEC;
578 9a64fbe4 bellard
                break;
579 9a64fbe4 bellard
            }
580 9a64fbe4 bellard
        } else {
581 9a64fbe4 bellard
            exception = EXCP_DSI;
582 9a64fbe4 bellard
            switch (ret) {
583 9a64fbe4 bellard
            case -1:
584 9a64fbe4 bellard
                /* No matches in page tables */
585 9a64fbe4 bellard
                error_code = EXCP_DSI_TRANSLATE;
586 9a64fbe4 bellard
                break;
587 9a64fbe4 bellard
            case -2:
588 9a64fbe4 bellard
                /* Access rights violation */
589 9a64fbe4 bellard
                error_code = EXCP_DSI_PROT;
590 9a64fbe4 bellard
                break;
591 9a64fbe4 bellard
            case -4:
592 9a64fbe4 bellard
                /* Direct store exception */
593 9a64fbe4 bellard
                switch (access_type) {
594 9a64fbe4 bellard
                case ACCESS_FLOAT:
595 9a64fbe4 bellard
                    /* Floating point load/store */
596 9a64fbe4 bellard
                    exception = EXCP_ALIGN;
597 9a64fbe4 bellard
                    error_code = EXCP_ALIGN_FP;
598 9a64fbe4 bellard
                    break;
599 9a64fbe4 bellard
                case ACCESS_RES:
600 9a64fbe4 bellard
                    /* lwarx, ldarx or srwcx. */
601 9a64fbe4 bellard
                    exception = EXCP_DSI;
602 9a64fbe4 bellard
                    error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
603 9a64fbe4 bellard
                    if (rw)
604 9a64fbe4 bellard
                        error_code |= EXCP_DSI_STORE;
605 9a64fbe4 bellard
                    break;
606 9a64fbe4 bellard
                case ACCESS_EXT:
607 9a64fbe4 bellard
                    /* eciwx or ecowx */
608 9a64fbe4 bellard
                    exception = EXCP_DSI;
609 9a64fbe4 bellard
                    error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT | EXCP_ECXW;
610 9a64fbe4 bellard
                    break;
611 9a64fbe4 bellard
                default:
612 9a64fbe4 bellard
                    exception = EXCP_PROGRAM;
613 9a64fbe4 bellard
                    error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
614 9a64fbe4 bellard
                    break;
615 9a64fbe4 bellard
                }
616 9a64fbe4 bellard
            }
617 9a64fbe4 bellard
            if (rw)
618 9a64fbe4 bellard
                error_code |= EXCP_DSI_STORE;
619 9a64fbe4 bellard
            /* Should find a better solution:
620 9a64fbe4 bellard
             * this will be invalid for some exception if more than one
621 9a64fbe4 bellard
             * exception occurs for one instruction
622 9a64fbe4 bellard
             */
623 9a64fbe4 bellard
            env->spr[DSISR] = 0;
624 9a64fbe4 bellard
            if (error_code & EXCP_DSI_DIRECT) {
625 9a64fbe4 bellard
                env->spr[DSISR] |= 0x80000000;
626 9a64fbe4 bellard
                if (access_type == ACCESS_EXT ||
627 9a64fbe4 bellard
                    access_type == ACCESS_RES)
628 9a64fbe4 bellard
                    env->spr[DSISR] |= 0x04000000;
629 9a64fbe4 bellard
            }
630 9a64fbe4 bellard
            if ((error_code & 0xF) == EXCP_DSI_TRANSLATE)
631 9a64fbe4 bellard
                env->spr[DSISR] |= 0x40000000;
632 9a64fbe4 bellard
            if (error_code & EXCP_DSI_PROT)
633 9a64fbe4 bellard
                env->spr[DSISR] |= 0x08000000;
634 9a64fbe4 bellard
            if (error_code & EXCP_DSI_STORE)
635 9a64fbe4 bellard
                env->spr[DSISR] |= 0x02000000;
636 9a64fbe4 bellard
            if ((error_code & 0xF) == EXCP_DSI_DABR)
637 9a64fbe4 bellard
                env->spr[DSISR] |= 0x00400000;
638 9a64fbe4 bellard
            if (access_type == ACCESS_EXT)
639 9a64fbe4 bellard
                env->spr[DSISR] |= 0x00100000;
640 9a64fbe4 bellard
        }
641 9a64fbe4 bellard
#if 0
642 9a64fbe4 bellard
        printf("%s: set exception to %d %02x\n",
643 9a64fbe4 bellard
               __func__, exception, error_code);
644 9a64fbe4 bellard
#endif
645 9a64fbe4 bellard
        env->exception_index = exception;
646 9a64fbe4 bellard
        env->error_code = error_code;
647 9a64fbe4 bellard
        /* Store fault address */
648 9a64fbe4 bellard
        env->spr[DAR] = address;
649 9a64fbe4 bellard
        ret = 1;
650 9a64fbe4 bellard
    }
651 9a64fbe4 bellard
652 9a64fbe4 bellard
    return ret;
653 9a64fbe4 bellard
}
654 9a64fbe4 bellard
655 9a64fbe4 bellard
uint32_t _load_xer (void)
656 79aceca5 bellard
{
657 79aceca5 bellard
    return (xer_so << XER_SO) |
658 79aceca5 bellard
        (xer_ov << XER_OV) |
659 79aceca5 bellard
        (xer_ca << XER_CA) |
660 79aceca5 bellard
        (xer_bc << XER_BC);
661 79aceca5 bellard
}
662 79aceca5 bellard
663 9a64fbe4 bellard
void _store_xer (uint32_t value)
664 79aceca5 bellard
{
665 79aceca5 bellard
    xer_so = (value >> XER_SO) & 0x01;
666 79aceca5 bellard
    xer_ov = (value >> XER_OV) & 0x01;
667 79aceca5 bellard
    xer_ca = (value >> XER_CA) & 0x01;
668 79aceca5 bellard
    xer_bc = (value >> XER_BC) & 0x1f;
669 79aceca5 bellard
}
670 79aceca5 bellard
671 9a64fbe4 bellard
uint32_t _load_msr (void)
672 79aceca5 bellard
{
673 79aceca5 bellard
    return (msr_pow << MSR_POW) |
674 79aceca5 bellard
        (msr_ile << MSR_ILE) |
675 79aceca5 bellard
        (msr_ee << MSR_EE) |
676 79aceca5 bellard
        (msr_pr << MSR_PR) |
677 79aceca5 bellard
        (msr_fp << MSR_FP) |
678 79aceca5 bellard
        (msr_me << MSR_ME) |
679 79aceca5 bellard
        (msr_fe0 << MSR_FE0) |
680 79aceca5 bellard
        (msr_se << MSR_SE) |
681 79aceca5 bellard
        (msr_be << MSR_BE) |
682 79aceca5 bellard
        (msr_fe1 << MSR_FE1) |
683 79aceca5 bellard
        (msr_ip << MSR_IP) |
684 79aceca5 bellard
        (msr_ir << MSR_IR) |
685 79aceca5 bellard
        (msr_dr << MSR_DR) |
686 79aceca5 bellard
        (msr_ri << MSR_RI) |
687 79aceca5 bellard
        (msr_le << MSR_LE);
688 79aceca5 bellard
}
689 79aceca5 bellard
690 9a64fbe4 bellard
void _store_msr (uint32_t value)
691 79aceca5 bellard
{
692 9a64fbe4 bellard
    msr_pow = (value >> MSR_POW) & 0x03;
693 9a64fbe4 bellard
    msr_ile = (value >> MSR_ILE) & 0x01;
694 9a64fbe4 bellard
    msr_ee = (value >> MSR_EE) & 0x01;
695 9a64fbe4 bellard
    msr_pr = (value >> MSR_PR) & 0x01;
696 9a64fbe4 bellard
    msr_fp = (value >> MSR_FP) & 0x01;
697 9a64fbe4 bellard
    msr_me = (value >> MSR_ME) & 0x01;
698 9a64fbe4 bellard
    msr_fe0 = (value >> MSR_FE0) & 0x01;
699 9a64fbe4 bellard
    msr_se = (value >> MSR_SE) & 0x01;
700 9a64fbe4 bellard
    msr_be = (value >> MSR_BE) & 0x01;
701 9a64fbe4 bellard
    msr_fe1 = (value >> MSR_FE1) & 0x01;
702 9a64fbe4 bellard
    msr_ip = (value >> MSR_IP) & 0x01;
703 9a64fbe4 bellard
    msr_ir = (value >> MSR_IR) & 0x01;
704 9a64fbe4 bellard
    msr_dr = (value >> MSR_DR) & 0x01;
705 9a64fbe4 bellard
    msr_ri = (value >> MSR_RI) & 0x01;
706 9a64fbe4 bellard
    msr_le = (value >> MSR_LE) & 0x01;
707 79aceca5 bellard
}
708 79aceca5 bellard
709 9a64fbe4 bellard
void do_interrupt (CPUState *env)
710 79aceca5 bellard
{
711 9a64fbe4 bellard
#if defined (CONFIG_USER_ONLY)
712 9a64fbe4 bellard
    env->exception_index |= 0x100;
713 9a64fbe4 bellard
#else
714 9a64fbe4 bellard
    uint32_t msr;
715 9a64fbe4 bellard
    int excp = env->exception_index;
716 79aceca5 bellard
717 9a64fbe4 bellard
    /* Dequeue PPC exceptions */
718 9a64fbe4 bellard
    if (excp < EXCP_PPC_MAX)
719 9a64fbe4 bellard
        env->exceptions &= ~(1 << excp);
720 9a64fbe4 bellard
    msr = _load_msr();
721 9a64fbe4 bellard
#if defined (DEBUG_EXCEPTIONS)
722 9a64fbe4 bellard
    if (excp != EXCP_DECR && excp == EXCP_PROGRAM && excp < EXCP_PPC_MAX) 
723 9a64fbe4 bellard
    {
724 9a64fbe4 bellard
        if (loglevel > 0) {
725 9a64fbe4 bellard
            fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
726 9a64fbe4 bellard
                    env->nip, excp << 8, env->error_code);
727 9a64fbe4 bellard
        } else {
728 9a64fbe4 bellard
            printf("Raise exception at 0x%08x => 0x%08x (%02x)\n",
729 9a64fbe4 bellard
                   env->nip, excp << 8, env->error_code);
730 9a64fbe4 bellard
        }
731 9a64fbe4 bellard
        printf("nip=0x%08x LR=0x%08x CTR=0x%08x MSR=0x%08x DECR=0x%08x\n",
732 9a64fbe4 bellard
               env->nip, env->lr, env->ctr, msr, env->decr);
733 9a64fbe4 bellard
        {
734 79aceca5 bellard
    int i;
735 9a64fbe4 bellard
            for (i = 0; i < 32; i++) {
736 9a64fbe4 bellard
                if ((i & 7) == 0)
737 9a64fbe4 bellard
                    printf("GPR%02d:", i);
738 9a64fbe4 bellard
                printf(" %08x", env->gpr[i]);
739 9a64fbe4 bellard
                if ((i & 7) == 7)
740 9a64fbe4 bellard
                    printf("\n");
741 fb0eaffc bellard
    }
742 9a64fbe4 bellard
            printf("CR: 0x");
743 9a64fbe4 bellard
    for (i = 0; i < 8; i++)
744 9a64fbe4 bellard
                printf("%01x", env->crf[i]);
745 9a64fbe4 bellard
            printf("  [");
746 9a64fbe4 bellard
            for (i = 0; i < 8; i++) {
747 9a64fbe4 bellard
                char a = '-';
748 9a64fbe4 bellard
                if (env->crf[i] & 0x08)
749 9a64fbe4 bellard
                    a = 'L';
750 9a64fbe4 bellard
                else if (env->crf[i] & 0x04)
751 9a64fbe4 bellard
                    a = 'G';
752 9a64fbe4 bellard
                else if (env->crf[i] & 0x02)
753 9a64fbe4 bellard
                    a = 'E';
754 9a64fbe4 bellard
                printf(" %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
755 79aceca5 bellard
    }
756 9a64fbe4 bellard
            printf(" ] ");
757 79aceca5 bellard
    }
758 9a64fbe4 bellard
        printf("TB: 0x%08x %08x\n", env->tb[1], env->tb[0]);
759 9a64fbe4 bellard
        printf("XER 0x%08x SRR0 0x%08x SRR1 0x%08x\n",
760 9a64fbe4 bellard
               _load_xer(), env->spr[SRR0], env->spr[SRR1]);
761 79aceca5 bellard
    }
762 9a64fbe4 bellard
#endif
763 9a64fbe4 bellard
    /* Generate informations in save/restore registers */
764 9a64fbe4 bellard
    switch (excp) {
765 9a64fbe4 bellard
    case EXCP_OFCALL:
766 9a64fbe4 bellard
#if defined (USE_OPEN_FIRMWARE)
767 9a64fbe4 bellard
        env->gpr[3] = OF_client_entry((void *)env->gpr[3]);
768 9a64fbe4 bellard
#endif
769 9a64fbe4 bellard
        return;
770 9a64fbe4 bellard
    case EXCP_RTASCALL:
771 9a64fbe4 bellard
#if defined (USE_OPEN_FIRMWARE)
772 9a64fbe4 bellard
        printf("RTAS call !\n");
773 9a64fbe4 bellard
        env->gpr[3] = RTAS_entry((void *)env->gpr[3]);
774 9a64fbe4 bellard
        printf("RTAS call done\n");
775 9a64fbe4 bellard
#endif
776 9a64fbe4 bellard
        return;
777 9a64fbe4 bellard
    case EXCP_NONE:
778 9a64fbe4 bellard
        /* Do nothing */
779 9a64fbe4 bellard
#if defined (DEBUG_EXCEPTIONS)
780 9a64fbe4 bellard
        printf("%s: escape EXCP_NONE\n", __func__);
781 9a64fbe4 bellard
#endif
782 9a64fbe4 bellard
        return;
783 9a64fbe4 bellard
    case EXCP_RESET:
784 9a64fbe4 bellard
        if (msr_ip)
785 9a64fbe4 bellard
            excp += 0xFFC00;
786 9a64fbe4 bellard
        goto store_next;
787 9a64fbe4 bellard
    case EXCP_MACHINE_CHECK:
788 9a64fbe4 bellard
        if (msr_me == 0) {
789 9a64fbe4 bellard
            printf("Machine check exception while not allowed !\n");
790 9a64fbe4 bellard
            if (loglevel) {
791 9a64fbe4 bellard
                fprintf(logfile,
792 9a64fbe4 bellard
                        "Machine check exception while not allowed !\n");
793 79aceca5 bellard
        }
794 9a64fbe4 bellard
            abort();
795 79aceca5 bellard
    }
796 9a64fbe4 bellard
        msr_me = 0;
797 9a64fbe4 bellard
        break;
798 9a64fbe4 bellard
    case EXCP_DSI:
799 9a64fbe4 bellard
        /* Store exception cause */
800 9a64fbe4 bellard
        /* data location address has been stored
801 9a64fbe4 bellard
         * when the fault has been detected
802 9a64fbe4 bellard
     */
803 9a64fbe4 bellard
        goto store_current;
804 9a64fbe4 bellard
    case EXCP_ISI:
805 9a64fbe4 bellard
        /* Store exception cause */
806 9a64fbe4 bellard
        if (env->error_code == EXCP_ISI_TRANSLATE)
807 9a64fbe4 bellard
            msr |= 0x40000000;
808 9a64fbe4 bellard
        else if (env->error_code == EXCP_ISI_NOEXEC ||
809 9a64fbe4 bellard
            env->error_code == EXCP_ISI_GUARD)
810 9a64fbe4 bellard
            msr |= 0x10000000;
811 9a64fbe4 bellard
        else
812 9a64fbe4 bellard
            msr |= 0x08000000;
813 9a64fbe4 bellard
        goto store_next;
814 9a64fbe4 bellard
    case EXCP_EXTERNAL:
815 9a64fbe4 bellard
        if (msr_ee == 0) {
816 9a64fbe4 bellard
#if defined (DEBUG_EXCEPTIONS)
817 9a64fbe4 bellard
            if (loglevel > 0) {
818 9a64fbe4 bellard
                fprintf(logfile, "Skipping hardware interrupt\n");
819 9a64fbe4 bellard
            } else {
820 9a64fbe4 bellard
                printf("Skipping hardware interrupt\n");
821 79aceca5 bellard
    }
822 9a64fbe4 bellard
#endif
823 9a64fbe4 bellard
            return;
824 79aceca5 bellard
            }
825 9a64fbe4 bellard
        goto store_next;
826 9a64fbe4 bellard
    case EXCP_ALIGN:
827 9a64fbe4 bellard
        /* Store exception cause */
828 9a64fbe4 bellard
        /* Get rS/rD and rA from faulting opcode */
829 9a64fbe4 bellard
        env->spr[DSISR] |=
830 9a64fbe4 bellard
            (ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16;
831 9a64fbe4 bellard
        /* data location address has been stored
832 9a64fbe4 bellard
         * when the fault has been detected
833 9a64fbe4 bellard
         */
834 9a64fbe4 bellard
        goto store_current;
835 9a64fbe4 bellard
    case EXCP_PROGRAM:
836 9a64fbe4 bellard
        msr &= ~0xFFFF0000;
837 9a64fbe4 bellard
        switch (env->error_code & ~0xF) {
838 9a64fbe4 bellard
        case EXCP_FP:
839 9a64fbe4 bellard
            if (msr_fe0 == 0 && msr_fe1 == 0) {
840 9a64fbe4 bellard
#if defined (DEBUG_EXCEPTIONS)
841 9a64fbe4 bellard
                printf("Ignore floating point exception\n");
842 9a64fbe4 bellard
#endif
843 9a64fbe4 bellard
                return;
844 79aceca5 bellard
        }
845 9a64fbe4 bellard
            msr |= 0x00100000;
846 9a64fbe4 bellard
            /* Set FX */
847 9a64fbe4 bellard
            env->fpscr[7] |= 0x8;
848 9a64fbe4 bellard
            /* Finally, update FEX */
849 9a64fbe4 bellard
            if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
850 9a64fbe4 bellard
                ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
851 9a64fbe4 bellard
                env->fpscr[7] |= 0x4;
852 9a64fbe4 bellard
        break;
853 9a64fbe4 bellard
        case EXCP_INVAL:
854 9a64fbe4 bellard
            msr |= 0x00080000;
855 9a64fbe4 bellard
        break;
856 9a64fbe4 bellard
        case EXCP_PRIV:
857 9a64fbe4 bellard
            msr |= 0x00040000;
858 9a64fbe4 bellard
        break;
859 9a64fbe4 bellard
        case EXCP_TRAP:
860 9a64fbe4 bellard
            msr |= 0x00020000;
861 9a64fbe4 bellard
            break;
862 9a64fbe4 bellard
        default:
863 9a64fbe4 bellard
            /* Should never occur */
864 9a64fbe4 bellard
        break;
865 79aceca5 bellard
    }
866 9a64fbe4 bellard
        msr |= 0x00010000;
867 9a64fbe4 bellard
        goto store_current;
868 9a64fbe4 bellard
    case EXCP_NO_FP:
869 9a64fbe4 bellard
        goto store_current;
870 9a64fbe4 bellard
    case EXCP_DECR:
871 9a64fbe4 bellard
        if (msr_ee == 0) {
872 9a64fbe4 bellard
            /* Requeue it */
873 9a64fbe4 bellard
            do_queue_exception(EXCP_DECR);
874 9a64fbe4 bellard
            return;
875 9a64fbe4 bellard
        }
876 9a64fbe4 bellard
        goto store_next;
877 9a64fbe4 bellard
    case EXCP_SYSCALL:
878 9a64fbe4 bellard
#if defined (DEBUG_EXCEPTIONS)
879 9a64fbe4 bellard
        printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
880 9a64fbe4 bellard
               env->gpr[0], env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
881 9a64fbe4 bellard
#endif
882 9a64fbe4 bellard
        goto store_next;
883 9a64fbe4 bellard
    case EXCP_TRACE:
884 9a64fbe4 bellard
        goto store_next;
885 9a64fbe4 bellard
    case EXCP_FP_ASSIST:
886 9a64fbe4 bellard
        goto store_next;
887 9a64fbe4 bellard
    case EXCP_MTMSR:
888 9a64fbe4 bellard
        /* Nothing to do */
889 9a64fbe4 bellard
#if defined (DEBUG_EXCEPTIONS)
890 9a64fbe4 bellard
        printf("%s: escape EXCP_MTMSR\n", __func__);
891 9a64fbe4 bellard
#endif
892 9a64fbe4 bellard
        return;
893 9a64fbe4 bellard
    case EXCP_BRANCH:
894 9a64fbe4 bellard
        /* Nothing to do */
895 9a64fbe4 bellard
#if defined (DEBUG_EXCEPTIONS)
896 9a64fbe4 bellard
        printf("%s: escape EXCP_BRANCH\n", __func__);
897 9a64fbe4 bellard
#endif
898 9a64fbe4 bellard
        return;
899 9a64fbe4 bellard
    case EXCP_RFI:
900 9a64fbe4 bellard
        /* Restore user-mode state */
901 9a64fbe4 bellard
#if defined (DEBUG_EXCEPTIONS)
902 9a64fbe4 bellard
        printf("%s: escape EXCP_RFI\n", __func__);
903 9a64fbe4 bellard
#endif
904 9a64fbe4 bellard
        return;
905 9a64fbe4 bellard
    store_current:
906 9a64fbe4 bellard
        /* SRR0 is set to current instruction */
907 9a64fbe4 bellard
        env->spr[SRR0] = (uint32_t)env->nip - 4;
908 9a64fbe4 bellard
        break;
909 9a64fbe4 bellard
    store_next:
910 9a64fbe4 bellard
        /* SRR0 is set to next instruction */
911 9a64fbe4 bellard
        env->spr[SRR0] = (uint32_t)env->nip;
912 9a64fbe4 bellard
        break;
913 9a64fbe4 bellard
    }
914 9a64fbe4 bellard
    env->spr[SRR1] = msr;
915 9a64fbe4 bellard
    /* reload MSR with correct bits */
916 9a64fbe4 bellard
    msr_pow = 0;
917 9a64fbe4 bellard
    msr_ee = 0;
918 9a64fbe4 bellard
    msr_pr = 0;
919 9a64fbe4 bellard
    msr_fp = 0;
920 9a64fbe4 bellard
    msr_fe0 = 0;
921 9a64fbe4 bellard
    msr_se = 0;
922 9a64fbe4 bellard
    msr_be = 0;
923 9a64fbe4 bellard
    msr_fe1 = 0;
924 9a64fbe4 bellard
    msr_ir = 0;
925 9a64fbe4 bellard
    msr_dr = 0;
926 9a64fbe4 bellard
    msr_ri = 0;
927 9a64fbe4 bellard
    msr_le = msr_ile;
928 9a64fbe4 bellard
    /* Jump to handler */
929 9a64fbe4 bellard
    env->nip = excp << 8;
930 9a64fbe4 bellard
    env->exception_index = EXCP_NONE;
931 9a64fbe4 bellard
    /* Invalidate all TLB as we may have changed translation mode */
932 9a64fbe4 bellard
    do_tlbia();
933 9a64fbe4 bellard
    /* ensure that no TB jump will be modified as
934 9a64fbe4 bellard
       the program flow was changed */
935 9a64fbe4 bellard
#ifdef __sparc__
936 9a64fbe4 bellard
    tmp_T0 = 0;
937 9a64fbe4 bellard
#else
938 9a64fbe4 bellard
    T0 = 0;
939 9a64fbe4 bellard
#endif
940 9a64fbe4 bellard
#endif
941 fb0eaffc bellard
}