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/*
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 *  PPC emulation for qemu: main translation routines.
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 * 
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 *  Copyright (c) 2003 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "dyngen-exec.h"
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#include "cpu.h"
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#include "exec.h"
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#include "disas.h"
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//#define DO_SINGLE_STEP
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//#define DO_STEP_FLUSH
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//#define DEBUG_DISAS
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enum {
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#define DEF(s, n, copy_size) INDEX_op_ ## s,
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#include "opc.h"
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#undef DEF
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    NB_OPS,
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};
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
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#include "gen-op.h"
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#define GEN8(func, NAME) \
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static GenOpFunc *NAME ## _table [8] = {                                      \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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};                                                                            \
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static inline void func(int n)                                                \
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{                                                                             \
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    NAME ## _table[n]();                                                      \
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}
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#define GEN16(func, NAME)                                                     \
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static GenOpFunc *NAME ## _table [16] = {                                     \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
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};                                                                            \
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static inline void func(int n)                                                \
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{                                                                             \
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    NAME ## _table[n]();                                                      \
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}
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#define GEN32(func, NAME) \
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static GenOpFunc *NAME ## _table [32] = {                                     \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
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NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
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NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
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NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
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};                                                                            \
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static inline void func(int n)                                                \
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{                                                                             \
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    NAME ## _table[n]();                                                      \
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}
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/* Condition register moves */
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GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
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GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
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GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
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GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
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/* Floating point condition and status register moves */
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GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
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GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
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GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
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static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
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    &gen_op_store_T0_fpscri_fpscr0,
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    &gen_op_store_T0_fpscri_fpscr1,
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    &gen_op_store_T0_fpscri_fpscr2,
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    &gen_op_store_T0_fpscri_fpscr3,
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    &gen_op_store_T0_fpscri_fpscr4,
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    &gen_op_store_T0_fpscri_fpscr5,
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    &gen_op_store_T0_fpscri_fpscr6,
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    &gen_op_store_T0_fpscri_fpscr7,
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};
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static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
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{
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    (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
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}
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/* Segment register moves */
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GEN16(gen_op_load_sr, gen_op_load_sr);
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GEN16(gen_op_store_sr, gen_op_store_sr);
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/* General purpose registers moves */
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GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
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GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
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GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
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GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
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GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
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GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
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/* floating point registers moves */
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GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
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GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
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GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
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GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
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GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
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GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
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static uint8_t  spr_access[1024 / 2];
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/* internal defines */
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typedef struct DisasContext {
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    struct TranslationBlock *tb;
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    uint32_t *nip;
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    uint32_t opcode;
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    uint32_t exception;
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    /* Time base offset */
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    uint32_t tb_offset;
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    /* Decrementer offset */
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    uint32_t decr_offset;
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    /* Execution mode */
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#if !defined(CONFIG_USER_ONLY)
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    int supervisor;
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#endif
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    /* Routine used to access memory */
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    int mem_idx;
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} DisasContext;
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typedef struct opc_handler_t {
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    /* invalid bits */
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    uint32_t inval;
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    /* instruction type */
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    uint32_t type;
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    /* handler */
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    void (*handler)(DisasContext *ctx);
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} opc_handler_t;
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#define RET_EXCP(excp, error)                                                 \
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do {                                                                          \
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    gen_op_queue_exception_err(excp, error);                                  \
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    ctx->exception = excp;                                                    \
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    return;                                                                   \
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} while (0)
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#define RET_INVAL()                                                           \
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RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
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#define RET_PRIVOPC()                                                         \
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RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
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#define RET_PRIVREG()                                                         \
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RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
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#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
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static void gen_##name (DisasContext *ctx);                                   \
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GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \
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static void gen_##name (DisasContext *ctx)
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typedef struct opcode_t {
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    unsigned char opc1, opc2, opc3;
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    opc_handler_t handler;
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} opcode_t;
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/* XXX: move that elsewhere */
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extern FILE *logfile;
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extern int loglevel;
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/***                           Instruction decoding                        ***/
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#define EXTRACT_HELPER(name, shift, nb)                                       \
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static inline uint32_t name (uint32_t opcode)                                 \
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{                                                                             \
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    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
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}
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#define EXTRACT_SHELPER(name, shift, nb)                                      \
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static inline int32_t name (uint32_t opcode)                                  \
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{                                                                             \
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    return s_ext16((opcode >> (shift)) & ((1 << (nb)) - 1));                  \
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}
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/* Opcode part 1 */
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EXTRACT_HELPER(opc1, 26, 6);
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/* Opcode part 2 */
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EXTRACT_HELPER(opc2, 1, 5);
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/* Opcode part 3 */
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EXTRACT_HELPER(opc3, 6, 5);
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/* Update Cr0 flags */
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EXTRACT_HELPER(Rc, 0, 1);
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/* Destination */
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EXTRACT_HELPER(rD, 21, 5);
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/* Source */
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EXTRACT_HELPER(rS, 21, 5);
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/* First operand */
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EXTRACT_HELPER(rA, 16, 5);
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/* Second operand */
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EXTRACT_HELPER(rB, 11, 5);
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/* Third operand */
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EXTRACT_HELPER(rC, 6, 5);
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/***                               Get CRn                                 ***/
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EXTRACT_HELPER(crfD, 23, 3);
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EXTRACT_HELPER(crfS, 18, 3);
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EXTRACT_HELPER(crbD, 21, 5);
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EXTRACT_HELPER(crbA, 16, 5);
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EXTRACT_HELPER(crbB, 11, 5);
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/* SPR / TBL */
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EXTRACT_HELPER(SPR, 11, 10);
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/***                              Get constants                            ***/
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EXTRACT_HELPER(IMM, 12, 8);
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/* 16 bits signed immediate value */
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EXTRACT_SHELPER(SIMM, 0, 16);
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/* 16 bits unsigned immediate value */
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EXTRACT_HELPER(UIMM, 0, 16);
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/* Bit count */
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EXTRACT_HELPER(NB, 11, 5);
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/* Shift count */
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EXTRACT_HELPER(SH, 11, 5);
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/* Mask start */
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EXTRACT_HELPER(MB, 6, 5);
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/* Mask end */
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EXTRACT_HELPER(ME, 1, 5);
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/* Trap operand */
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EXTRACT_HELPER(TO, 21, 5);
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EXTRACT_HELPER(CRM, 12, 8);
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EXTRACT_HELPER(FM, 17, 8);
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EXTRACT_HELPER(SR, 16, 4);
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EXTRACT_HELPER(FPIMM, 20, 4);
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/***                            Jump target decoding                       ***/
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/* Displacement */
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EXTRACT_SHELPER(d, 0, 16);
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/* Immediate address */
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static inline uint32_t LI (uint32_t opcode)
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{
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    return (opcode >> 0) & 0x03FFFFFC;
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}
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static inline uint32_t BD (uint32_t opcode)
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{
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    return (opcode >> 0) & 0xFFFC;
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}
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EXTRACT_HELPER(BO, 21, 5);
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EXTRACT_HELPER(BI, 16, 5);
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/* Absolute/relative address */
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EXTRACT_HELPER(AA, 1, 1);
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/* Link */
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EXTRACT_HELPER(LK, 0, 1);
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/* Create a mask between <start> and <end> bits */
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static inline uint32_t MASK (uint32_t start, uint32_t end)
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{
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    uint32_t ret;
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    ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
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    if (start > end)
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        return ~ret;
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    return ret;
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}
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#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
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__attribute__ ((section(".opcodes"), unused))                                 \
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static opcode_t opc_##name = {                                                \
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    .opc1 = op1,                                                              \
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    .opc2 = op2,                                                              \
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    .opc3 = op3,                                                              \
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    .handler = {                                                              \
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        .inval   = invl,                                                      \
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        .type = _typ,                                                         \
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        .handler = &gen_##name,                                               \
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    },                                                                        \
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}
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#define GEN_OPCODE_MARK(name)                                                 \
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__attribute__ ((section(".opcodes"), unused))                                 \
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static opcode_t opc_##name = {                                                \
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    .opc1 = 0xFF,                                                             \
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    .opc2 = 0xFF,                                                             \
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    .opc3 = 0xFF,                                                             \
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    .handler = {                                                              \
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        .inval   = 0x00000000,                                                \
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        .type = 0x00,                                                         \
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        .handler = NULL,                                                      \
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    },                                                                        \
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}
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/* Start opcode list */
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GEN_OPCODE_MARK(start);
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/* Invalid instruction */
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GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
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{
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    RET_INVAL();
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}
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/* Special opcode to stop emulation */
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GEN_HANDLER(stop, 0x06, 0x00, 0xFF, 0x03FFFFC1, PPC_COMMON)
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{
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    gen_op_queue_exception(EXCP_HLT);
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    ctx->exception = EXCP_HLT;
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}
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/* Special opcode to call open-firmware */
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GEN_HANDLER(of_enter, 0x06, 0x01, 0xFF, 0x03FFFFC1, PPC_COMMON)
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{
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    gen_op_queue_exception(EXCP_OFCALL);
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    ctx->exception = EXCP_OFCALL;
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}
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/* Special opcode to call RTAS */
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GEN_HANDLER(rtas_enter, 0x06, 0x02, 0xFF, 0x03FFFFC1, PPC_COMMON)
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{
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    printf("RTAS entry point !\n");
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    gen_op_queue_exception(EXCP_RTASCALL);
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    ctx->exception = EXCP_RTASCALL;
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}
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static opc_handler_t invalid_handler = {
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    .inval   = 0xFFFFFFFF,
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    .type    = PPC_NONE,
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    .handler = gen_invalid,
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};
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/***                           Integer arithmetic                          ***/
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#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval)                       \
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GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER)                       \
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{                                                                             \
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    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
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    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
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    gen_op_##name();                                                          \
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    if (Rc(ctx->opcode) != 0)                                                 \
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        gen_op_set_Rc0();                                                     \
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    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
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}
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#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval)                     \
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GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER)                       \
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{                                                                             \
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    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
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    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
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    gen_op_##name();                                                          \
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    if (Rc(ctx->opcode) != 0)                                                 \
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        gen_op_set_Rc0_ov();                                                  \
361 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
362 79aceca5 bellard
}
363 79aceca5 bellard
364 79aceca5 bellard
#define __GEN_INT_ARITH1(name, opc1, opc2, opc3)                              \
365 79aceca5 bellard
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER)                  \
366 79aceca5 bellard
{                                                                             \
367 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
368 79aceca5 bellard
    gen_op_##name();                                                          \
369 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)                                                 \
370 79aceca5 bellard
        gen_op_set_Rc0();                                                     \
371 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
372 79aceca5 bellard
}
373 79aceca5 bellard
#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3)                            \
374 79aceca5 bellard
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER)                  \
375 79aceca5 bellard
{                                                                             \
376 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
377 79aceca5 bellard
    gen_op_##name();                                                          \
378 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)                                                 \
379 79aceca5 bellard
        gen_op_set_Rc0_ov();                                                  \
380 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
381 79aceca5 bellard
}
382 79aceca5 bellard
383 79aceca5 bellard
/* Two operands arithmetic functions */
384 79aceca5 bellard
#define GEN_INT_ARITH2(name, opc1, opc2, opc3)                                \
385 79aceca5 bellard
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000)                          \
386 79aceca5 bellard
__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
387 79aceca5 bellard
388 79aceca5 bellard
/* Two operands arithmetic functions with no overflow allowed */
389 79aceca5 bellard
#define GEN_INT_ARITHN(name, opc1, opc2, opc3)                                \
390 79aceca5 bellard
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
391 79aceca5 bellard
392 79aceca5 bellard
/* One operand arithmetic functions */
393 79aceca5 bellard
#define GEN_INT_ARITH1(name, opc1, opc2, opc3)                                \
394 79aceca5 bellard
__GEN_INT_ARITH1(name, opc1, opc2, opc3)                                      \
395 79aceca5 bellard
__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
396 79aceca5 bellard
397 79aceca5 bellard
/* add    add.    addo    addo.    */
398 79aceca5 bellard
GEN_INT_ARITH2 (add,    0x1F, 0x0A, 0x08);
399 79aceca5 bellard
/* addc   addc.   addco   addco.   */
400 79aceca5 bellard
GEN_INT_ARITH2 (addc,   0x1F, 0x0A, 0x00);
401 79aceca5 bellard
/* adde   adde.   addeo   addeo.   */
402 79aceca5 bellard
GEN_INT_ARITH2 (adde,   0x1F, 0x0A, 0x04);
403 79aceca5 bellard
/* addme  addme.  addmeo  addmeo.  */
404 79aceca5 bellard
GEN_INT_ARITH1 (addme,  0x1F, 0x0A, 0x07);
405 79aceca5 bellard
/* addze  addze.  addzeo  addzeo.  */
406 79aceca5 bellard
GEN_INT_ARITH1 (addze,  0x1F, 0x0A, 0x06);
407 79aceca5 bellard
/* divw   divw.   divwo   divwo.   */
408 79aceca5 bellard
GEN_INT_ARITH2 (divw,   0x1F, 0x0B, 0x0F);
409 79aceca5 bellard
/* divwu  divwu.  divwuo  divwuo.  */
410 79aceca5 bellard
GEN_INT_ARITH2 (divwu,  0x1F, 0x0B, 0x0E);
411 79aceca5 bellard
/* mulhw  mulhw.                   */
412 79aceca5 bellard
GEN_INT_ARITHN (mulhw,  0x1F, 0x0B, 0x02);
413 79aceca5 bellard
/* mulhwu mulhwu.                  */
414 79aceca5 bellard
GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
415 79aceca5 bellard
/* mullw  mullw.  mullwo  mullwo.  */
416 79aceca5 bellard
GEN_INT_ARITH2 (mullw,  0x1F, 0x0B, 0x07);
417 79aceca5 bellard
/* neg    neg.    nego    nego.    */
418 79aceca5 bellard
GEN_INT_ARITH1 (neg,    0x1F, 0x08, 0x03);
419 79aceca5 bellard
/* subf   subf.   subfo   subfo.   */
420 79aceca5 bellard
GEN_INT_ARITH2 (subf,   0x1F, 0x08, 0x01);
421 79aceca5 bellard
/* subfc  subfc.  subfco  subfco.  */
422 79aceca5 bellard
GEN_INT_ARITH2 (subfc,  0x1F, 0x08, 0x00);
423 79aceca5 bellard
/* subfe  subfe.  subfeo  subfeo.  */
424 79aceca5 bellard
GEN_INT_ARITH2 (subfe,  0x1F, 0x08, 0x04);
425 79aceca5 bellard
/* subfme subfme. subfmeo subfmeo. */
426 79aceca5 bellard
GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
427 79aceca5 bellard
/* subfze subfze. subfzeo subfzeo. */
428 79aceca5 bellard
GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
429 79aceca5 bellard
/* addi */
430 79aceca5 bellard
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
431 79aceca5 bellard
{
432 79aceca5 bellard
    int32_t simm = SIMM(ctx->opcode);
433 79aceca5 bellard
434 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
435 79aceca5 bellard
        gen_op_set_T0(simm);
436 79aceca5 bellard
    } else {
437 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
438 79aceca5 bellard
        gen_op_addi(simm);
439 79aceca5 bellard
    }
440 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
441 79aceca5 bellard
}
442 79aceca5 bellard
/* addic */
443 79aceca5 bellard
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
444 79aceca5 bellard
{
445 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
446 79aceca5 bellard
    gen_op_addic(SIMM(ctx->opcode));
447 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
448 79aceca5 bellard
}
449 79aceca5 bellard
/* addic. */
450 79aceca5 bellard
GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
451 79aceca5 bellard
{
452 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
453 79aceca5 bellard
    gen_op_addic(SIMM(ctx->opcode));
454 79aceca5 bellard
    gen_op_set_Rc0();
455 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
456 79aceca5 bellard
}
457 79aceca5 bellard
/* addis */
458 79aceca5 bellard
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
459 79aceca5 bellard
{
460 79aceca5 bellard
    int32_t simm = SIMM(ctx->opcode);
461 79aceca5 bellard
462 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
463 79aceca5 bellard
        gen_op_set_T0(simm << 16);
464 79aceca5 bellard
    } else {
465 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
466 79aceca5 bellard
        gen_op_addi(simm << 16);
467 79aceca5 bellard
    }
468 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
469 79aceca5 bellard
}
470 79aceca5 bellard
/* mulli */
471 79aceca5 bellard
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
472 79aceca5 bellard
{
473 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
474 79aceca5 bellard
    gen_op_mulli(SIMM(ctx->opcode));
475 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
476 79aceca5 bellard
}
477 79aceca5 bellard
/* subfic */
478 79aceca5 bellard
GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
479 79aceca5 bellard
{
480 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
481 79aceca5 bellard
    gen_op_subfic(SIMM(ctx->opcode));
482 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
483 79aceca5 bellard
}
484 79aceca5 bellard
485 79aceca5 bellard
/***                           Integer comparison                          ***/
486 79aceca5 bellard
#define GEN_CMP(name, opc)                                                    \
487 79aceca5 bellard
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER)                   \
488 79aceca5 bellard
{                                                                             \
489 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
490 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
491 79aceca5 bellard
    gen_op_##name();                                                          \
492 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
493 79aceca5 bellard
}
494 79aceca5 bellard
495 79aceca5 bellard
/* cmp */
496 79aceca5 bellard
GEN_CMP(cmp, 0x00);
497 79aceca5 bellard
/* cmpi */
498 79aceca5 bellard
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
499 79aceca5 bellard
{
500 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
501 79aceca5 bellard
    gen_op_cmpi(SIMM(ctx->opcode));
502 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
503 79aceca5 bellard
}
504 79aceca5 bellard
/* cmpl */
505 79aceca5 bellard
GEN_CMP(cmpl, 0x01);
506 79aceca5 bellard
/* cmpli */
507 79aceca5 bellard
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
508 79aceca5 bellard
{
509 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
510 79aceca5 bellard
    gen_op_cmpli(UIMM(ctx->opcode));
511 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
512 79aceca5 bellard
}
513 79aceca5 bellard
514 79aceca5 bellard
/***                            Integer logical                            ***/
515 79aceca5 bellard
#define __GEN_LOGICAL2(name, opc2, opc3)                                      \
516 79aceca5 bellard
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER)                  \
517 79aceca5 bellard
{                                                                             \
518 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
519 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
520 79aceca5 bellard
    gen_op_##name();                                                          \
521 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)                                                 \
522 79aceca5 bellard
        gen_op_set_Rc0();                                                     \
523 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
524 79aceca5 bellard
}
525 79aceca5 bellard
#define GEN_LOGICAL2(name, opc)                                               \
526 79aceca5 bellard
__GEN_LOGICAL2(name, 0x1C, opc)
527 79aceca5 bellard
528 79aceca5 bellard
#define GEN_LOGICAL1(name, opc)                                               \
529 79aceca5 bellard
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER)                   \
530 79aceca5 bellard
{                                                                             \
531 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
532 79aceca5 bellard
    gen_op_##name();                                                          \
533 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)                                                 \
534 79aceca5 bellard
        gen_op_set_Rc0();                                                     \
535 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
536 79aceca5 bellard
}
537 79aceca5 bellard
538 79aceca5 bellard
/* and & and. */
539 79aceca5 bellard
GEN_LOGICAL2(and, 0x00);
540 79aceca5 bellard
/* andc & andc. */
541 79aceca5 bellard
GEN_LOGICAL2(andc, 0x01);
542 79aceca5 bellard
/* andi. */
543 79aceca5 bellard
GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
544 79aceca5 bellard
{
545 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
546 79aceca5 bellard
    gen_op_andi_(UIMM(ctx->opcode));
547 79aceca5 bellard
    gen_op_set_Rc0();
548 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
549 79aceca5 bellard
}
550 79aceca5 bellard
/* andis. */
551 79aceca5 bellard
GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
552 79aceca5 bellard
{
553 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
554 79aceca5 bellard
    gen_op_andi_(UIMM(ctx->opcode) << 16);
555 79aceca5 bellard
    gen_op_set_Rc0();
556 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
557 79aceca5 bellard
}
558 79aceca5 bellard
559 79aceca5 bellard
/* cntlzw */
560 79aceca5 bellard
GEN_LOGICAL1(cntlzw, 0x00);
561 79aceca5 bellard
/* eqv & eqv. */
562 79aceca5 bellard
GEN_LOGICAL2(eqv, 0x08);
563 79aceca5 bellard
/* extsb & extsb. */
564 79aceca5 bellard
GEN_LOGICAL1(extsb, 0x1D);
565 79aceca5 bellard
/* extsh & extsh. */
566 79aceca5 bellard
GEN_LOGICAL1(extsh, 0x1C);
567 79aceca5 bellard
/* nand & nand. */
568 79aceca5 bellard
GEN_LOGICAL2(nand, 0x0E);
569 79aceca5 bellard
/* nor & nor. */
570 79aceca5 bellard
GEN_LOGICAL2(nor, 0x03);
571 9a64fbe4 bellard
572 79aceca5 bellard
/* or & or. */
573 9a64fbe4 bellard
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
574 9a64fbe4 bellard
{
575 9a64fbe4 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
576 9a64fbe4 bellard
    /* Optimisation for mr case */
577 9a64fbe4 bellard
    if (rS(ctx->opcode) != rB(ctx->opcode)) {
578 9a64fbe4 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
579 9a64fbe4 bellard
        gen_op_or();
580 9a64fbe4 bellard
    }
581 9a64fbe4 bellard
    if (Rc(ctx->opcode) != 0)
582 9a64fbe4 bellard
        gen_op_set_Rc0();
583 9a64fbe4 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
584 9a64fbe4 bellard
}
585 9a64fbe4 bellard
586 79aceca5 bellard
/* orc & orc. */
587 79aceca5 bellard
GEN_LOGICAL2(orc, 0x0C);
588 79aceca5 bellard
/* xor & xor. */
589 9a64fbe4 bellard
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
590 9a64fbe4 bellard
{
591 9a64fbe4 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
592 9a64fbe4 bellard
    /* Optimisation for "set to zero" case */
593 9a64fbe4 bellard
    if (rS(ctx->opcode) != rB(ctx->opcode)) {
594 9a64fbe4 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
595 9a64fbe4 bellard
        gen_op_xor();
596 9a64fbe4 bellard
    } else {
597 9a64fbe4 bellard
        gen_op_set_T0(0);
598 9a64fbe4 bellard
    }
599 9a64fbe4 bellard
    if (Rc(ctx->opcode) != 0)
600 9a64fbe4 bellard
        gen_op_set_Rc0();
601 9a64fbe4 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
602 9a64fbe4 bellard
}
603 79aceca5 bellard
/* ori */
604 79aceca5 bellard
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
605 79aceca5 bellard
{
606 79aceca5 bellard
    uint32_t uimm = UIMM(ctx->opcode);
607 79aceca5 bellard
608 9a64fbe4 bellard
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
609 9a64fbe4 bellard
        /* NOP */
610 9a64fbe4 bellard
        return;
611 79aceca5 bellard
        }
612 79aceca5 bellard
        gen_op_load_gpr_T0(rS(ctx->opcode));
613 9a64fbe4 bellard
    if (uimm != 0)
614 79aceca5 bellard
        gen_op_ori(uimm);
615 79aceca5 bellard
        gen_op_store_T0_gpr(rA(ctx->opcode));
616 79aceca5 bellard
}
617 79aceca5 bellard
/* oris */
618 79aceca5 bellard
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
619 79aceca5 bellard
{
620 79aceca5 bellard
    uint32_t uimm = UIMM(ctx->opcode);
621 79aceca5 bellard
622 9a64fbe4 bellard
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
623 9a64fbe4 bellard
        /* NOP */
624 9a64fbe4 bellard
        return;
625 79aceca5 bellard
        }
626 79aceca5 bellard
        gen_op_load_gpr_T0(rS(ctx->opcode));
627 9a64fbe4 bellard
    if (uimm != 0)
628 79aceca5 bellard
        gen_op_ori(uimm << 16);
629 79aceca5 bellard
        gen_op_store_T0_gpr(rA(ctx->opcode));
630 79aceca5 bellard
}
631 79aceca5 bellard
/* xori */
632 79aceca5 bellard
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
633 79aceca5 bellard
{
634 9a64fbe4 bellard
    uint32_t uimm = UIMM(ctx->opcode);
635 9a64fbe4 bellard
636 9a64fbe4 bellard
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
637 9a64fbe4 bellard
        /* NOP */
638 9a64fbe4 bellard
        return;
639 9a64fbe4 bellard
    }
640 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
641 9a64fbe4 bellard
    if (uimm != 0)
642 79aceca5 bellard
    gen_op_xori(UIMM(ctx->opcode));
643 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
644 79aceca5 bellard
}
645 79aceca5 bellard
646 79aceca5 bellard
/* xoris */
647 79aceca5 bellard
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
648 79aceca5 bellard
{
649 9a64fbe4 bellard
    uint32_t uimm = UIMM(ctx->opcode);
650 9a64fbe4 bellard
651 9a64fbe4 bellard
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
652 9a64fbe4 bellard
        /* NOP */
653 9a64fbe4 bellard
        return;
654 9a64fbe4 bellard
    }
655 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
656 9a64fbe4 bellard
    if (uimm != 0)
657 79aceca5 bellard
    gen_op_xori(UIMM(ctx->opcode) << 16);
658 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
659 79aceca5 bellard
}
660 79aceca5 bellard
661 79aceca5 bellard
/***                             Integer rotate                            ***/
662 79aceca5 bellard
/* rlwimi & rlwimi. */
663 79aceca5 bellard
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
664 79aceca5 bellard
{
665 79aceca5 bellard
    uint32_t mb, me;
666 79aceca5 bellard
667 79aceca5 bellard
    mb = MB(ctx->opcode);
668 79aceca5 bellard
    me = ME(ctx->opcode);
669 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
670 fb0eaffc bellard
    gen_op_load_gpr_T1(rA(ctx->opcode));
671 79aceca5 bellard
    gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
672 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)
673 79aceca5 bellard
        gen_op_set_Rc0();
674 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
675 79aceca5 bellard
}
676 79aceca5 bellard
/* rlwinm & rlwinm. */
677 79aceca5 bellard
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
678 79aceca5 bellard
{
679 79aceca5 bellard
    uint32_t mb, me, sh;
680 79aceca5 bellard
    
681 79aceca5 bellard
    sh = SH(ctx->opcode);
682 79aceca5 bellard
    mb = MB(ctx->opcode);
683 79aceca5 bellard
    me = ME(ctx->opcode);
684 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
685 79aceca5 bellard
    if (mb == 0) {
686 79aceca5 bellard
        if (me == 31) {
687 79aceca5 bellard
            gen_op_rotlwi(sh);
688 79aceca5 bellard
            goto store;
689 79aceca5 bellard
        } else if (me == (31 - sh)) {
690 79aceca5 bellard
            gen_op_slwi(sh);
691 79aceca5 bellard
            goto store;
692 79aceca5 bellard
        } else if (sh == 0) {
693 79aceca5 bellard
            gen_op_andi_(MASK(0, me));
694 79aceca5 bellard
            goto store;
695 79aceca5 bellard
        }
696 79aceca5 bellard
    } else if (me == 31) {
697 79aceca5 bellard
        if (sh == (32 - mb)) {
698 79aceca5 bellard
            gen_op_srwi(mb);
699 79aceca5 bellard
            goto store;
700 79aceca5 bellard
        } else if (sh == 0) {
701 79aceca5 bellard
            gen_op_andi_(MASK(mb, 31));
702 79aceca5 bellard
            goto store;
703 79aceca5 bellard
        }
704 79aceca5 bellard
    }
705 79aceca5 bellard
    gen_op_rlwinm(sh, MASK(mb, me));
706 79aceca5 bellard
store:
707 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)
708 79aceca5 bellard
        gen_op_set_Rc0();
709 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
710 79aceca5 bellard
}
711 79aceca5 bellard
/* rlwnm & rlwnm. */
712 79aceca5 bellard
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
713 79aceca5 bellard
{
714 79aceca5 bellard
    uint32_t mb, me;
715 79aceca5 bellard
716 79aceca5 bellard
    mb = MB(ctx->opcode);
717 79aceca5 bellard
    me = ME(ctx->opcode);
718 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
719 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));
720 79aceca5 bellard
    if (mb == 0 && me == 31) {
721 79aceca5 bellard
        gen_op_rotl();
722 79aceca5 bellard
    } else
723 79aceca5 bellard
    {
724 79aceca5 bellard
        gen_op_rlwnm(MASK(mb, me));
725 79aceca5 bellard
    }
726 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)
727 79aceca5 bellard
        gen_op_set_Rc0();
728 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
729 79aceca5 bellard
}
730 79aceca5 bellard
731 79aceca5 bellard
/***                             Integer shift                             ***/
732 79aceca5 bellard
/* slw & slw. */
733 79aceca5 bellard
__GEN_LOGICAL2(slw, 0x18, 0x00);
734 79aceca5 bellard
/* sraw & sraw. */
735 79aceca5 bellard
__GEN_LOGICAL2(sraw, 0x18, 0x18);
736 79aceca5 bellard
/* srawi & srawi. */
737 79aceca5 bellard
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
738 79aceca5 bellard
{
739 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
740 79aceca5 bellard
    gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
741 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)
742 79aceca5 bellard
        gen_op_set_Rc0();
743 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
744 79aceca5 bellard
}
745 79aceca5 bellard
/* srw & srw. */
746 79aceca5 bellard
__GEN_LOGICAL2(srw, 0x18, 0x10);
747 79aceca5 bellard
748 79aceca5 bellard
/***                       Floating-Point arithmetic                       ***/
749 9a64fbe4 bellard
#define _GEN_FLOAT_ACB(name, op1, op2)                                        \
750 9a64fbe4 bellard
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT)                   \
751 9a64fbe4 bellard
{                                                                             \
752 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
753 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
754 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
755 9a64fbe4 bellard
    gen_op_load_fpr_FT2(rB(ctx->opcode));                                     \
756 9a64fbe4 bellard
    gen_op_f##name();                                                         \
757 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
758 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
759 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
760 9a64fbe4 bellard
}
761 9a64fbe4 bellard
762 9a64fbe4 bellard
#define GEN_FLOAT_ACB(name, op2)                                              \
763 9a64fbe4 bellard
_GEN_FLOAT_ACB(name, 0x3F, op2);                                              \
764 9a64fbe4 bellard
_GEN_FLOAT_ACB(name##s, 0x3B, op2);
765 9a64fbe4 bellard
766 9a64fbe4 bellard
#define _GEN_FLOAT_AB(name, op1, op2, inval)                                  \
767 9a64fbe4 bellard
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \
768 9a64fbe4 bellard
{                                                                             \
769 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
770 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
771 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rB(ctx->opcode));                                     \
772 9a64fbe4 bellard
    gen_op_f##name();                                                         \
773 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
774 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
775 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
776 9a64fbe4 bellard
}
777 9a64fbe4 bellard
#define GEN_FLOAT_AB(name, op2, inval)                                        \
778 9a64fbe4 bellard
_GEN_FLOAT_AB(name, 0x3F, op2, inval);                                        \
779 9a64fbe4 bellard
_GEN_FLOAT_AB(name##s, 0x3B, op2, inval);
780 9a64fbe4 bellard
781 9a64fbe4 bellard
#define _GEN_FLOAT_AC(name, op1, op2, inval)                                  \
782 9a64fbe4 bellard
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \
783 9a64fbe4 bellard
{                                                                             \
784 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
785 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
786 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
787 9a64fbe4 bellard
    gen_op_f##name();                                                         \
788 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
789 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
790 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
791 9a64fbe4 bellard
}
792 9a64fbe4 bellard
#define GEN_FLOAT_AC(name, op2, inval)                                        \
793 9a64fbe4 bellard
_GEN_FLOAT_AC(name, 0x3F, op2, inval);                                        \
794 9a64fbe4 bellard
_GEN_FLOAT_AC(name##s, 0x3B, op2, inval);
795 9a64fbe4 bellard
796 9a64fbe4 bellard
#define GEN_FLOAT_B(name, op2, op3)                                           \
797 9a64fbe4 bellard
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT)                   \
798 9a64fbe4 bellard
{                                                                             \
799 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
800 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
801 9a64fbe4 bellard
    gen_op_f##name();                                                         \
802 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
803 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
804 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
805 79aceca5 bellard
}
806 79aceca5 bellard
807 9a64fbe4 bellard
#define GEN_FLOAT_BS(name, op2)                                               \
808 9a64fbe4 bellard
GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT)                  \
809 9a64fbe4 bellard
{                                                                             \
810 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
811 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
812 9a64fbe4 bellard
    gen_op_f##name();                                                         \
813 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
814 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
815 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
816 79aceca5 bellard
}
817 79aceca5 bellard
818 9a64fbe4 bellard
/* fadd - fadds */
819 9a64fbe4 bellard
GEN_FLOAT_AB(add, 0x15, 0x000007C0);
820 79aceca5 bellard
/* fdiv */
821 9a64fbe4 bellard
GEN_FLOAT_AB(div, 0x12, 0x000007C0);
822 79aceca5 bellard
/* fmul */
823 9a64fbe4 bellard
GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
824 79aceca5 bellard
825 79aceca5 bellard
/* fres */
826 9a64fbe4 bellard
GEN_FLOAT_BS(res, 0x18);
827 79aceca5 bellard
828 79aceca5 bellard
/* frsqrte */
829 9a64fbe4 bellard
GEN_FLOAT_BS(rsqrte, 0x1A);
830 79aceca5 bellard
831 79aceca5 bellard
/* fsel */
832 9a64fbe4 bellard
_GEN_FLOAT_ACB(sel, 0x3F, 0x17);
833 79aceca5 bellard
/* fsub */
834 9a64fbe4 bellard
GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
835 79aceca5 bellard
/* Optional: */
836 79aceca5 bellard
/* fsqrt */
837 9a64fbe4 bellard
GEN_FLOAT_BS(sqrt, 0x16);
838 79aceca5 bellard
839 9a64fbe4 bellard
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
840 79aceca5 bellard
{
841 9a64fbe4 bellard
    gen_op_reset_scrfx();
842 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));
843 9a64fbe4 bellard
    gen_op_fsqrts();
844 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));
845 9a64fbe4 bellard
    if (Rc(ctx->opcode))
846 9a64fbe4 bellard
        gen_op_set_Rc1();
847 79aceca5 bellard
}
848 79aceca5 bellard
849 79aceca5 bellard
/***                     Floating-Point multiply-and-add                   ***/
850 79aceca5 bellard
/* fmadd */
851 9a64fbe4 bellard
GEN_FLOAT_ACB(madd, 0x1D);
852 79aceca5 bellard
/* fmsub */
853 9a64fbe4 bellard
GEN_FLOAT_ACB(msub, 0x1C);
854 79aceca5 bellard
/* fnmadd */
855 9a64fbe4 bellard
GEN_FLOAT_ACB(nmadd, 0x1F);
856 79aceca5 bellard
/* fnmsub */
857 9a64fbe4 bellard
GEN_FLOAT_ACB(nmsub, 0x1E);
858 79aceca5 bellard
859 79aceca5 bellard
/***                     Floating-Point round & convert                    ***/
860 79aceca5 bellard
/* fctiw */
861 9a64fbe4 bellard
GEN_FLOAT_B(ctiw, 0x0E, 0x00);
862 79aceca5 bellard
/* fctiwz */
863 9a64fbe4 bellard
GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
864 79aceca5 bellard
/* frsp */
865 9a64fbe4 bellard
GEN_FLOAT_B(rsp, 0x0C, 0x00);
866 79aceca5 bellard
867 79aceca5 bellard
/***                         Floating-Point compare                        ***/
868 79aceca5 bellard
/* fcmpo */
869 79aceca5 bellard
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
870 79aceca5 bellard
{
871 9a64fbe4 bellard
    gen_op_reset_scrfx();
872 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));
873 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rB(ctx->opcode));
874 9a64fbe4 bellard
    gen_op_fcmpo();
875 9a64fbe4 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
876 79aceca5 bellard
}
877 79aceca5 bellard
878 79aceca5 bellard
/* fcmpu */
879 79aceca5 bellard
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
880 79aceca5 bellard
{
881 9a64fbe4 bellard
    gen_op_reset_scrfx();
882 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));
883 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rB(ctx->opcode));
884 9a64fbe4 bellard
    gen_op_fcmpu();
885 9a64fbe4 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
886 79aceca5 bellard
}
887 79aceca5 bellard
888 9a64fbe4 bellard
/***                         Floating-point move                           ***/
889 9a64fbe4 bellard
/* fabs */
890 9a64fbe4 bellard
GEN_FLOAT_B(abs, 0x08, 0x08);
891 9a64fbe4 bellard
892 9a64fbe4 bellard
/* fmr  - fmr. */
893 9a64fbe4 bellard
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
894 9a64fbe4 bellard
{
895 9a64fbe4 bellard
    gen_op_reset_scrfx();
896 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));
897 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));
898 9a64fbe4 bellard
    if (Rc(ctx->opcode))
899 9a64fbe4 bellard
        gen_op_set_Rc1();
900 9a64fbe4 bellard
}
901 9a64fbe4 bellard
902 9a64fbe4 bellard
/* fnabs */
903 9a64fbe4 bellard
GEN_FLOAT_B(nabs, 0x08, 0x04);
904 9a64fbe4 bellard
/* fneg */
905 9a64fbe4 bellard
GEN_FLOAT_B(neg, 0x08, 0x01);
906 9a64fbe4 bellard
907 79aceca5 bellard
/***                  Floating-Point status & ctrl register                ***/
908 79aceca5 bellard
/* mcrfs */
909 79aceca5 bellard
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
910 79aceca5 bellard
{
911 fb0eaffc bellard
    gen_op_load_fpscr_T0(crfS(ctx->opcode));
912 fb0eaffc bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
913 fb0eaffc bellard
    gen_op_clear_fpscr(crfS(ctx->opcode));
914 79aceca5 bellard
}
915 79aceca5 bellard
916 79aceca5 bellard
/* mffs */
917 79aceca5 bellard
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
918 79aceca5 bellard
{
919 28b6751f bellard
    gen_op_load_fpscr();
920 fb0eaffc bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));
921 fb0eaffc bellard
    if (Rc(ctx->opcode))
922 fb0eaffc bellard
        gen_op_set_Rc1();
923 79aceca5 bellard
}
924 79aceca5 bellard
925 79aceca5 bellard
/* mtfsb0 */
926 79aceca5 bellard
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
927 79aceca5 bellard
{
928 fb0eaffc bellard
    uint8_t crb;
929 fb0eaffc bellard
    
930 fb0eaffc bellard
    crb = crbD(ctx->opcode) >> 2;
931 fb0eaffc bellard
    gen_op_load_fpscr_T0(crb);
932 fb0eaffc bellard
    gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
933 fb0eaffc bellard
    gen_op_store_T0_fpscr(crb);
934 fb0eaffc bellard
    if (Rc(ctx->opcode))
935 fb0eaffc bellard
        gen_op_set_Rc1();
936 79aceca5 bellard
}
937 79aceca5 bellard
938 79aceca5 bellard
/* mtfsb1 */
939 79aceca5 bellard
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
940 79aceca5 bellard
{
941 fb0eaffc bellard
    uint8_t crb;
942 fb0eaffc bellard
    
943 fb0eaffc bellard
    crb = crbD(ctx->opcode) >> 2;
944 fb0eaffc bellard
    gen_op_load_fpscr_T0(crb);
945 fb0eaffc bellard
    gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
946 fb0eaffc bellard
    gen_op_store_T0_fpscr(crb);
947 fb0eaffc bellard
    if (Rc(ctx->opcode))
948 fb0eaffc bellard
        gen_op_set_Rc1();
949 79aceca5 bellard
}
950 79aceca5 bellard
951 79aceca5 bellard
/* mtfsf */
952 79aceca5 bellard
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
953 79aceca5 bellard
{
954 fb0eaffc bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));
955 28b6751f bellard
    gen_op_store_fpscr(FM(ctx->opcode));
956 fb0eaffc bellard
    if (Rc(ctx->opcode))
957 fb0eaffc bellard
        gen_op_set_Rc1();
958 79aceca5 bellard
}
959 79aceca5 bellard
960 79aceca5 bellard
/* mtfsfi */
961 79aceca5 bellard
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
962 79aceca5 bellard
{
963 fb0eaffc bellard
    gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
964 fb0eaffc bellard
    if (Rc(ctx->opcode))
965 fb0eaffc bellard
        gen_op_set_Rc1();
966 79aceca5 bellard
}
967 79aceca5 bellard
968 79aceca5 bellard
/***                             Integer load                              ***/
969 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
970 9a64fbe4 bellard
#define op_ldst(name)        gen_op_##name##_raw()
971 9a64fbe4 bellard
#define OP_LD_TABLE(width)
972 9a64fbe4 bellard
#define OP_ST_TABLE(width)
973 9a64fbe4 bellard
#else
974 9a64fbe4 bellard
#define op_ldst(name)        (*gen_op_##name[ctx->mem_idx])()
975 9a64fbe4 bellard
#define OP_LD_TABLE(width)                                                    \
976 9a64fbe4 bellard
static GenOpFunc *gen_op_l##width[] = {                                       \
977 9a64fbe4 bellard
    &gen_op_l##width##_user,                                                  \
978 9a64fbe4 bellard
    &gen_op_l##width##_kernel,                                                \
979 9a64fbe4 bellard
}
980 9a64fbe4 bellard
#define OP_ST_TABLE(width)                                                    \
981 9a64fbe4 bellard
static GenOpFunc *gen_op_st##width[] = {                                      \
982 9a64fbe4 bellard
    &gen_op_st##width##_user,                                                 \
983 9a64fbe4 bellard
    &gen_op_st##width##_kernel,                                               \
984 9a64fbe4 bellard
}
985 9a64fbe4 bellard
#endif
986 9a64fbe4 bellard
987 9a64fbe4 bellard
#define GEN_LD(width, opc)                                                    \
988 79aceca5 bellard
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)               \
989 79aceca5 bellard
{                                                                             \
990 79aceca5 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
991 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
992 9a64fbe4 bellard
        gen_op_set_T0(simm);                                                  \
993 79aceca5 bellard
    } else {                                                                  \
994 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
995 9a64fbe4 bellard
        if (simm != 0)                                                        \
996 9a64fbe4 bellard
            gen_op_addi(simm);                                                \
997 79aceca5 bellard
    }                                                                         \
998 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
999 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1000 79aceca5 bellard
}
1001 79aceca5 bellard
1002 9a64fbe4 bellard
#define GEN_LDU(width, opc)                                                   \
1003 79aceca5 bellard
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)            \
1004 79aceca5 bellard
{                                                                             \
1005 9a64fbe4 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1006 79aceca5 bellard
    if (rA(ctx->opcode) == 0 ||                                               \
1007 9a64fbe4 bellard
        rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1008 9a64fbe4 bellard
        RET_INVAL();                                                          \
1009 9a64fbe4 bellard
    }                                                                         \
1010 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1011 9a64fbe4 bellard
    if (simm != 0)                                                            \
1012 9a64fbe4 bellard
        gen_op_addi(simm);                                                    \
1013 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1014 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1015 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1016 79aceca5 bellard
}
1017 79aceca5 bellard
1018 9a64fbe4 bellard
#define GEN_LDUX(width, opc)                                                  \
1019 79aceca5 bellard
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER)           \
1020 79aceca5 bellard
{                                                                             \
1021 79aceca5 bellard
    if (rA(ctx->opcode) == 0 ||                                               \
1022 9a64fbe4 bellard
        rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1023 9a64fbe4 bellard
        RET_INVAL();                                                          \
1024 9a64fbe4 bellard
    }                                                                         \
1025 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1026 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1027 9a64fbe4 bellard
    gen_op_add();                                                             \
1028 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1029 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1030 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1031 79aceca5 bellard
}
1032 79aceca5 bellard
1033 9a64fbe4 bellard
#define GEN_LDX(width, opc2, opc3)                                            \
1034 79aceca5 bellard
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER)           \
1035 79aceca5 bellard
{                                                                             \
1036 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1037 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1038 79aceca5 bellard
    } else {                                                                  \
1039 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1040 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1041 9a64fbe4 bellard
        gen_op_add();                                                         \
1042 79aceca5 bellard
    }                                                                         \
1043 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1044 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1045 79aceca5 bellard
}
1046 79aceca5 bellard
1047 9a64fbe4 bellard
#define GEN_LDS(width, op)                                                    \
1048 9a64fbe4 bellard
OP_LD_TABLE(width);                                                           \
1049 9a64fbe4 bellard
GEN_LD(width, op | 0x20);                                                     \
1050 9a64fbe4 bellard
GEN_LDU(width, op | 0x21);                                                    \
1051 9a64fbe4 bellard
GEN_LDUX(width, op | 0x01);                                                   \
1052 9a64fbe4 bellard
GEN_LDX(width, 0x17, op | 0x00)
1053 79aceca5 bellard
1054 79aceca5 bellard
/* lbz lbzu lbzux lbzx */
1055 9a64fbe4 bellard
GEN_LDS(bz, 0x02);
1056 79aceca5 bellard
/* lha lhau lhaux lhax */
1057 9a64fbe4 bellard
GEN_LDS(ha, 0x0A);
1058 79aceca5 bellard
/* lhz lhzu lhzux lhzx */
1059 9a64fbe4 bellard
GEN_LDS(hz, 0x08);
1060 79aceca5 bellard
/* lwz lwzu lwzux lwzx */
1061 9a64fbe4 bellard
GEN_LDS(wz, 0x00);
1062 79aceca5 bellard
1063 79aceca5 bellard
/***                              Integer store                            ***/
1064 9a64fbe4 bellard
#define GEN_ST(width, opc)                                                    \
1065 79aceca5 bellard
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)              \
1066 79aceca5 bellard
{                                                                             \
1067 79aceca5 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1068 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1069 9a64fbe4 bellard
        gen_op_set_T0(simm);                                                  \
1070 79aceca5 bellard
    } else {                                                                  \
1071 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1072 9a64fbe4 bellard
        if (simm != 0)                                                        \
1073 9a64fbe4 bellard
            gen_op_addi(simm);                                                \
1074 79aceca5 bellard
    }                                                                         \
1075 9a64fbe4 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1076 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1077 79aceca5 bellard
}
1078 79aceca5 bellard
1079 9a64fbe4 bellard
#define GEN_STU(width, opc)                                                   \
1080 79aceca5 bellard
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)           \
1081 79aceca5 bellard
{                                                                             \
1082 9a64fbe4 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1083 9a64fbe4 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1084 9a64fbe4 bellard
        RET_INVAL();                                                          \
1085 9a64fbe4 bellard
    }                                                                         \
1086 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1087 9a64fbe4 bellard
    if (simm != 0)                                                            \
1088 9a64fbe4 bellard
        gen_op_addi(simm);                                                    \
1089 79aceca5 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1090 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1091 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1092 79aceca5 bellard
}
1093 79aceca5 bellard
1094 9a64fbe4 bellard
#define GEN_STUX(width, opc)                                                  \
1095 79aceca5 bellard
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER)          \
1096 79aceca5 bellard
{                                                                             \
1097 9a64fbe4 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1098 9a64fbe4 bellard
        RET_INVAL();                                                          \
1099 9a64fbe4 bellard
    }                                                                         \
1100 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1101 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1102 9a64fbe4 bellard
    gen_op_add();                                                             \
1103 9a64fbe4 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1104 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1105 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1106 79aceca5 bellard
}
1107 79aceca5 bellard
1108 9a64fbe4 bellard
#define GEN_STX(width, opc2, opc3)                                            \
1109 79aceca5 bellard
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER)          \
1110 79aceca5 bellard
{                                                                             \
1111 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1112 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1113 79aceca5 bellard
    } else {                                                                  \
1114 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1115 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1116 9a64fbe4 bellard
        gen_op_add();                                                         \
1117 79aceca5 bellard
    }                                                                         \
1118 9a64fbe4 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1119 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1120 79aceca5 bellard
}
1121 79aceca5 bellard
1122 9a64fbe4 bellard
#define GEN_STS(width, op)                                                    \
1123 9a64fbe4 bellard
OP_ST_TABLE(width);                                                           \
1124 9a64fbe4 bellard
GEN_ST(width, op | 0x20);                                                     \
1125 9a64fbe4 bellard
GEN_STU(width, op | 0x21);                                                    \
1126 9a64fbe4 bellard
GEN_STUX(width, op | 0x01);                                                   \
1127 9a64fbe4 bellard
GEN_STX(width, 0x17, op | 0x00)
1128 79aceca5 bellard
1129 79aceca5 bellard
/* stb stbu stbux stbx */
1130 9a64fbe4 bellard
GEN_STS(b, 0x06);
1131 79aceca5 bellard
/* sth sthu sthux sthx */
1132 9a64fbe4 bellard
GEN_STS(h, 0x0C);
1133 79aceca5 bellard
/* stw stwu stwux stwx */
1134 9a64fbe4 bellard
GEN_STS(w, 0x04);
1135 79aceca5 bellard
1136 79aceca5 bellard
/***                Integer load and store with byte reverse               ***/
1137 79aceca5 bellard
/* lhbrx */
1138 9a64fbe4 bellard
OP_LD_TABLE(hbr);
1139 9a64fbe4 bellard
GEN_LDX(hbr, 0x16, 0x18);
1140 79aceca5 bellard
/* lwbrx */
1141 9a64fbe4 bellard
OP_LD_TABLE(wbr);
1142 9a64fbe4 bellard
GEN_LDX(wbr, 0x16, 0x10);
1143 79aceca5 bellard
/* sthbrx */
1144 9a64fbe4 bellard
OP_ST_TABLE(hbr);
1145 9a64fbe4 bellard
GEN_STX(hbr, 0x16, 0x1C);
1146 79aceca5 bellard
/* stwbrx */
1147 9a64fbe4 bellard
OP_ST_TABLE(wbr);
1148 9a64fbe4 bellard
GEN_STX(wbr, 0x16, 0x14);
1149 79aceca5 bellard
1150 79aceca5 bellard
/***                    Integer load and store multiple                    ***/
1151 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1152 9a64fbe4 bellard
#define op_ldstm(name, reg) gen_op_##name##_raw(reg)
1153 9a64fbe4 bellard
#else
1154 9a64fbe4 bellard
#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1155 9a64fbe4 bellard
static GenOpFunc1 *gen_op_lmw[] = {
1156 9a64fbe4 bellard
    &gen_op_lmw_user,
1157 9a64fbe4 bellard
    &gen_op_lmw_kernel,
1158 9a64fbe4 bellard
};
1159 9a64fbe4 bellard
static GenOpFunc1 *gen_op_stmw[] = {
1160 9a64fbe4 bellard
    &gen_op_stmw_user,
1161 9a64fbe4 bellard
    &gen_op_stmw_kernel,
1162 9a64fbe4 bellard
};
1163 9a64fbe4 bellard
#endif
1164 9a64fbe4 bellard
1165 79aceca5 bellard
/* lmw */
1166 79aceca5 bellard
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1167 79aceca5 bellard
{
1168 9a64fbe4 bellard
    int simm = SIMM(ctx->opcode);
1169 9a64fbe4 bellard
1170 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
1171 9a64fbe4 bellard
        gen_op_set_T0(simm);
1172 79aceca5 bellard
    } else {
1173 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
1174 9a64fbe4 bellard
        if (simm != 0)
1175 9a64fbe4 bellard
            gen_op_addi(simm);
1176 79aceca5 bellard
    }
1177 9a64fbe4 bellard
    op_ldstm(lmw, rD(ctx->opcode));
1178 79aceca5 bellard
}
1179 79aceca5 bellard
1180 79aceca5 bellard
/* stmw */
1181 79aceca5 bellard
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1182 79aceca5 bellard
{
1183 9a64fbe4 bellard
    int simm = SIMM(ctx->opcode);
1184 9a64fbe4 bellard
1185 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
1186 9a64fbe4 bellard
        gen_op_set_T0(simm);
1187 79aceca5 bellard
    } else {
1188 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
1189 9a64fbe4 bellard
        if (simm != 0)
1190 9a64fbe4 bellard
            gen_op_addi(simm);
1191 79aceca5 bellard
    }
1192 9a64fbe4 bellard
    op_ldstm(stmw, rS(ctx->opcode));
1193 79aceca5 bellard
}
1194 79aceca5 bellard
1195 79aceca5 bellard
/***                    Integer load and store strings                     ***/
1196 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1197 9a64fbe4 bellard
#define op_ldsts(name, start) gen_op_##name##_raw(start)
1198 9a64fbe4 bellard
#define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb)
1199 9a64fbe4 bellard
#else
1200 9a64fbe4 bellard
#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1201 9a64fbe4 bellard
#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1202 9a64fbe4 bellard
static GenOpFunc1 *gen_op_lswi[] = {
1203 9a64fbe4 bellard
    &gen_op_lswi_user,
1204 9a64fbe4 bellard
    &gen_op_lswi_kernel,
1205 9a64fbe4 bellard
};
1206 9a64fbe4 bellard
static GenOpFunc3 *gen_op_lswx[] = {
1207 9a64fbe4 bellard
    &gen_op_lswx_user,
1208 9a64fbe4 bellard
    &gen_op_lswx_kernel,
1209 9a64fbe4 bellard
};
1210 9a64fbe4 bellard
static GenOpFunc1 *gen_op_stsw[] = {
1211 9a64fbe4 bellard
    &gen_op_stsw_user,
1212 9a64fbe4 bellard
    &gen_op_stsw_kernel,
1213 9a64fbe4 bellard
};
1214 9a64fbe4 bellard
#endif
1215 9a64fbe4 bellard
1216 79aceca5 bellard
/* lswi */
1217 9a64fbe4 bellard
/* PPC32 specification says we must generate an exception if
1218 9a64fbe4 bellard
 * rA is in the range of registers to be loaded.
1219 9a64fbe4 bellard
 * In an other hand, IBM says this is valid, but rA won't be loaded.
1220 9a64fbe4 bellard
 * For now, I'll follow the spec...
1221 9a64fbe4 bellard
 */
1222 79aceca5 bellard
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1223 79aceca5 bellard
{
1224 79aceca5 bellard
    int nb = NB(ctx->opcode);
1225 79aceca5 bellard
    int start = rD(ctx->opcode);
1226 9a64fbe4 bellard
    int ra = rA(ctx->opcode);
1227 79aceca5 bellard
    int nr;
1228 79aceca5 bellard
1229 79aceca5 bellard
    if (nb == 0)
1230 79aceca5 bellard
        nb = 32;
1231 79aceca5 bellard
    nr = nb / 4;
1232 9a64fbe4 bellard
    if (((start + nr) > 32  && start <= ra && (start + nr - 32) >= ra) ||
1233 9a64fbe4 bellard
        ((start + nr) <= 32 && start <= ra && (start + nr) >= ra)) {
1234 9a64fbe4 bellard
        RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1235 79aceca5 bellard
        }
1236 9a64fbe4 bellard
    if (ra == 0) {
1237 79aceca5 bellard
        gen_op_set_T0(0);
1238 79aceca5 bellard
    } else {
1239 9a64fbe4 bellard
        gen_op_load_gpr_T0(ra);
1240 79aceca5 bellard
    }
1241 9a64fbe4 bellard
    gen_op_set_T1(nb);
1242 9a64fbe4 bellard
    op_ldsts(lswi, start);
1243 79aceca5 bellard
}
1244 79aceca5 bellard
1245 79aceca5 bellard
/* lswx */
1246 79aceca5 bellard
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1247 79aceca5 bellard
{
1248 9a64fbe4 bellard
    int ra = rA(ctx->opcode);
1249 9a64fbe4 bellard
    int rb = rB(ctx->opcode);
1250 9a64fbe4 bellard
1251 9a64fbe4 bellard
    if (ra == 0) {
1252 9a64fbe4 bellard
        gen_op_load_gpr_T0(rb);
1253 9a64fbe4 bellard
        ra = rb;
1254 79aceca5 bellard
    } else {
1255 9a64fbe4 bellard
        gen_op_load_gpr_T0(ra);
1256 9a64fbe4 bellard
        gen_op_load_gpr_T1(rb);
1257 9a64fbe4 bellard
        gen_op_add();
1258 79aceca5 bellard
    }
1259 9a64fbe4 bellard
    gen_op_load_xer_bc();
1260 9a64fbe4 bellard
    op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
1261 79aceca5 bellard
}
1262 79aceca5 bellard
1263 79aceca5 bellard
/* stswi */
1264 79aceca5 bellard
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1265 79aceca5 bellard
{
1266 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
1267 79aceca5 bellard
        gen_op_set_T0(0);
1268 79aceca5 bellard
    } else {
1269 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
1270 79aceca5 bellard
    }
1271 9a64fbe4 bellard
    gen_op_set_T1(NB(ctx->opcode));
1272 9a64fbe4 bellard
    op_ldsts(stsw, rS(ctx->opcode));
1273 79aceca5 bellard
}
1274 79aceca5 bellard
1275 79aceca5 bellard
/* stswx */
1276 79aceca5 bellard
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1277 79aceca5 bellard
{
1278 9a64fbe4 bellard
    int ra = rA(ctx->opcode);
1279 9a64fbe4 bellard
1280 9a64fbe4 bellard
    if (ra == 0) {
1281 9a64fbe4 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));
1282 9a64fbe4 bellard
        ra = rB(ctx->opcode);
1283 79aceca5 bellard
    } else {
1284 9a64fbe4 bellard
        gen_op_load_gpr_T0(ra);
1285 9a64fbe4 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
1286 9a64fbe4 bellard
        gen_op_add();
1287 79aceca5 bellard
    }
1288 9a64fbe4 bellard
    gen_op_load_xer_bc();
1289 9a64fbe4 bellard
    op_ldsts(stsw, rS(ctx->opcode));
1290 79aceca5 bellard
}
1291 79aceca5 bellard
1292 79aceca5 bellard
/***                        Memory synchronisation                         ***/
1293 79aceca5 bellard
/* eieio */
1294 79aceca5 bellard
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1295 79aceca5 bellard
{
1296 79aceca5 bellard
}
1297 79aceca5 bellard
1298 79aceca5 bellard
/* isync */
1299 79aceca5 bellard
GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1300 79aceca5 bellard
{
1301 79aceca5 bellard
}
1302 79aceca5 bellard
1303 79aceca5 bellard
/* lwarx */
1304 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1305 9a64fbe4 bellard
#define op_stwcx() gen_op_stwcx_raw()
1306 9a64fbe4 bellard
#else
1307 9a64fbe4 bellard
#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1308 9a64fbe4 bellard
static GenOpFunc *gen_op_stwcx[] = {
1309 9a64fbe4 bellard
    &gen_op_stwcx_user,
1310 9a64fbe4 bellard
    &gen_op_stwcx_kernel,
1311 9a64fbe4 bellard
};
1312 9a64fbe4 bellard
#endif
1313 9a64fbe4 bellard
1314 9a64fbe4 bellard
GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
1315 79aceca5 bellard
{
1316 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
1317 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));
1318 79aceca5 bellard
    } else {
1319 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
1320 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
1321 9a64fbe4 bellard
        gen_op_add();
1322 79aceca5 bellard
    }
1323 9a64fbe4 bellard
    op_ldst(lwz);
1324 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));
1325 9a64fbe4 bellard
    gen_op_set_reservation();
1326 79aceca5 bellard
}
1327 79aceca5 bellard
1328 79aceca5 bellard
/* stwcx. */
1329 9a64fbe4 bellard
GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
1330 79aceca5 bellard
{
1331 79aceca5 bellard
        if (rA(ctx->opcode) == 0) {
1332 79aceca5 bellard
            gen_op_load_gpr_T0(rB(ctx->opcode));
1333 79aceca5 bellard
        } else {
1334 79aceca5 bellard
            gen_op_load_gpr_T0(rA(ctx->opcode));
1335 79aceca5 bellard
            gen_op_load_gpr_T1(rB(ctx->opcode));
1336 9a64fbe4 bellard
        gen_op_add();
1337 79aceca5 bellard
        }
1338 9a64fbe4 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));
1339 9a64fbe4 bellard
    op_stwcx();
1340 79aceca5 bellard
}
1341 79aceca5 bellard
1342 79aceca5 bellard
/* sync */
1343 79aceca5 bellard
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1344 79aceca5 bellard
{
1345 79aceca5 bellard
}
1346 79aceca5 bellard
1347 79aceca5 bellard
/***                         Floating-point load                           ***/
1348 9a64fbe4 bellard
#define GEN_LDF(width, opc)                                                   \
1349 9a64fbe4 bellard
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)               \
1350 79aceca5 bellard
{                                                                             \
1351 79aceca5 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1352 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1353 9a64fbe4 bellard
        gen_op_set_T0(simm);                                                  \
1354 79aceca5 bellard
    } else {                                                                  \
1355 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1356 9a64fbe4 bellard
        if (simm != 0)                                                        \
1357 9a64fbe4 bellard
            gen_op_addi(simm);                                                \
1358 79aceca5 bellard
    }                                                                         \
1359 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1360 9a64fbe4 bellard
    gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1361 79aceca5 bellard
}
1362 79aceca5 bellard
1363 9a64fbe4 bellard
#define GEN_LDUF(width, opc)                                                  \
1364 9a64fbe4 bellard
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)            \
1365 79aceca5 bellard
{                                                                             \
1366 9a64fbe4 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1367 79aceca5 bellard
    if (rA(ctx->opcode) == 0 ||                                               \
1368 9a64fbe4 bellard
        rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1369 9a64fbe4 bellard
        RET_INVAL();                                                          \
1370 9a64fbe4 bellard
    }                                                                         \
1371 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1372 9a64fbe4 bellard
    if (simm != 0)                                                            \
1373 9a64fbe4 bellard
        gen_op_addi(simm);                                                    \
1374 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1375 9a64fbe4 bellard
    gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1376 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1377 79aceca5 bellard
}
1378 79aceca5 bellard
1379 9a64fbe4 bellard
#define GEN_LDUXF(width, opc)                                                 \
1380 9a64fbe4 bellard
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER)           \
1381 79aceca5 bellard
{                                                                             \
1382 79aceca5 bellard
    if (rA(ctx->opcode) == 0 ||                                               \
1383 9a64fbe4 bellard
        rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1384 9a64fbe4 bellard
        RET_INVAL();                                                          \
1385 9a64fbe4 bellard
    }                                                                         \
1386 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1387 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1388 9a64fbe4 bellard
    gen_op_add();                                                             \
1389 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1390 9a64fbe4 bellard
    gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1391 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1392 79aceca5 bellard
}
1393 79aceca5 bellard
1394 9a64fbe4 bellard
#define GEN_LDXF(width, opc2, opc3)                                           \
1395 9a64fbe4 bellard
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER)           \
1396 79aceca5 bellard
{                                                                             \
1397 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1398 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1399 79aceca5 bellard
    } else {                                                                  \
1400 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1401 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1402 9a64fbe4 bellard
        gen_op_add();                                                         \
1403 79aceca5 bellard
    }                                                                         \
1404 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1405 9a64fbe4 bellard
    gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1406 79aceca5 bellard
}
1407 79aceca5 bellard
1408 9a64fbe4 bellard
#define GEN_LDFS(width, op)                                                   \
1409 9a64fbe4 bellard
OP_LD_TABLE(width);                                                           \
1410 9a64fbe4 bellard
GEN_LDF(width, op | 0x20);                                                    \
1411 9a64fbe4 bellard
GEN_LDUF(width, op | 0x21);                                                   \
1412 9a64fbe4 bellard
GEN_LDUXF(width, op | 0x01);                                                  \
1413 9a64fbe4 bellard
GEN_LDXF(width, 0x17, op | 0x00)
1414 79aceca5 bellard
1415 79aceca5 bellard
/* lfd lfdu lfdux lfdx */
1416 9a64fbe4 bellard
GEN_LDFS(fd, 0x12);
1417 79aceca5 bellard
/* lfs lfsu lfsux lfsx */
1418 9a64fbe4 bellard
GEN_LDFS(fs, 0x10);
1419 79aceca5 bellard
1420 79aceca5 bellard
/***                         Floating-point store                          ***/
1421 79aceca5 bellard
#define GEN_STF(width, opc)                                                   \
1422 9a64fbe4 bellard
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)              \
1423 79aceca5 bellard
{                                                                             \
1424 79aceca5 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1425 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1426 9a64fbe4 bellard
        gen_op_set_T0(simm);                                                  \
1427 79aceca5 bellard
    } else {                                                                  \
1428 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1429 9a64fbe4 bellard
        if (simm != 0)                                                        \
1430 9a64fbe4 bellard
            gen_op_addi(simm);                                                \
1431 79aceca5 bellard
    }                                                                         \
1432 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1433 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1434 79aceca5 bellard
}
1435 79aceca5 bellard
1436 9a64fbe4 bellard
#define GEN_STUF(width, opc)                                                  \
1437 9a64fbe4 bellard
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)           \
1438 79aceca5 bellard
{                                                                             \
1439 9a64fbe4 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1440 9a64fbe4 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1441 9a64fbe4 bellard
        RET_INVAL();                                                          \
1442 9a64fbe4 bellard
    }                                                                         \
1443 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1444 9a64fbe4 bellard
    if (simm != 0)                                                            \
1445 9a64fbe4 bellard
        gen_op_addi(simm);                                                    \
1446 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1447 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1448 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1449 79aceca5 bellard
}
1450 79aceca5 bellard
1451 9a64fbe4 bellard
#define GEN_STUXF(width, opc)                                                 \
1452 9a64fbe4 bellard
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER)          \
1453 79aceca5 bellard
{                                                                             \
1454 9a64fbe4 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1455 9a64fbe4 bellard
        RET_INVAL();                                                          \
1456 9a64fbe4 bellard
    }                                                                         \
1457 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1458 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1459 9a64fbe4 bellard
    gen_op_add();                                                             \
1460 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1461 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1462 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1463 79aceca5 bellard
}
1464 79aceca5 bellard
1465 9a64fbe4 bellard
#define GEN_STXF(width, opc2, opc3)                                           \
1466 9a64fbe4 bellard
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER)          \
1467 79aceca5 bellard
{                                                                             \
1468 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1469 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1470 79aceca5 bellard
    } else {                                                                  \
1471 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1472 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1473 9a64fbe4 bellard
        gen_op_add();                                                         \
1474 79aceca5 bellard
    }                                                                         \
1475 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1476 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1477 79aceca5 bellard
}
1478 79aceca5 bellard
1479 9a64fbe4 bellard
#define GEN_STFS(width, op)                                                   \
1480 9a64fbe4 bellard
OP_ST_TABLE(width);                                                           \
1481 9a64fbe4 bellard
GEN_STF(width, op | 0x20);                                                    \
1482 9a64fbe4 bellard
GEN_STUF(width, op | 0x21);                                                   \
1483 9a64fbe4 bellard
GEN_STUXF(width, op | 0x01);                                                  \
1484 9a64fbe4 bellard
GEN_STXF(width, 0x17, op | 0x00)
1485 79aceca5 bellard
1486 79aceca5 bellard
/* stfd stfdu stfdux stfdx */
1487 9a64fbe4 bellard
GEN_STFS(fd, 0x16);
1488 79aceca5 bellard
/* stfs stfsu stfsux stfsx */
1489 9a64fbe4 bellard
GEN_STFS(fs, 0x14);
1490 79aceca5 bellard
1491 79aceca5 bellard
/* Optional: */
1492 79aceca5 bellard
/* stfiwx */
1493 79aceca5 bellard
GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1494 79aceca5 bellard
{
1495 9a64fbe4 bellard
    RET_INVAL();
1496 79aceca5 bellard
}
1497 79aceca5 bellard
1498 79aceca5 bellard
/***                                Branch                                 ***/
1499 79aceca5 bellard
#define GEN_BCOND(name, opc1, opc2, opc3, prologue,                           \
1500 9a64fbe4 bellard
   bl_ctr,       b_ctr,       bl_ctrz,       b_ctrz,       b,        bl,      \
1501 79aceca5 bellard
   bl_ctr_true,  b_ctr_true,  bl_ctrz_true,  b_ctrz_true,  bl_true,  b_true,  \
1502 79aceca5 bellard
   bl_ctr_false, b_ctr_false, bl_ctrz_false, b_ctrz_false, bl_false, b_false) \
1503 79aceca5 bellard
GEN_HANDLER(name, opc1, opc2, opc3, 0x00000000, PPC_FLOW)                     \
1504 79aceca5 bellard
{                                                                             \
1505 79aceca5 bellard
    __attribute__ ((unused)) uint32_t target;                                 \
1506 79aceca5 bellard
    uint32_t bo = BO(ctx->opcode);                                            \
1507 79aceca5 bellard
    uint32_t bi = BI(ctx->opcode);                                            \
1508 79aceca5 bellard
    uint32_t mask;                                                            \
1509 9a64fbe4 bellard
    gen_op_update_tb(ctx->tb_offset);                                         \
1510 9a64fbe4 bellard
    gen_op_update_decr(ctx->decr_offset);                                     \
1511 9a64fbe4 bellard
    gen_op_process_exceptions((uint32_t)ctx->nip - 4);                        \
1512 79aceca5 bellard
    prologue;                                                                 \
1513 9a64fbe4 bellard
/*    gen_op_set_T1((uint32_t)ctx->tb);*/                                     \
1514 79aceca5 bellard
    if ((bo & 0x4) == 0)                                                      \
1515 79aceca5 bellard
        gen_op_dec_ctr();                                                     \
1516 79aceca5 bellard
    if (bo & 0x10) {                                                          \
1517 79aceca5 bellard
        /* No CR condition */                                                 \
1518 79aceca5 bellard
        switch (bo & 0x6) {                                                   \
1519 79aceca5 bellard
        case 0:                                                               \
1520 79aceca5 bellard
            if (LK(ctx->opcode)) {                                            \
1521 79aceca5 bellard
                bl_ctr;                                                       \
1522 79aceca5 bellard
            } else {                                                          \
1523 79aceca5 bellard
                b_ctr;                                                        \
1524 79aceca5 bellard
            }                                                                 \
1525 79aceca5 bellard
            break;                                                            \
1526 79aceca5 bellard
        case 2:                                                               \
1527 79aceca5 bellard
            if (LK(ctx->opcode)) {                                            \
1528 79aceca5 bellard
                bl_ctrz;                                                      \
1529 79aceca5 bellard
            } else {                                                          \
1530 79aceca5 bellard
                b_ctrz;                                                       \
1531 79aceca5 bellard
            }                                                                 \
1532 79aceca5 bellard
            break;                                                            \
1533 79aceca5 bellard
        case 4:                                                               \
1534 79aceca5 bellard
        case 6:                                                               \
1535 9a64fbe4 bellard
            if (LK(ctx->opcode)) {                                            \
1536 9a64fbe4 bellard
                bl;                                                           \
1537 9a64fbe4 bellard
            } else {                                                          \
1538 79aceca5 bellard
            b;                                                                \
1539 9a64fbe4 bellard
            }                                                                 \
1540 79aceca5 bellard
            break;                                                            \
1541 79aceca5 bellard
        default:                                                              \
1542 79aceca5 bellard
            printf("ERROR: %s: unhandled ba case (%d)\n", __func__, bo);      \
1543 9a64fbe4 bellard
            RET_INVAL();                                                      \
1544 79aceca5 bellard
            break;                                                            \
1545 79aceca5 bellard
        }                                                                     \
1546 79aceca5 bellard
    } else {                                                                  \
1547 79aceca5 bellard
        mask = 1 << (3 - (bi & 0x03));                                        \
1548 79aceca5 bellard
        gen_op_load_crf_T0(bi >> 2);                                          \
1549 79aceca5 bellard
        if (bo & 0x8) {                                                       \
1550 79aceca5 bellard
            switch (bo & 0x6) {                                               \
1551 79aceca5 bellard
            case 0:                                                           \
1552 79aceca5 bellard
                if (LK(ctx->opcode)) {                                        \
1553 79aceca5 bellard
                    bl_ctr_true;                                              \
1554 79aceca5 bellard
                } else {                                                      \
1555 79aceca5 bellard
                    b_ctr_true;                                               \
1556 79aceca5 bellard
                }                                                             \
1557 79aceca5 bellard
                break;                                                        \
1558 79aceca5 bellard
            case 2:                                                           \
1559 79aceca5 bellard
                if (LK(ctx->opcode)) {                                        \
1560 79aceca5 bellard
                    bl_ctrz_true;                                             \
1561 79aceca5 bellard
                } else {                                                      \
1562 79aceca5 bellard
                    b_ctrz_true;                                              \
1563 79aceca5 bellard
                }                                                             \
1564 79aceca5 bellard
                break;                                                        \
1565 79aceca5 bellard
            case 4:                                                           \
1566 79aceca5 bellard
            case 6:                                                           \
1567 79aceca5 bellard
                if (LK(ctx->opcode)) {                                        \
1568 79aceca5 bellard
                    bl_true;                                                  \
1569 79aceca5 bellard
                } else {                                                      \
1570 79aceca5 bellard
                    b_true;                                                   \
1571 79aceca5 bellard
                }                                                             \
1572 79aceca5 bellard
                break;                                                        \
1573 79aceca5 bellard
            default:                                                          \
1574 79aceca5 bellard
                printf("ERROR: %s: unhandled b case (%d)\n", __func__, bo);   \
1575 9a64fbe4 bellard
                RET_INVAL();                                                  \
1576 79aceca5 bellard
                break;                                                        \
1577 79aceca5 bellard
            }                                                                 \
1578 79aceca5 bellard
        } else {                                                              \
1579 79aceca5 bellard
            switch (bo & 0x6) {                                               \
1580 79aceca5 bellard
            case 0:                                                           \
1581 79aceca5 bellard
                if (LK(ctx->opcode)) {                                        \
1582 79aceca5 bellard
                    bl_ctr_false;                                             \
1583 79aceca5 bellard
                } else {                                                      \
1584 79aceca5 bellard
                    b_ctr_false;                                              \
1585 79aceca5 bellard
                }                                                             \
1586 79aceca5 bellard
                break;                                                        \
1587 79aceca5 bellard
            case 2:                                                           \
1588 79aceca5 bellard
                if (LK(ctx->opcode)) {                                        \
1589 79aceca5 bellard
                    bl_ctrz_false;                                            \
1590 79aceca5 bellard
                } else {                                                      \
1591 79aceca5 bellard
                    b_ctrz_false;                                             \
1592 79aceca5 bellard
                }                                                             \
1593 79aceca5 bellard
                break;                                                        \
1594 79aceca5 bellard
            case 4:                                                           \
1595 79aceca5 bellard
            case 6:                                                           \
1596 79aceca5 bellard
                if (LK(ctx->opcode)) {                                        \
1597 79aceca5 bellard
                    bl_false;                                                 \
1598 79aceca5 bellard
                } else {                                                      \
1599 79aceca5 bellard
                    b_false;                                                  \
1600 79aceca5 bellard
                }                                                             \
1601 79aceca5 bellard
                break;                                                        \
1602 79aceca5 bellard
            default:                                                          \
1603 79aceca5 bellard
                printf("ERROR: %s: unhandled bn case (%d)\n", __func__, bo);  \
1604 9a64fbe4 bellard
                RET_INVAL();                                                  \
1605 79aceca5 bellard
                break;                                                        \
1606 79aceca5 bellard
            }                                                                 \
1607 79aceca5 bellard
        }                                                                     \
1608 79aceca5 bellard
    }                                                                         \
1609 9a64fbe4 bellard
    ctx->exception = EXCP_BRANCH;                                             \
1610 79aceca5 bellard
}
1611 79aceca5 bellard
1612 79aceca5 bellard
/* b ba bl bla */
1613 79aceca5 bellard
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1614 79aceca5 bellard
{
1615 79aceca5 bellard
    uint32_t li = s_ext24(LI(ctx->opcode)), target;
1616 79aceca5 bellard
1617 9a64fbe4 bellard
    gen_op_update_tb(ctx->tb_offset);
1618 9a64fbe4 bellard
    gen_op_update_decr(ctx->decr_offset);
1619 9a64fbe4 bellard
    gen_op_process_exceptions((uint32_t)ctx->nip - 4);
1620 79aceca5 bellard
    if (AA(ctx->opcode) == 0)
1621 79aceca5 bellard
        target = (uint32_t)ctx->nip + li - 4;
1622 79aceca5 bellard
    else
1623 9a64fbe4 bellard
        target = li;
1624 9a64fbe4 bellard
//    gen_op_set_T1((uint32_t)ctx->tb);
1625 9a64fbe4 bellard
    if (LK(ctx->opcode)) {
1626 9a64fbe4 bellard
        gen_op_bl(target, (uint32_t)ctx->nip);
1627 9a64fbe4 bellard
    } else {
1628 79aceca5 bellard
    gen_op_b(target);
1629 9a64fbe4 bellard
    }
1630 9a64fbe4 bellard
    ctx->exception = EXCP_BRANCH;
1631 79aceca5 bellard
}
1632 79aceca5 bellard
1633 79aceca5 bellard
/* bc bca bcl bcla */
1634 79aceca5 bellard
GEN_BCOND(bc, 0x10, 0xFF, 0xFF,
1635 79aceca5 bellard
          do {
1636 79aceca5 bellard
              uint32_t li = s_ext16(BD(ctx->opcode));
1637 79aceca5 bellard
              if (AA(ctx->opcode) == 0) {
1638 79aceca5 bellard
                  target = (uint32_t)ctx->nip + li - 4;
1639 79aceca5 bellard
              } else {
1640 79aceca5 bellard
                  target = li;
1641 79aceca5 bellard
              }
1642 79aceca5 bellard
          } while (0),
1643 79aceca5 bellard
          gen_op_bl_ctr((uint32_t)ctx->nip, target),
1644 79aceca5 bellard
          gen_op_b_ctr((uint32_t)ctx->nip, target),
1645 79aceca5 bellard
          gen_op_bl_ctrz((uint32_t)ctx->nip, target),
1646 79aceca5 bellard
          gen_op_b_ctrz((uint32_t)ctx->nip, target),
1647 79aceca5 bellard
          gen_op_b(target),
1648 9a64fbe4 bellard
          gen_op_bl(target, (uint32_t)ctx->nip),
1649 79aceca5 bellard
          gen_op_bl_ctr_true((uint32_t)ctx->nip, target, mask),
1650 79aceca5 bellard
          gen_op_b_ctr_true((uint32_t)ctx->nip, target, mask),
1651 79aceca5 bellard
          gen_op_bl_ctrz_true((uint32_t)ctx->nip, target, mask),
1652 79aceca5 bellard
          gen_op_b_ctrz_true((uint32_t)ctx->nip, target, mask),
1653 79aceca5 bellard
          gen_op_bl_true((uint32_t)ctx->nip, target, mask),
1654 79aceca5 bellard
          gen_op_b_true((uint32_t)ctx->nip, target, mask),
1655 79aceca5 bellard
          gen_op_bl_ctr_false((uint32_t)ctx->nip, target, mask),
1656 79aceca5 bellard
          gen_op_b_ctr_false((uint32_t)ctx->nip, target, mask),
1657 79aceca5 bellard
          gen_op_bl_ctrz_false((uint32_t)ctx->nip, target, mask),
1658 79aceca5 bellard
          gen_op_b_ctrz_false((uint32_t)ctx->nip, target, mask),
1659 79aceca5 bellard
          gen_op_bl_false((uint32_t)ctx->nip, target, mask),
1660 79aceca5 bellard
          gen_op_b_false((uint32_t)ctx->nip, target, mask));
1661 79aceca5 bellard
1662 79aceca5 bellard
/* bcctr bcctrl */
1663 79aceca5 bellard
GEN_BCOND(bcctr, 0x13, 0x10, 0x10, do { } while (0),
1664 79aceca5 bellard
          gen_op_bctrl_ctr((uint32_t)ctx->nip),
1665 79aceca5 bellard
          gen_op_bctr_ctr((uint32_t)ctx->nip),
1666 79aceca5 bellard
          gen_op_bctrl_ctrz((uint32_t)ctx->nip),
1667 79aceca5 bellard
          gen_op_bctr_ctrz((uint32_t)ctx->nip),
1668 79aceca5 bellard
          gen_op_bctr(),
1669 9a64fbe4 bellard
          gen_op_bctrl((uint32_t)ctx->nip),
1670 79aceca5 bellard
          gen_op_bctrl_ctr_true((uint32_t)ctx->nip, mask),
1671 79aceca5 bellard
          gen_op_bctr_ctr_true((uint32_t)ctx->nip, mask),
1672 79aceca5 bellard
          gen_op_bctrl_ctrz_true((uint32_t)ctx->nip, mask),
1673 79aceca5 bellard
          gen_op_bctr_ctrz_true((uint32_t)ctx->nip, mask),
1674 79aceca5 bellard
          gen_op_bctrl_true((uint32_t)ctx->nip, mask),
1675 79aceca5 bellard
          gen_op_bctr_true((uint32_t)ctx->nip, mask),
1676 79aceca5 bellard
          gen_op_bctrl_ctr_false((uint32_t)ctx->nip, mask),
1677 79aceca5 bellard
          gen_op_bctr_ctr_false((uint32_t)ctx->nip, mask),
1678 79aceca5 bellard
          gen_op_bctrl_ctrz_false((uint32_t)ctx->nip, mask),
1679 79aceca5 bellard
          gen_op_bctr_ctrz_false((uint32_t)ctx->nip, mask),
1680 79aceca5 bellard
          gen_op_bctrl_false((uint32_t)ctx->nip, mask),
1681 79aceca5 bellard
          gen_op_bctr_false((uint32_t)ctx->nip, mask))
1682 79aceca5 bellard
1683 79aceca5 bellard
/* bclr bclrl */
1684 79aceca5 bellard
GEN_BCOND(bclr, 0x13, 0x10, 0x00, do { } while (0),
1685 79aceca5 bellard
          gen_op_blrl_ctr((uint32_t)ctx->nip),
1686 79aceca5 bellard
          gen_op_blr_ctr((uint32_t)ctx->nip),
1687 79aceca5 bellard
          gen_op_blrl_ctrz((uint32_t)ctx->nip),
1688 79aceca5 bellard
          gen_op_blr_ctrz((uint32_t)ctx->nip),
1689 79aceca5 bellard
          gen_op_blr(),
1690 9a64fbe4 bellard
          gen_op_blrl((uint32_t)ctx->nip),
1691 79aceca5 bellard
          gen_op_blrl_ctr_true((uint32_t)ctx->nip, mask),
1692 79aceca5 bellard
          gen_op_blr_ctr_true((uint32_t)ctx->nip, mask),
1693 79aceca5 bellard
          gen_op_blrl_ctrz_true((uint32_t)ctx->nip, mask),
1694 79aceca5 bellard
          gen_op_blr_ctrz_true((uint32_t)ctx->nip, mask),
1695 79aceca5 bellard
          gen_op_blrl_true((uint32_t)ctx->nip, mask),
1696 79aceca5 bellard
          gen_op_blr_true((uint32_t)ctx->nip, mask),
1697 79aceca5 bellard
          gen_op_blrl_ctr_false((uint32_t)ctx->nip, mask),
1698 79aceca5 bellard
          gen_op_blr_ctr_false((uint32_t)ctx->nip, mask),
1699 79aceca5 bellard
          gen_op_blrl_ctrz_false((uint32_t)ctx->nip, mask),
1700 79aceca5 bellard
          gen_op_blr_ctrz_false((uint32_t)ctx->nip, mask),
1701 79aceca5 bellard
          gen_op_blrl_false((uint32_t)ctx->nip, mask),
1702 79aceca5 bellard
          gen_op_blr_false((uint32_t)ctx->nip, mask))
1703 79aceca5 bellard
1704 79aceca5 bellard
/***                      Condition register logical                       ***/
1705 79aceca5 bellard
#define GEN_CRLOGIC(op, opc)                                                  \
1706 79aceca5 bellard
GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                 \
1707 79aceca5 bellard
{                                                                             \
1708 79aceca5 bellard
    gen_op_load_crf_T0(crbA(ctx->opcode) >> 2);                               \
1709 79aceca5 bellard
    gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03));                         \
1710 79aceca5 bellard
    gen_op_load_crf_T1(crbB(ctx->opcode) >> 2);                               \
1711 79aceca5 bellard
    gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03));                         \
1712 79aceca5 bellard
    gen_op_##op();                                                            \
1713 79aceca5 bellard
    gen_op_load_crf_T1(crbD(ctx->opcode) >> 2);                               \
1714 79aceca5 bellard
    gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))),                \
1715 79aceca5 bellard
                     3 - (crbD(ctx->opcode) & 0x03));                         \
1716 79aceca5 bellard
    gen_op_store_T1_crf(crbD(ctx->opcode) >> 2);                              \
1717 79aceca5 bellard
}
1718 79aceca5 bellard
1719 79aceca5 bellard
/* crand */
1720 79aceca5 bellard
GEN_CRLOGIC(and, 0x08)
1721 79aceca5 bellard
/* crandc */
1722 79aceca5 bellard
GEN_CRLOGIC(andc, 0x04)
1723 79aceca5 bellard
/* creqv */
1724 79aceca5 bellard
GEN_CRLOGIC(eqv, 0x09)
1725 79aceca5 bellard
/* crnand */
1726 79aceca5 bellard
GEN_CRLOGIC(nand, 0x07)
1727 79aceca5 bellard
/* crnor */
1728 79aceca5 bellard
GEN_CRLOGIC(nor, 0x01)
1729 79aceca5 bellard
/* cror */
1730 79aceca5 bellard
GEN_CRLOGIC(or, 0x0E)
1731 79aceca5 bellard
/* crorc */
1732 79aceca5 bellard
GEN_CRLOGIC(orc, 0x0D)
1733 79aceca5 bellard
/* crxor */
1734 79aceca5 bellard
GEN_CRLOGIC(xor, 0x06)
1735 79aceca5 bellard
/* mcrf */
1736 79aceca5 bellard
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1737 79aceca5 bellard
{
1738 79aceca5 bellard
    gen_op_load_crf_T0(crfS(ctx->opcode));
1739 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
1740 79aceca5 bellard
}
1741 79aceca5 bellard
1742 79aceca5 bellard
/***                           System linkage                              ***/
1743 79aceca5 bellard
/* rfi (supervisor only) */
1744 79aceca5 bellard
GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1745 79aceca5 bellard
{
1746 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1747 9a64fbe4 bellard
    RET_PRIVOPC();
1748 9a64fbe4 bellard
#else
1749 9a64fbe4 bellard
    /* Restore CPU state */
1750 9a64fbe4 bellard
    if (!ctx->supervisor) {
1751 9a64fbe4 bellard
        RET_PRIVOPC();
1752 9a64fbe4 bellard
    }
1753 9a64fbe4 bellard
    gen_op_rfi();
1754 9a64fbe4 bellard
    ctx->exception = EXCP_RFI;
1755 9a64fbe4 bellard
#endif
1756 79aceca5 bellard
}
1757 79aceca5 bellard
1758 79aceca5 bellard
/* sc */
1759 79aceca5 bellard
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1760 79aceca5 bellard
{
1761 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1762 9a64fbe4 bellard
    gen_op_queue_exception(EXCP_SYSCALL_USER);
1763 9a64fbe4 bellard
#else
1764 9a64fbe4 bellard
    gen_op_queue_exception(EXCP_SYSCALL);
1765 9a64fbe4 bellard
#endif
1766 9a64fbe4 bellard
    ctx->exception = EXCP_SYSCALL;
1767 79aceca5 bellard
}
1768 79aceca5 bellard
1769 79aceca5 bellard
/***                                Trap                                   ***/
1770 79aceca5 bellard
/* tw */
1771 79aceca5 bellard
GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1772 79aceca5 bellard
{
1773 9a64fbe4 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
1774 9a64fbe4 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));
1775 9a64fbe4 bellard
    gen_op_tw(TO(ctx->opcode));
1776 79aceca5 bellard
}
1777 79aceca5 bellard
1778 79aceca5 bellard
/* twi */
1779 79aceca5 bellard
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1780 79aceca5 bellard
{
1781 9a64fbe4 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
1782 9a64fbe4 bellard
#if 0
1783 9a64fbe4 bellard
    printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1784 9a64fbe4 bellard
           SIMM(ctx->opcode), TO(ctx->opcode));
1785 9a64fbe4 bellard
#endif
1786 9a64fbe4 bellard
    gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
1787 79aceca5 bellard
}
1788 79aceca5 bellard
1789 79aceca5 bellard
/***                          Processor control                            ***/
1790 79aceca5 bellard
static inline int check_spr_access (int spr, int rw, int supervisor)
1791 79aceca5 bellard
{
1792 79aceca5 bellard
    uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1793 79aceca5 bellard
1794 9a64fbe4 bellard
#if 0
1795 9a64fbe4 bellard
    if (spr != LR && spr != CTR) {
1796 9a64fbe4 bellard
    if (loglevel > 0) {
1797 9a64fbe4 bellard
        fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1798 9a64fbe4 bellard
                SPR_ENCODE(spr), supervisor, rw, rights,
1799 9a64fbe4 bellard
                (rights >> ((2 * supervisor) + rw)) & 1);
1800 9a64fbe4 bellard
    } else {
1801 9a64fbe4 bellard
        printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1802 9a64fbe4 bellard
               SPR_ENCODE(spr), supervisor, rw, rights,
1803 9a64fbe4 bellard
               (rights >> ((2 * supervisor) + rw)) & 1);
1804 9a64fbe4 bellard
    }
1805 9a64fbe4 bellard
    }
1806 9a64fbe4 bellard
#endif
1807 9a64fbe4 bellard
    if (rights == 0)
1808 9a64fbe4 bellard
        return -1;
1809 79aceca5 bellard
    rights = rights >> (2 * supervisor);
1810 79aceca5 bellard
    rights = rights >> rw;
1811 79aceca5 bellard
1812 79aceca5 bellard
    return rights & 1;
1813 79aceca5 bellard
}
1814 79aceca5 bellard
1815 79aceca5 bellard
/* mcrxr */
1816 79aceca5 bellard
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1817 79aceca5 bellard
{
1818 79aceca5 bellard
    gen_op_load_xer_cr();
1819 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
1820 79aceca5 bellard
    gen_op_clear_xer_cr();
1821 79aceca5 bellard
}
1822 79aceca5 bellard
1823 79aceca5 bellard
/* mfcr */
1824 79aceca5 bellard
GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1825 79aceca5 bellard
{
1826 79aceca5 bellard
    gen_op_load_cr();
1827 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
1828 79aceca5 bellard
}
1829 79aceca5 bellard
1830 79aceca5 bellard
/* mfmsr */
1831 79aceca5 bellard
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1832 79aceca5 bellard
{
1833 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1834 9a64fbe4 bellard
    RET_PRIVREG();
1835 9a64fbe4 bellard
#else
1836 9a64fbe4 bellard
    if (!ctx->supervisor) {
1837 9a64fbe4 bellard
        RET_PRIVREG();
1838 9a64fbe4 bellard
    }
1839 79aceca5 bellard
    gen_op_load_msr();
1840 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
1841 9a64fbe4 bellard
#endif
1842 79aceca5 bellard
}
1843 79aceca5 bellard
1844 79aceca5 bellard
/* mfspr */
1845 79aceca5 bellard
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1846 79aceca5 bellard
{
1847 79aceca5 bellard
    uint32_t sprn = SPR(ctx->opcode);
1848 79aceca5 bellard
1849 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1850 9a64fbe4 bellard
    switch (check_spr_access(sprn, 0, 0))
1851 9a64fbe4 bellard
#else
1852 9a64fbe4 bellard
    switch (check_spr_access(sprn, 0, ctx->supervisor))
1853 9a64fbe4 bellard
#endif
1854 9a64fbe4 bellard
    {
1855 9a64fbe4 bellard
    case -1:
1856 9a64fbe4 bellard
        RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1857 9a64fbe4 bellard
        break;
1858 9a64fbe4 bellard
    case 0:
1859 9a64fbe4 bellard
        RET_PRIVREG();
1860 9a64fbe4 bellard
        break;
1861 9a64fbe4 bellard
    default:
1862 9a64fbe4 bellard
        break;
1863 79aceca5 bellard
        }
1864 9a64fbe4 bellard
    switch (sprn) {
1865 9a64fbe4 bellard
    case XER:
1866 79aceca5 bellard
        gen_op_load_xer();
1867 79aceca5 bellard
        break;
1868 9a64fbe4 bellard
    case LR:
1869 9a64fbe4 bellard
        gen_op_load_lr();
1870 9a64fbe4 bellard
        break;
1871 9a64fbe4 bellard
    case CTR:
1872 9a64fbe4 bellard
        gen_op_load_ctr();
1873 9a64fbe4 bellard
        break;
1874 9a64fbe4 bellard
    case IBAT0U:
1875 9a64fbe4 bellard
        gen_op_load_ibat(0, 0);
1876 9a64fbe4 bellard
        break;
1877 9a64fbe4 bellard
    case IBAT1U:
1878 9a64fbe4 bellard
        gen_op_load_ibat(0, 1);
1879 9a64fbe4 bellard
        break;
1880 9a64fbe4 bellard
    case IBAT2U:
1881 9a64fbe4 bellard
        gen_op_load_ibat(0, 2);
1882 9a64fbe4 bellard
        break;
1883 9a64fbe4 bellard
    case IBAT3U:
1884 9a64fbe4 bellard
        gen_op_load_ibat(0, 3);
1885 9a64fbe4 bellard
        break;
1886 9a64fbe4 bellard
    case IBAT4U:
1887 9a64fbe4 bellard
        gen_op_load_ibat(0, 4);
1888 9a64fbe4 bellard
        break;
1889 9a64fbe4 bellard
    case IBAT5U:
1890 9a64fbe4 bellard
        gen_op_load_ibat(0, 5);
1891 9a64fbe4 bellard
        break;
1892 9a64fbe4 bellard
    case IBAT6U:
1893 9a64fbe4 bellard
        gen_op_load_ibat(0, 6);
1894 9a64fbe4 bellard
        break;
1895 9a64fbe4 bellard
    case IBAT7U:
1896 9a64fbe4 bellard
        gen_op_load_ibat(0, 7);
1897 9a64fbe4 bellard
        break;
1898 9a64fbe4 bellard
    case IBAT0L:
1899 9a64fbe4 bellard
        gen_op_load_ibat(1, 0);
1900 9a64fbe4 bellard
        break;
1901 9a64fbe4 bellard
    case IBAT1L:
1902 9a64fbe4 bellard
        gen_op_load_ibat(1, 1);
1903 9a64fbe4 bellard
        break;
1904 9a64fbe4 bellard
    case IBAT2L:
1905 9a64fbe4 bellard
        gen_op_load_ibat(1, 2);
1906 9a64fbe4 bellard
        break;
1907 9a64fbe4 bellard
    case IBAT3L:
1908 9a64fbe4 bellard
        gen_op_load_ibat(1, 3);
1909 9a64fbe4 bellard
        break;
1910 9a64fbe4 bellard
    case IBAT4L:
1911 9a64fbe4 bellard
        gen_op_load_ibat(1, 4);
1912 9a64fbe4 bellard
        break;
1913 9a64fbe4 bellard
    case IBAT5L:
1914 9a64fbe4 bellard
        gen_op_load_ibat(1, 5);
1915 9a64fbe4 bellard
        break;
1916 9a64fbe4 bellard
    case IBAT6L:
1917 9a64fbe4 bellard
        gen_op_load_ibat(1, 6);
1918 9a64fbe4 bellard
        break;
1919 9a64fbe4 bellard
    case IBAT7L:
1920 9a64fbe4 bellard
        gen_op_load_ibat(1, 7);
1921 9a64fbe4 bellard
        break;
1922 9a64fbe4 bellard
    case DBAT0U:
1923 9a64fbe4 bellard
        gen_op_load_dbat(0, 0);
1924 9a64fbe4 bellard
        break;
1925 9a64fbe4 bellard
    case DBAT1U:
1926 9a64fbe4 bellard
        gen_op_load_dbat(0, 1);
1927 9a64fbe4 bellard
        break;
1928 9a64fbe4 bellard
    case DBAT2U:
1929 9a64fbe4 bellard
        gen_op_load_dbat(0, 2);
1930 9a64fbe4 bellard
        break;
1931 9a64fbe4 bellard
    case DBAT3U:
1932 9a64fbe4 bellard
        gen_op_load_dbat(0, 3);
1933 9a64fbe4 bellard
        break;
1934 9a64fbe4 bellard
    case DBAT4U:
1935 9a64fbe4 bellard
        gen_op_load_dbat(0, 4);
1936 9a64fbe4 bellard
        break;
1937 9a64fbe4 bellard
    case DBAT5U:
1938 9a64fbe4 bellard
        gen_op_load_dbat(0, 5);
1939 9a64fbe4 bellard
        break;
1940 9a64fbe4 bellard
    case DBAT6U:
1941 9a64fbe4 bellard
        gen_op_load_dbat(0, 6);
1942 9a64fbe4 bellard
        break;
1943 9a64fbe4 bellard
    case DBAT7U:
1944 9a64fbe4 bellard
        gen_op_load_dbat(0, 7);
1945 9a64fbe4 bellard
        break;
1946 9a64fbe4 bellard
    case DBAT0L:
1947 9a64fbe4 bellard
        gen_op_load_dbat(1, 0);
1948 9a64fbe4 bellard
        break;
1949 9a64fbe4 bellard
    case DBAT1L:
1950 9a64fbe4 bellard
        gen_op_load_dbat(1, 1);
1951 9a64fbe4 bellard
        break;
1952 9a64fbe4 bellard
    case DBAT2L:
1953 9a64fbe4 bellard
        gen_op_load_dbat(1, 2);
1954 9a64fbe4 bellard
        break;
1955 9a64fbe4 bellard
    case DBAT3L:
1956 9a64fbe4 bellard
        gen_op_load_dbat(1, 3);
1957 9a64fbe4 bellard
        break;
1958 9a64fbe4 bellard
    case DBAT4L:
1959 9a64fbe4 bellard
        gen_op_load_dbat(1, 4);
1960 9a64fbe4 bellard
        break;
1961 9a64fbe4 bellard
    case DBAT5L:
1962 9a64fbe4 bellard
        gen_op_load_dbat(1, 5);
1963 9a64fbe4 bellard
        break;
1964 9a64fbe4 bellard
    case DBAT6L:
1965 9a64fbe4 bellard
        gen_op_load_dbat(1, 6);
1966 9a64fbe4 bellard
        break;
1967 9a64fbe4 bellard
    case DBAT7L:
1968 9a64fbe4 bellard
        gen_op_load_dbat(1, 7);
1969 9a64fbe4 bellard
        break;
1970 9a64fbe4 bellard
    case SDR1:
1971 9a64fbe4 bellard
        gen_op_load_sdr1();
1972 9a64fbe4 bellard
        break;
1973 9a64fbe4 bellard
    case V_TBL:
1974 79aceca5 bellard
        gen_op_update_tb(ctx->tb_offset);
1975 79aceca5 bellard
        ctx->tb_offset = 0;
1976 9a64fbe4 bellard
        /* TBL is still in T0 */
1977 79aceca5 bellard
        break;
1978 9a64fbe4 bellard
    case V_TBU:
1979 79aceca5 bellard
        gen_op_update_tb(ctx->tb_offset);
1980 79aceca5 bellard
        ctx->tb_offset = 0;
1981 9a64fbe4 bellard
        gen_op_load_tb(1);
1982 9a64fbe4 bellard
        break;
1983 9a64fbe4 bellard
    case DECR:
1984 9a64fbe4 bellard
        gen_op_update_decr(ctx->decr_offset);
1985 9a64fbe4 bellard
        ctx->decr_offset = 0;
1986 9a64fbe4 bellard
        /* decr is still in T0 */
1987 79aceca5 bellard
        break;
1988 79aceca5 bellard
    default:
1989 79aceca5 bellard
        gen_op_load_spr(sprn);
1990 79aceca5 bellard
        break;
1991 79aceca5 bellard
    }
1992 9a64fbe4 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
1993 79aceca5 bellard
}
1994 79aceca5 bellard
1995 79aceca5 bellard
/* mftb */
1996 79aceca5 bellard
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
1997 79aceca5 bellard
{
1998 79aceca5 bellard
    uint32_t sprn = SPR(ctx->opcode);
1999 79aceca5 bellard
2000 79aceca5 bellard
        /* We need to update the time base before reading it */
2001 9a64fbe4 bellard
    switch (sprn) {
2002 9a64fbe4 bellard
    case V_TBL:
2003 79aceca5 bellard
        gen_op_update_tb(ctx->tb_offset);
2004 9a64fbe4 bellard
        /* TBL is still in T0 */
2005 79aceca5 bellard
        break;
2006 9a64fbe4 bellard
    case V_TBU:
2007 79aceca5 bellard
        gen_op_update_tb(ctx->tb_offset);
2008 9a64fbe4 bellard
        gen_op_load_tb(1);
2009 79aceca5 bellard
        break;
2010 79aceca5 bellard
    default:
2011 9a64fbe4 bellard
        RET_INVAL();
2012 79aceca5 bellard
        break;
2013 79aceca5 bellard
    }
2014 9a64fbe4 bellard
    ctx->tb_offset = 0;
2015 9a64fbe4 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
2016 79aceca5 bellard
}
2017 79aceca5 bellard
2018 79aceca5 bellard
/* mtcrf */
2019 79aceca5 bellard
GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
2020 79aceca5 bellard
{
2021 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
2022 79aceca5 bellard
    gen_op_store_cr(CRM(ctx->opcode));
2023 79aceca5 bellard
}
2024 79aceca5 bellard
2025 79aceca5 bellard
/* mtmsr */
2026 79aceca5 bellard
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
2027 79aceca5 bellard
{
2028 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2029 9a64fbe4 bellard
    RET_PRIVREG();
2030 9a64fbe4 bellard
#else
2031 9a64fbe4 bellard
    if (!ctx->supervisor) {
2032 9a64fbe4 bellard
        RET_PRIVREG();
2033 9a64fbe4 bellard
    }
2034 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
2035 79aceca5 bellard
    gen_op_store_msr();
2036 79aceca5 bellard
    /* Must stop the translation as machine state (may have) changed */
2037 9a64fbe4 bellard
    ctx->exception = EXCP_MTMSR;
2038 9a64fbe4 bellard
#endif
2039 79aceca5 bellard
}
2040 79aceca5 bellard
2041 79aceca5 bellard
/* mtspr */
2042 79aceca5 bellard
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
2043 79aceca5 bellard
{
2044 79aceca5 bellard
    uint32_t sprn = SPR(ctx->opcode);
2045 79aceca5 bellard
2046 9a64fbe4 bellard
#if 0
2047 9a64fbe4 bellard
    if (loglevel > 0) {
2048 9a64fbe4 bellard
        fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
2049 9a64fbe4 bellard
                rS(ctx->opcode), sprn);
2050 9a64fbe4 bellard
    }
2051 9a64fbe4 bellard
#endif
2052 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2053 9a64fbe4 bellard
    switch (check_spr_access(sprn, 1, 0))
2054 9a64fbe4 bellard
#else
2055 9a64fbe4 bellard
    switch (check_spr_access(sprn, 1, ctx->supervisor))
2056 9a64fbe4 bellard
#endif
2057 9a64fbe4 bellard
    {
2058 9a64fbe4 bellard
    case -1:
2059 9a64fbe4 bellard
        RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2060 9a64fbe4 bellard
        break;
2061 9a64fbe4 bellard
    case 0:
2062 9a64fbe4 bellard
        RET_PRIVREG();
2063 9a64fbe4 bellard
        break;
2064 9a64fbe4 bellard
    default:
2065 9a64fbe4 bellard
        break;
2066 9a64fbe4 bellard
    }
2067 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
2068 9a64fbe4 bellard
    switch (sprn) {
2069 9a64fbe4 bellard
    case XER:
2070 79aceca5 bellard
        gen_op_store_xer();
2071 9a64fbe4 bellard
        break;
2072 9a64fbe4 bellard
    case LR:
2073 9a64fbe4 bellard
        gen_op_andi_(~0x03);
2074 9a64fbe4 bellard
        gen_op_store_lr();
2075 9a64fbe4 bellard
        break;
2076 9a64fbe4 bellard
    case CTR:
2077 9a64fbe4 bellard
        gen_op_store_ctr();
2078 9a64fbe4 bellard
        break;
2079 9a64fbe4 bellard
    case IBAT0U:
2080 9a64fbe4 bellard
        gen_op_store_ibat(0, 0);
2081 9a64fbe4 bellard
        gen_op_tlbia();
2082 9a64fbe4 bellard
        break;
2083 9a64fbe4 bellard
    case IBAT1U:
2084 9a64fbe4 bellard
        gen_op_store_ibat(0, 1);
2085 9a64fbe4 bellard
        gen_op_tlbia();
2086 9a64fbe4 bellard
        break;
2087 9a64fbe4 bellard
    case IBAT2U:
2088 9a64fbe4 bellard
        gen_op_store_ibat(0, 2);
2089 9a64fbe4 bellard
        gen_op_tlbia();
2090 9a64fbe4 bellard
        break;
2091 9a64fbe4 bellard
    case IBAT3U:
2092 9a64fbe4 bellard
        gen_op_store_ibat(0, 3);
2093 9a64fbe4 bellard
        gen_op_tlbia();
2094 9a64fbe4 bellard
        break;
2095 9a64fbe4 bellard
    case IBAT4U:
2096 9a64fbe4 bellard
        gen_op_store_ibat(0, 4);
2097 9a64fbe4 bellard
        gen_op_tlbia();
2098 9a64fbe4 bellard
        break;
2099 9a64fbe4 bellard
    case IBAT5U:
2100 9a64fbe4 bellard
        gen_op_store_ibat(0, 5);
2101 9a64fbe4 bellard
        gen_op_tlbia();
2102 9a64fbe4 bellard
        break;
2103 9a64fbe4 bellard
    case IBAT6U:
2104 9a64fbe4 bellard
        gen_op_store_ibat(0, 6);
2105 9a64fbe4 bellard
        gen_op_tlbia();
2106 9a64fbe4 bellard
        break;
2107 9a64fbe4 bellard
    case IBAT7U:
2108 9a64fbe4 bellard
        gen_op_store_ibat(0, 7);
2109 9a64fbe4 bellard
        gen_op_tlbia();
2110 9a64fbe4 bellard
        break;
2111 9a64fbe4 bellard
    case IBAT0L:
2112 9a64fbe4 bellard
        gen_op_store_ibat(1, 0);
2113 9a64fbe4 bellard
        gen_op_tlbia();
2114 9a64fbe4 bellard
        break;
2115 9a64fbe4 bellard
    case IBAT1L:
2116 9a64fbe4 bellard
        gen_op_store_ibat(1, 1);
2117 9a64fbe4 bellard
        gen_op_tlbia();
2118 9a64fbe4 bellard
        break;
2119 9a64fbe4 bellard
    case IBAT2L:
2120 9a64fbe4 bellard
        gen_op_store_ibat(1, 2);
2121 9a64fbe4 bellard
        gen_op_tlbia();
2122 9a64fbe4 bellard
        break;
2123 9a64fbe4 bellard
    case IBAT3L:
2124 9a64fbe4 bellard
        gen_op_store_ibat(1, 3);
2125 9a64fbe4 bellard
        gen_op_tlbia();
2126 9a64fbe4 bellard
        break;
2127 9a64fbe4 bellard
    case IBAT4L:
2128 9a64fbe4 bellard
        gen_op_store_ibat(1, 4);
2129 9a64fbe4 bellard
        gen_op_tlbia();
2130 9a64fbe4 bellard
        break;
2131 9a64fbe4 bellard
    case IBAT5L:
2132 9a64fbe4 bellard
        gen_op_store_ibat(1, 5);
2133 9a64fbe4 bellard
        gen_op_tlbia();
2134 9a64fbe4 bellard
        break;
2135 9a64fbe4 bellard
    case IBAT6L:
2136 9a64fbe4 bellard
        gen_op_store_ibat(1, 6);
2137 9a64fbe4 bellard
        gen_op_tlbia();
2138 9a64fbe4 bellard
        break;
2139 9a64fbe4 bellard
    case IBAT7L:
2140 9a64fbe4 bellard
        gen_op_store_ibat(1, 7);
2141 9a64fbe4 bellard
        gen_op_tlbia();
2142 9a64fbe4 bellard
        break;
2143 9a64fbe4 bellard
    case DBAT0U:
2144 9a64fbe4 bellard
        gen_op_store_dbat(0, 0);
2145 9a64fbe4 bellard
        gen_op_tlbia();
2146 9a64fbe4 bellard
        break;
2147 9a64fbe4 bellard
    case DBAT1U:
2148 9a64fbe4 bellard
        gen_op_store_dbat(0, 1);
2149 9a64fbe4 bellard
        gen_op_tlbia();
2150 9a64fbe4 bellard
        break;
2151 9a64fbe4 bellard
    case DBAT2U:
2152 9a64fbe4 bellard
        gen_op_store_dbat(0, 2);
2153 9a64fbe4 bellard
        gen_op_tlbia();
2154 9a64fbe4 bellard
        break;
2155 9a64fbe4 bellard
    case DBAT3U:
2156 9a64fbe4 bellard
        gen_op_store_dbat(0, 3);
2157 9a64fbe4 bellard
        gen_op_tlbia();
2158 9a64fbe4 bellard
        break;
2159 9a64fbe4 bellard
    case DBAT4U:
2160 9a64fbe4 bellard
        gen_op_store_dbat(0, 4);
2161 9a64fbe4 bellard
        gen_op_tlbia();
2162 9a64fbe4 bellard
        break;
2163 9a64fbe4 bellard
    case DBAT5U:
2164 9a64fbe4 bellard
        gen_op_store_dbat(0, 5);
2165 9a64fbe4 bellard
        gen_op_tlbia();
2166 9a64fbe4 bellard
        break;
2167 9a64fbe4 bellard
    case DBAT6U:
2168 9a64fbe4 bellard
        gen_op_store_dbat(0, 6);
2169 9a64fbe4 bellard
        gen_op_tlbia();
2170 9a64fbe4 bellard
        break;
2171 9a64fbe4 bellard
    case DBAT7U:
2172 9a64fbe4 bellard
        gen_op_store_dbat(0, 7);
2173 9a64fbe4 bellard
        gen_op_tlbia();
2174 9a64fbe4 bellard
        break;
2175 9a64fbe4 bellard
    case DBAT0L:
2176 9a64fbe4 bellard
        gen_op_store_dbat(1, 0);
2177 9a64fbe4 bellard
        gen_op_tlbia();
2178 9a64fbe4 bellard
        break;
2179 9a64fbe4 bellard
    case DBAT1L:
2180 9a64fbe4 bellard
        gen_op_store_dbat(1, 1);
2181 9a64fbe4 bellard
        gen_op_tlbia();
2182 9a64fbe4 bellard
        break;
2183 9a64fbe4 bellard
    case DBAT2L:
2184 9a64fbe4 bellard
        gen_op_store_dbat(1, 2);
2185 9a64fbe4 bellard
        gen_op_tlbia();
2186 9a64fbe4 bellard
        break;
2187 9a64fbe4 bellard
    case DBAT3L:
2188 9a64fbe4 bellard
        gen_op_store_dbat(1, 3);
2189 9a64fbe4 bellard
        gen_op_tlbia();
2190 9a64fbe4 bellard
        break;
2191 9a64fbe4 bellard
    case DBAT4L:
2192 9a64fbe4 bellard
        gen_op_store_dbat(1, 4);
2193 9a64fbe4 bellard
        gen_op_tlbia();
2194 9a64fbe4 bellard
        break;
2195 9a64fbe4 bellard
    case DBAT5L:
2196 9a64fbe4 bellard
        gen_op_store_dbat(1, 5);
2197 9a64fbe4 bellard
        gen_op_tlbia();
2198 9a64fbe4 bellard
        break;
2199 9a64fbe4 bellard
    case DBAT6L:
2200 9a64fbe4 bellard
        gen_op_store_dbat(1, 6);
2201 9a64fbe4 bellard
        gen_op_tlbia();
2202 9a64fbe4 bellard
        break;
2203 9a64fbe4 bellard
    case DBAT7L:
2204 9a64fbe4 bellard
        gen_op_store_dbat(1, 7);
2205 9a64fbe4 bellard
        gen_op_tlbia();
2206 9a64fbe4 bellard
        break;
2207 9a64fbe4 bellard
    case SDR1:
2208 9a64fbe4 bellard
        gen_op_store_sdr1();
2209 9a64fbe4 bellard
        gen_op_tlbia();
2210 9a64fbe4 bellard
        break;
2211 9a64fbe4 bellard
    case O_TBL:
2212 9a64fbe4 bellard
        gen_op_store_tb(0);
2213 9a64fbe4 bellard
        ctx->tb_offset = 0;
2214 9a64fbe4 bellard
        break;
2215 9a64fbe4 bellard
    case O_TBU:
2216 9a64fbe4 bellard
        gen_op_store_tb(1);
2217 9a64fbe4 bellard
        ctx->tb_offset = 0;
2218 9a64fbe4 bellard
        break;
2219 9a64fbe4 bellard
    case DECR:
2220 9a64fbe4 bellard
        gen_op_store_decr();
2221 9a64fbe4 bellard
        ctx->decr_offset = 0;
2222 9a64fbe4 bellard
        break;
2223 9a64fbe4 bellard
    default:
2224 79aceca5 bellard
        gen_op_store_spr(sprn);
2225 9a64fbe4 bellard
        break;
2226 79aceca5 bellard
    }
2227 79aceca5 bellard
}
2228 79aceca5 bellard
2229 79aceca5 bellard
/***                         Cache management                              ***/
2230 79aceca5 bellard
/* For now, all those will be implemented as nop:
2231 79aceca5 bellard
 * this is valid, regarding the PowerPC specs...
2232 9a64fbe4 bellard
 * We just have to flush tb while invalidating instruction cache lines...
2233 79aceca5 bellard
 */
2234 79aceca5 bellard
/* dcbf */
2235 9a64fbe4 bellard
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
2236 79aceca5 bellard
{
2237 79aceca5 bellard
}
2238 79aceca5 bellard
2239 79aceca5 bellard
/* dcbi (Supervisor only) */
2240 9a64fbe4 bellard
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
2241 79aceca5 bellard
{
2242 9a64fbe4 bellard
#if !defined(CONFIG_USER_ONLY)
2243 9a64fbe4 bellard
    if (!ctx->supervisor)
2244 9a64fbe4 bellard
#endif
2245 9a64fbe4 bellard
    {
2246 9a64fbe4 bellard
        RET_PRIVOPC();
2247 9a64fbe4 bellard
    }
2248 79aceca5 bellard
}
2249 79aceca5 bellard
2250 79aceca5 bellard
/* dcdst */
2251 9a64fbe4 bellard
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
2252 79aceca5 bellard
{
2253 79aceca5 bellard
}
2254 79aceca5 bellard
2255 79aceca5 bellard
/* dcbt */
2256 9a64fbe4 bellard
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
2257 79aceca5 bellard
{
2258 79aceca5 bellard
}
2259 79aceca5 bellard
2260 79aceca5 bellard
/* dcbtst */
2261 9a64fbe4 bellard
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
2262 79aceca5 bellard
{
2263 79aceca5 bellard
}
2264 79aceca5 bellard
2265 79aceca5 bellard
/* dcbz */
2266 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2267 9a64fbe4 bellard
#define op_dcbz() gen_op_dcbz_raw()
2268 9a64fbe4 bellard
#else
2269 9a64fbe4 bellard
#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2270 9a64fbe4 bellard
static GenOpFunc *gen_op_dcbz[] = {
2271 9a64fbe4 bellard
    &gen_op_dcbz_user,
2272 9a64fbe4 bellard
    &gen_op_dcbz_kernel,
2273 9a64fbe4 bellard
};
2274 9a64fbe4 bellard
#endif
2275 9a64fbe4 bellard
2276 9a64fbe4 bellard
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
2277 79aceca5 bellard
{
2278 fb0eaffc bellard
    if (rA(ctx->opcode) == 0) {
2279 fb0eaffc bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));
2280 fb0eaffc bellard
    } else {
2281 fb0eaffc bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
2282 fb0eaffc bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
2283 9a64fbe4 bellard
        gen_op_add();
2284 fb0eaffc bellard
    }
2285 9a64fbe4 bellard
    op_dcbz();
2286 79aceca5 bellard
}
2287 79aceca5 bellard
2288 79aceca5 bellard
/* icbi */
2289 9a64fbe4 bellard
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
2290 79aceca5 bellard
{
2291 fb0eaffc bellard
    if (rA(ctx->opcode) == 0) {
2292 fb0eaffc bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));
2293 fb0eaffc bellard
    } else {
2294 fb0eaffc bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
2295 fb0eaffc bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
2296 9a64fbe4 bellard
        gen_op_add();
2297 fb0eaffc bellard
    }
2298 9a64fbe4 bellard
    gen_op_icbi();
2299 79aceca5 bellard
}
2300 79aceca5 bellard
2301 79aceca5 bellard
/* Optional: */
2302 79aceca5 bellard
/* dcba */
2303 9a64fbe4 bellard
GEN_HANDLER(dcba, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE_OPT)
2304 79aceca5 bellard
{
2305 79aceca5 bellard
}
2306 79aceca5 bellard
2307 79aceca5 bellard
/***                    Segment register manipulation                      ***/
2308 79aceca5 bellard
/* Supervisor only: */
2309 79aceca5 bellard
/* mfsr */
2310 79aceca5 bellard
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2311 79aceca5 bellard
{
2312 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2313 9a64fbe4 bellard
    RET_PRIVREG();
2314 9a64fbe4 bellard
#else
2315 9a64fbe4 bellard
    if (!ctx->supervisor) {
2316 9a64fbe4 bellard
        RET_PRIVREG();
2317 9a64fbe4 bellard
    }
2318 9a64fbe4 bellard
    gen_op_load_sr(SR(ctx->opcode));
2319 9a64fbe4 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
2320 9a64fbe4 bellard
#endif
2321 79aceca5 bellard
}
2322 79aceca5 bellard
2323 79aceca5 bellard
/* mfsrin */
2324 9a64fbe4 bellard
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
2325 79aceca5 bellard
{
2326 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2327 9a64fbe4 bellard
    RET_PRIVREG();
2328 9a64fbe4 bellard
#else
2329 9a64fbe4 bellard
    if (!ctx->supervisor) {
2330 9a64fbe4 bellard
        RET_PRIVREG();
2331