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/*
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* Copyright (C) 2010 Red Hat, Inc.
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*
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* written by Gerd Hoffmann <kraxel@redhat.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "msi.h" |
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#include "qemu-timer.h" |
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#include "audiodev.h" |
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#include "intel-hda.h" |
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#include "intel-hda-defs.h" |
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|
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/* --------------------------------------------------------------------- */
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/* hda bus */
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static struct BusInfo hda_codec_bus_info = { |
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.name = "HDA",
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.size = sizeof(HDACodecBus),
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.props = (Property[]) { |
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DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), |
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DEFINE_PROP_END_OF_LIST() |
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} |
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}; |
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void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
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hda_codec_response_func response, |
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hda_codec_xfer_func xfer) |
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{ |
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qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL);
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bus->response = response; |
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bus->xfer = xfer; |
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} |
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|
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static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo *base) |
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{ |
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HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus); |
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HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
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HDACodecDeviceInfo *info = DO_UPCAST(HDACodecDeviceInfo, qdev, base); |
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dev->info = info; |
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if (dev->cad == -1) { |
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dev->cad = bus->next_cad; |
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} |
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if (dev->cad >= 15) |
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return -1; |
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bus->next_cad = dev->cad + 1;
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return info->init(dev);
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} |
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|
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static int hda_codec_dev_exit(DeviceState *qdev) |
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{ |
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HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
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if (dev->info->exit) {
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dev->info->exit(dev); |
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} |
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return 0; |
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} |
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void hda_codec_register(HDACodecDeviceInfo *info)
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{ |
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info->qdev.init = hda_codec_dev_init; |
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info->qdev.exit = hda_codec_dev_exit; |
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info->qdev.bus_info = &hda_codec_bus_info; |
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qdev_register(&info->qdev); |
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} |
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|
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HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) |
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{ |
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DeviceState *qdev; |
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HDACodecDevice *cdev; |
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QLIST_FOREACH(qdev, &bus->qbus.children, sibling) { |
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cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
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if (cdev->cad == cad) {
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return cdev;
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} |
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} |
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return NULL; |
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} |
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void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) |
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{ |
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HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
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bus->response(dev, solicited, response); |
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} |
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|
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bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, |
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uint8_t *buf, uint32_t len) |
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{ |
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HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
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return bus->xfer(dev, stnr, output, buf, len);
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} |
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|
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/* --------------------------------------------------------------------- */
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/* intel hda emulation */
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|
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typedef struct IntelHDAStream IntelHDAStream; |
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typedef struct IntelHDAState IntelHDAState; |
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typedef struct IntelHDAReg IntelHDAReg; |
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|
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typedef struct bpl { |
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uint64_t addr; |
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uint32_t len; |
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uint32_t flags; |
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} bpl; |
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struct IntelHDAStream {
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/* registers */
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uint32_t ctl; |
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uint32_t lpib; |
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uint32_t cbl; |
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uint32_t lvi; |
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uint32_t fmt; |
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uint32_t bdlp_lbase; |
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uint32_t bdlp_ubase; |
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/* state */
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bpl *bpl; |
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uint32_t bentries; |
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uint32_t bsize, be, bp; |
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}; |
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struct IntelHDAState {
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PCIDevice pci; |
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const char *name; |
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HDACodecBus codecs; |
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|
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/* registers */
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uint32_t g_ctl; |
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uint32_t wake_en; |
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uint32_t state_sts; |
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uint32_t int_ctl; |
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uint32_t int_sts; |
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uint32_t wall_clk; |
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uint32_t corb_lbase; |
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uint32_t corb_ubase; |
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uint32_t corb_rp; |
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uint32_t corb_wp; |
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uint32_t corb_ctl; |
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uint32_t corb_sts; |
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uint32_t corb_size; |
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uint32_t rirb_lbase; |
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uint32_t rirb_ubase; |
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uint32_t rirb_wp; |
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uint32_t rirb_cnt; |
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uint32_t rirb_ctl; |
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uint32_t rirb_sts; |
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uint32_t rirb_size; |
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uint32_t dp_lbase; |
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uint32_t dp_ubase; |
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uint32_t icw; |
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uint32_t irr; |
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uint32_t ics; |
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/* streams */
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IntelHDAStream st[8];
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/* state */
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int mmio_addr;
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uint32_t rirb_count; |
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int64_t wall_base_ns; |
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/* debug logging */
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const IntelHDAReg *last_reg;
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uint32_t last_val; |
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uint32_t last_write; |
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uint32_t last_sec; |
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uint32_t repeat_count; |
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/* properties */
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uint32_t debug; |
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uint32_t msi; |
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}; |
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struct IntelHDAReg {
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const char *name; /* register name */ |
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uint32_t size; /* size in bytes */
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uint32_t reset; /* reset value */
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uint32_t wmask; /* write mask */
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uint32_t wclear; /* write 1 to clear bits */
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uint32_t offset; /* location in IntelHDAState */
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uint32_t shift; /* byte access entries for dwords */
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uint32_t stream; |
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void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); |
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void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); |
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}; |
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static void intel_hda_reset(DeviceState *dev); |
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/* --------------------------------------------------------------------- */
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static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
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{ |
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target_phys_addr_t addr; |
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#if TARGET_PHYS_ADDR_BITS == 32 |
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addr = lbase; |
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#else
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addr = ubase; |
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addr <<= 32;
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addr |= lbase; |
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#endif
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return addr;
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} |
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static void stl_phys_le(target_phys_addr_t addr, uint32_t value) |
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{ |
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uint32_t value_le = cpu_to_le32(value); |
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cpu_physical_memory_write(addr, (uint8_t*)(&value_le), sizeof(value_le));
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} |
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static uint32_t ldl_phys_le(target_phys_addr_t addr)
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{ |
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uint32_t value_le; |
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cpu_physical_memory_read(addr, (uint8_t*)(&value_le), sizeof(value_le));
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return le32_to_cpu(value_le);
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} |
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static void intel_hda_update_int_sts(IntelHDAState *d) |
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{ |
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uint32_t sts = 0;
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uint32_t i; |
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/* update controller status */
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if (d->rirb_sts & ICH6_RBSTS_IRQ) {
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sts |= (1 << 30); |
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} |
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if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
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sts |= (1 << 30); |
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} |
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if (d->state_sts & d->wake_en) {
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sts |= (1 << 30); |
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} |
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/* update stream status */
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for (i = 0; i < 8; i++) { |
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/* buffer completion interrupt */
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if (d->st[i].ctl & (1 << 26)) { |
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sts |= (1 << i);
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} |
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} |
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/* update global status */
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if (sts & d->int_ctl) {
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sts |= (1 << 31); |
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} |
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d->int_sts = sts; |
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} |
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static void intel_hda_update_irq(IntelHDAState *d) |
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{ |
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int msi = d->msi && msi_enabled(&d->pci);
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int level;
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intel_hda_update_int_sts(d); |
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if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) { |
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level = 1;
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} else {
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level = 0;
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} |
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dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__, |
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level, msi ? "msi" : "intx"); |
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if (msi) {
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if (level) {
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msi_notify(&d->pci, 0);
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} |
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} else {
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qemu_set_irq(d->pci.irq[0], level);
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} |
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} |
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static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) |
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{ |
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uint32_t cad, nid, data; |
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HDACodecDevice *codec; |
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cad = (verb >> 28) & 0x0f; |
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if (verb & (1 << 27)) { |
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/* indirect node addressing, not specified in HDA 1.0 */
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dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__); |
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return -1; |
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} |
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nid = (verb >> 20) & 0x7f; |
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data = verb & 0xfffff;
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|
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codec = hda_codec_find(&d->codecs, cad); |
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if (codec == NULL) { |
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dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__); |
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return -1; |
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} |
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codec->info->command(codec, nid, data); |
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return 0; |
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} |
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|
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static void intel_hda_corb_run(IntelHDAState *d) |
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{ |
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target_phys_addr_t addr; |
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uint32_t rp, verb; |
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|
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if (d->ics & ICH6_IRS_BUSY) {
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dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw); |
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intel_hda_send_command(d, d->icw); |
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return;
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} |
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|
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for (;;) {
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if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
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dprint(d, 2, "%s: !run\n", __FUNCTION__); |
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return;
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} |
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if ((d->corb_rp & 0xff) == d->corb_wp) { |
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dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__); |
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return;
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} |
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if (d->rirb_count == d->rirb_cnt) {
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dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__); |
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return;
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} |
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rp = (d->corb_rp + 1) & 0xff; |
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addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); |
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verb = ldl_phys_le(addr + 4*rp);
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d->corb_rp = rp; |
345 |
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dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb); |
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intel_hda_send_command(d, verb); |
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} |
349 |
} |
350 |
|
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static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) |
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{ |
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HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
354 |
IntelHDAState *d = container_of(bus, IntelHDAState, codecs); |
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target_phys_addr_t addr; |
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uint32_t wp, ex; |
357 |
|
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if (d->ics & ICH6_IRS_BUSY) {
|
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dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", |
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__FUNCTION__, response, dev->cad); |
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d->irr = response; |
362 |
d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
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d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
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return;
|
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} |
366 |
|
367 |
if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
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dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__); |
369 |
return;
|
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} |
371 |
|
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ex = (solicited ? 0 : (1 << 4)) | dev->cad; |
373 |
wp = (d->rirb_wp + 1) & 0xff; |
374 |
addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); |
375 |
stl_phys_le(addr + 8*wp, response);
|
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stl_phys_le(addr + 8*wp + 4, ex); |
377 |
d->rirb_wp = wp; |
378 |
|
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dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", |
380 |
__FUNCTION__, wp, response, ex); |
381 |
|
382 |
d->rirb_count++; |
383 |
if (d->rirb_count == d->rirb_cnt) {
|
384 |
dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count); |
385 |
if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
|
386 |
d->rirb_sts |= ICH6_RBSTS_IRQ; |
387 |
intel_hda_update_irq(d); |
388 |
} |
389 |
} else if ((d->corb_rp & 0xff) == d->corb_wp) { |
390 |
dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__, |
391 |
d->rirb_count, d->rirb_cnt); |
392 |
if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
|
393 |
d->rirb_sts |= ICH6_RBSTS_IRQ; |
394 |
intel_hda_update_irq(d); |
395 |
} |
396 |
} |
397 |
} |
398 |
|
399 |
static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, |
400 |
uint8_t *buf, uint32_t len) |
401 |
{ |
402 |
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
403 |
IntelHDAState *d = container_of(bus, IntelHDAState, codecs); |
404 |
IntelHDAStream *st = NULL;
|
405 |
target_phys_addr_t addr; |
406 |
uint32_t s, copy, left; |
407 |
bool irq = false; |
408 |
|
409 |
for (s = 0; s < ARRAY_SIZE(d->st); s++) { |
410 |
if (stnr == ((d->st[s].ctl >> 20) & 0x0f)) { |
411 |
st = d->st + s; |
412 |
break;
|
413 |
} |
414 |
} |
415 |
if (st == NULL) { |
416 |
return false; |
417 |
} |
418 |
if (st->bpl == NULL) { |
419 |
return false; |
420 |
} |
421 |
if (st->ctl & (1 << 26)) { |
422 |
/*
|
423 |
* Wait with the next DMA xfer until the guest
|
424 |
* has acked the buffer completion interrupt
|
425 |
*/
|
426 |
return false; |
427 |
} |
428 |
|
429 |
left = len; |
430 |
while (left > 0) { |
431 |
copy = left; |
432 |
if (copy > st->bsize - st->lpib)
|
433 |
copy = st->bsize - st->lpib; |
434 |
if (copy > st->bpl[st->be].len - st->bp)
|
435 |
copy = st->bpl[st->be].len - st->bp; |
436 |
|
437 |
dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", |
438 |
st->be, st->bp, st->bpl[st->be].len, copy); |
439 |
|
440 |
cpu_physical_memory_rw(st->bpl[st->be].addr + st->bp, |
441 |
buf, copy, !output); |
442 |
st->lpib += copy; |
443 |
st->bp += copy; |
444 |
buf += copy; |
445 |
left -= copy; |
446 |
|
447 |
if (st->bpl[st->be].len == st->bp) {
|
448 |
/* bpl entry filled */
|
449 |
if (st->bpl[st->be].flags & 0x01) { |
450 |
irq = true;
|
451 |
} |
452 |
st->bp = 0;
|
453 |
st->be++; |
454 |
if (st->be == st->bentries) {
|
455 |
/* bpl wrap around */
|
456 |
st->be = 0;
|
457 |
st->lpib = 0;
|
458 |
} |
459 |
} |
460 |
} |
461 |
if (d->dp_lbase & 0x01) { |
462 |
addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
|
463 |
stl_phys_le(addr + 8*s, st->lpib);
|
464 |
} |
465 |
dprint(d, 3, "dma: --\n"); |
466 |
|
467 |
if (irq) {
|
468 |
st->ctl |= (1 << 26); /* buffer completion interrupt */ |
469 |
intel_hda_update_irq(d); |
470 |
} |
471 |
return true; |
472 |
} |
473 |
|
474 |
static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) |
475 |
{ |
476 |
target_phys_addr_t addr; |
477 |
uint8_t buf[16];
|
478 |
uint32_t i; |
479 |
|
480 |
addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); |
481 |
st->bentries = st->lvi +1;
|
482 |
qemu_free(st->bpl); |
483 |
st->bpl = qemu_malloc(sizeof(bpl) * st->bentries);
|
484 |
for (i = 0; i < st->bentries; i++, addr += 16) { |
485 |
cpu_physical_memory_read(addr, buf, 16);
|
486 |
st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); |
487 |
st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
|
488 |
st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
|
489 |
dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", |
490 |
i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); |
491 |
} |
492 |
|
493 |
st->bsize = st->cbl; |
494 |
st->lpib = 0;
|
495 |
st->be = 0;
|
496 |
st->bp = 0;
|
497 |
} |
498 |
|
499 |
static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running) |
500 |
{ |
501 |
DeviceState *qdev; |
502 |
HDACodecDevice *cdev; |
503 |
|
504 |
QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) { |
505 |
cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
506 |
if (cdev->info->stream) {
|
507 |
cdev->info->stream(cdev, stream, running); |
508 |
} |
509 |
} |
510 |
} |
511 |
|
512 |
/* --------------------------------------------------------------------- */
|
513 |
|
514 |
static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
515 |
{ |
516 |
if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { |
517 |
intel_hda_reset(&d->pci.qdev); |
518 |
} |
519 |
} |
520 |
|
521 |
static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
522 |
{ |
523 |
intel_hda_update_irq(d); |
524 |
} |
525 |
|
526 |
static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
527 |
{ |
528 |
intel_hda_update_irq(d); |
529 |
} |
530 |
|
531 |
static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
532 |
{ |
533 |
intel_hda_update_irq(d); |
534 |
} |
535 |
|
536 |
static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) |
537 |
{ |
538 |
int64_t ns; |
539 |
|
540 |
ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns; |
541 |
d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ |
542 |
} |
543 |
|
544 |
static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
545 |
{ |
546 |
intel_hda_corb_run(d); |
547 |
} |
548 |
|
549 |
static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
550 |
{ |
551 |
intel_hda_corb_run(d); |
552 |
} |
553 |
|
554 |
static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
555 |
{ |
556 |
if (d->rirb_wp & ICH6_RIRBWP_RST) {
|
557 |
d->rirb_wp = 0;
|
558 |
} |
559 |
} |
560 |
|
561 |
static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
562 |
{ |
563 |
intel_hda_update_irq(d); |
564 |
|
565 |
if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
|
566 |
/* cleared ICH6_RBSTS_IRQ */
|
567 |
d->rirb_count = 0;
|
568 |
intel_hda_corb_run(d); |
569 |
} |
570 |
} |
571 |
|
572 |
static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
573 |
{ |
574 |
if (d->ics & ICH6_IRS_BUSY) {
|
575 |
intel_hda_corb_run(d); |
576 |
} |
577 |
} |
578 |
|
579 |
static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
580 |
{ |
581 |
IntelHDAStream *st = d->st + reg->stream; |
582 |
|
583 |
if (st->ctl & 0x01) { |
584 |
/* reset */
|
585 |
dprint(d, 1, "st #%d: reset\n", reg->stream); |
586 |
st->ctl = 0;
|
587 |
} |
588 |
if ((st->ctl & 0x02) != (old & 0x02)) { |
589 |
uint32_t stnr = (st->ctl >> 20) & 0x0f; |
590 |
/* run bit flipped */
|
591 |
if (st->ctl & 0x02) { |
592 |
/* start */
|
593 |
dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", |
594 |
reg->stream, stnr, st->cbl); |
595 |
intel_hda_parse_bdl(d, st); |
596 |
intel_hda_notify_codecs(d, stnr, true);
|
597 |
} else {
|
598 |
/* stop */
|
599 |
dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); |
600 |
intel_hda_notify_codecs(d, stnr, false);
|
601 |
} |
602 |
} |
603 |
intel_hda_update_irq(d); |
604 |
} |
605 |
|
606 |
/* --------------------------------------------------------------------- */
|
607 |
|
608 |
#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) |
609 |
|
610 |
static const struct IntelHDAReg regtab[] = { |
611 |
/* global */
|
612 |
[ ICH6_REG_GCAP ] = { |
613 |
.name = "GCAP",
|
614 |
.size = 2,
|
615 |
.reset = 0x4401,
|
616 |
}, |
617 |
[ ICH6_REG_VMIN ] = { |
618 |
.name = "VMIN",
|
619 |
.size = 1,
|
620 |
}, |
621 |
[ ICH6_REG_VMAJ ] = { |
622 |
.name = "VMAJ",
|
623 |
.size = 1,
|
624 |
.reset = 1,
|
625 |
}, |
626 |
[ ICH6_REG_OUTPAY ] = { |
627 |
.name = "OUTPAY",
|
628 |
.size = 2,
|
629 |
.reset = 0x3c,
|
630 |
}, |
631 |
[ ICH6_REG_INPAY ] = { |
632 |
.name = "INPAY",
|
633 |
.size = 2,
|
634 |
.reset = 0x1d,
|
635 |
}, |
636 |
[ ICH6_REG_GCTL ] = { |
637 |
.name = "GCTL",
|
638 |
.size = 4,
|
639 |
.wmask = 0x0103,
|
640 |
.offset = offsetof(IntelHDAState, g_ctl), |
641 |
.whandler = intel_hda_set_g_ctl, |
642 |
}, |
643 |
[ ICH6_REG_WAKEEN ] = { |
644 |
.name = "WAKEEN",
|
645 |
.size = 2,
|
646 |
.wmask = 0x7fff,
|
647 |
.offset = offsetof(IntelHDAState, wake_en), |
648 |
.whandler = intel_hda_set_wake_en, |
649 |
}, |
650 |
[ ICH6_REG_STATESTS ] = { |
651 |
.name = "STATESTS",
|
652 |
.size = 2,
|
653 |
.wmask = 0x7fff,
|
654 |
.wclear = 0x7fff,
|
655 |
.offset = offsetof(IntelHDAState, state_sts), |
656 |
.whandler = intel_hda_set_state_sts, |
657 |
}, |
658 |
|
659 |
/* interrupts */
|
660 |
[ ICH6_REG_INTCTL ] = { |
661 |
.name = "INTCTL",
|
662 |
.size = 4,
|
663 |
.wmask = 0xc00000ff,
|
664 |
.offset = offsetof(IntelHDAState, int_ctl), |
665 |
.whandler = intel_hda_set_int_ctl, |
666 |
}, |
667 |
[ ICH6_REG_INTSTS ] = { |
668 |
.name = "INTSTS",
|
669 |
.size = 4,
|
670 |
.wmask = 0xc00000ff,
|
671 |
.wclear = 0xc00000ff,
|
672 |
.offset = offsetof(IntelHDAState, int_sts), |
673 |
}, |
674 |
|
675 |
/* misc */
|
676 |
[ ICH6_REG_WALLCLK ] = { |
677 |
.name = "WALLCLK",
|
678 |
.size = 4,
|
679 |
.offset = offsetof(IntelHDAState, wall_clk), |
680 |
.rhandler = intel_hda_get_wall_clk, |
681 |
}, |
682 |
[ ICH6_REG_WALLCLK + 0x2000 ] = {
|
683 |
.name = "WALLCLK(alias)",
|
684 |
.size = 4,
|
685 |
.offset = offsetof(IntelHDAState, wall_clk), |
686 |
.rhandler = intel_hda_get_wall_clk, |
687 |
}, |
688 |
|
689 |
/* dma engine */
|
690 |
[ ICH6_REG_CORBLBASE ] = { |
691 |
.name = "CORBLBASE",
|
692 |
.size = 4,
|
693 |
.wmask = 0xffffff80,
|
694 |
.offset = offsetof(IntelHDAState, corb_lbase), |
695 |
}, |
696 |
[ ICH6_REG_CORBUBASE ] = { |
697 |
.name = "CORBUBASE",
|
698 |
.size = 4,
|
699 |
.wmask = 0xffffffff,
|
700 |
.offset = offsetof(IntelHDAState, corb_ubase), |
701 |
}, |
702 |
[ ICH6_REG_CORBWP ] = { |
703 |
.name = "CORBWP",
|
704 |
.size = 2,
|
705 |
.wmask = 0xff,
|
706 |
.offset = offsetof(IntelHDAState, corb_wp), |
707 |
.whandler = intel_hda_set_corb_wp, |
708 |
}, |
709 |
[ ICH6_REG_CORBRP ] = { |
710 |
.name = "CORBRP",
|
711 |
.size = 2,
|
712 |
.wmask = 0x80ff,
|
713 |
.offset = offsetof(IntelHDAState, corb_rp), |
714 |
}, |
715 |
[ ICH6_REG_CORBCTL ] = { |
716 |
.name = "CORBCTL",
|
717 |
.size = 1,
|
718 |
.wmask = 0x03,
|
719 |
.offset = offsetof(IntelHDAState, corb_ctl), |
720 |
.whandler = intel_hda_set_corb_ctl, |
721 |
}, |
722 |
[ ICH6_REG_CORBSTS ] = { |
723 |
.name = "CORBSTS",
|
724 |
.size = 1,
|
725 |
.wmask = 0x01,
|
726 |
.wclear = 0x01,
|
727 |
.offset = offsetof(IntelHDAState, corb_sts), |
728 |
}, |
729 |
[ ICH6_REG_CORBSIZE ] = { |
730 |
.name = "CORBSIZE",
|
731 |
.size = 1,
|
732 |
.reset = 0x42,
|
733 |
.offset = offsetof(IntelHDAState, corb_size), |
734 |
}, |
735 |
[ ICH6_REG_RIRBLBASE ] = { |
736 |
.name = "RIRBLBASE",
|
737 |
.size = 4,
|
738 |
.wmask = 0xffffff80,
|
739 |
.offset = offsetof(IntelHDAState, rirb_lbase), |
740 |
}, |
741 |
[ ICH6_REG_RIRBUBASE ] = { |
742 |
.name = "RIRBUBASE",
|
743 |
.size = 4,
|
744 |
.wmask = 0xffffffff,
|
745 |
.offset = offsetof(IntelHDAState, rirb_ubase), |
746 |
}, |
747 |
[ ICH6_REG_RIRBWP ] = { |
748 |
.name = "RIRBWP",
|
749 |
.size = 2,
|
750 |
.wmask = 0x8000,
|
751 |
.offset = offsetof(IntelHDAState, rirb_wp), |
752 |
.whandler = intel_hda_set_rirb_wp, |
753 |
}, |
754 |
[ ICH6_REG_RINTCNT ] = { |
755 |
.name = "RINTCNT",
|
756 |
.size = 2,
|
757 |
.wmask = 0xff,
|
758 |
.offset = offsetof(IntelHDAState, rirb_cnt), |
759 |
}, |
760 |
[ ICH6_REG_RIRBCTL ] = { |
761 |
.name = "RIRBCTL",
|
762 |
.size = 1,
|
763 |
.wmask = 0x07,
|
764 |
.offset = offsetof(IntelHDAState, rirb_ctl), |
765 |
}, |
766 |
[ ICH6_REG_RIRBSTS ] = { |
767 |
.name = "RIRBSTS",
|
768 |
.size = 1,
|
769 |
.wmask = 0x05,
|
770 |
.wclear = 0x05,
|
771 |
.offset = offsetof(IntelHDAState, rirb_sts), |
772 |
.whandler = intel_hda_set_rirb_sts, |
773 |
}, |
774 |
[ ICH6_REG_RIRBSIZE ] = { |
775 |
.name = "RIRBSIZE",
|
776 |
.size = 1,
|
777 |
.reset = 0x42,
|
778 |
.offset = offsetof(IntelHDAState, rirb_size), |
779 |
}, |
780 |
|
781 |
[ ICH6_REG_DPLBASE ] = { |
782 |
.name = "DPLBASE",
|
783 |
.size = 4,
|
784 |
.wmask = 0xffffff81,
|
785 |
.offset = offsetof(IntelHDAState, dp_lbase), |
786 |
}, |
787 |
[ ICH6_REG_DPUBASE ] = { |
788 |
.name = "DPUBASE",
|
789 |
.size = 4,
|
790 |
.wmask = 0xffffffff,
|
791 |
.offset = offsetof(IntelHDAState, dp_ubase), |
792 |
}, |
793 |
|
794 |
[ ICH6_REG_IC ] = { |
795 |
.name = "ICW",
|
796 |
.size = 4,
|
797 |
.wmask = 0xffffffff,
|
798 |
.offset = offsetof(IntelHDAState, icw), |
799 |
}, |
800 |
[ ICH6_REG_IR ] = { |
801 |
.name = "IRR",
|
802 |
.size = 4,
|
803 |
.offset = offsetof(IntelHDAState, irr), |
804 |
}, |
805 |
[ ICH6_REG_IRS ] = { |
806 |
.name = "ICS",
|
807 |
.size = 2,
|
808 |
.wmask = 0x0003,
|
809 |
.wclear = 0x0002,
|
810 |
.offset = offsetof(IntelHDAState, ics), |
811 |
.whandler = intel_hda_set_ics, |
812 |
}, |
813 |
|
814 |
#define HDA_STREAM(_t, _i) \
|
815 |
[ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ |
816 |
.stream = _i, \ |
817 |
.name = _t stringify(_i) " CTL", \
|
818 |
.size = 4, \
|
819 |
.wmask = 0x1cff001f, \
|
820 |
.offset = offsetof(IntelHDAState, st[_i].ctl), \ |
821 |
.whandler = intel_hda_set_st_ctl, \ |
822 |
}, \ |
823 |
[ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
|
824 |
.stream = _i, \ |
825 |
.name = _t stringify(_i) " CTL(stnr)", \
|
826 |
.size = 1, \
|
827 |
.shift = 16, \
|
828 |
.wmask = 0x00ff0000, \
|
829 |
.offset = offsetof(IntelHDAState, st[_i].ctl), \ |
830 |
.whandler = intel_hda_set_st_ctl, \ |
831 |
}, \ |
832 |
[ ST_REG(_i, ICH6_REG_SD_STS)] = { \ |
833 |
.stream = _i, \ |
834 |
.name = _t stringify(_i) " CTL(sts)", \
|
835 |
.size = 1, \
|
836 |
.shift = 24, \
|
837 |
.wmask = 0x1c000000, \
|
838 |
.wclear = 0x1c000000, \
|
839 |
.offset = offsetof(IntelHDAState, st[_i].ctl), \ |
840 |
.whandler = intel_hda_set_st_ctl, \ |
841 |
}, \ |
842 |
[ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ |
843 |
.stream = _i, \ |
844 |
.name = _t stringify(_i) " LPIB", \
|
845 |
.size = 4, \
|
846 |
.offset = offsetof(IntelHDAState, st[_i].lpib), \ |
847 |
}, \ |
848 |
[ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
|
849 |
.stream = _i, \ |
850 |
.name = _t stringify(_i) " LPIB(alias)", \
|
851 |
.size = 4, \
|
852 |
.offset = offsetof(IntelHDAState, st[_i].lpib), \ |
853 |
}, \ |
854 |
[ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ |
855 |
.stream = _i, \ |
856 |
.name = _t stringify(_i) " CBL", \
|
857 |
.size = 4, \
|
858 |
.wmask = 0xffffffff, \
|
859 |
.offset = offsetof(IntelHDAState, st[_i].cbl), \ |
860 |
}, \ |
861 |
[ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ |
862 |
.stream = _i, \ |
863 |
.name = _t stringify(_i) " LVI", \
|
864 |
.size = 2, \
|
865 |
.wmask = 0x00ff, \
|
866 |
.offset = offsetof(IntelHDAState, st[_i].lvi), \ |
867 |
}, \ |
868 |
[ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ |
869 |
.stream = _i, \ |
870 |
.name = _t stringify(_i) " FIFOS", \
|
871 |
.size = 2, \
|
872 |
.reset = HDA_BUFFER_SIZE, \ |
873 |
}, \ |
874 |
[ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ |
875 |
.stream = _i, \ |
876 |
.name = _t stringify(_i) " FMT", \
|
877 |
.size = 2, \
|
878 |
.wmask = 0x7f7f, \
|
879 |
.offset = offsetof(IntelHDAState, st[_i].fmt), \ |
880 |
}, \ |
881 |
[ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ |
882 |
.stream = _i, \ |
883 |
.name = _t stringify(_i) " BDLPL", \
|
884 |
.size = 4, \
|
885 |
.wmask = 0xffffff80, \
|
886 |
.offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ |
887 |
}, \ |
888 |
[ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ |
889 |
.stream = _i, \ |
890 |
.name = _t stringify(_i) " BDLPU", \
|
891 |
.size = 4, \
|
892 |
.wmask = 0xffffffff, \
|
893 |
.offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ |
894 |
}, \ |
895 |
|
896 |
HDA_STREAM("IN", 0) |
897 |
HDA_STREAM("IN", 1) |
898 |
HDA_STREAM("IN", 2) |
899 |
HDA_STREAM("IN", 3) |
900 |
|
901 |
HDA_STREAM("OUT", 4) |
902 |
HDA_STREAM("OUT", 5) |
903 |
HDA_STREAM("OUT", 6) |
904 |
HDA_STREAM("OUT", 7) |
905 |
|
906 |
}; |
907 |
|
908 |
static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr) |
909 |
{ |
910 |
const IntelHDAReg *reg;
|
911 |
|
912 |
if (addr >= sizeof(regtab)/sizeof(regtab[0])) { |
913 |
goto noreg;
|
914 |
} |
915 |
reg = regtab+addr; |
916 |
if (reg->name == NULL) { |
917 |
goto noreg;
|
918 |
} |
919 |
return reg;
|
920 |
|
921 |
noreg:
|
922 |
dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); |
923 |
return NULL; |
924 |
} |
925 |
|
926 |
static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) |
927 |
{ |
928 |
uint8_t *addr = (void*)d;
|
929 |
|
930 |
addr += reg->offset; |
931 |
return (uint32_t*)addr;
|
932 |
} |
933 |
|
934 |
static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, |
935 |
uint32_t wmask) |
936 |
{ |
937 |
uint32_t *addr; |
938 |
uint32_t old; |
939 |
|
940 |
if (!reg) {
|
941 |
return;
|
942 |
} |
943 |
|
944 |
if (d->debug) {
|
945 |
time_t now = time(NULL);
|
946 |
if (d->last_write && d->last_reg == reg && d->last_val == val) {
|
947 |
d->repeat_count++; |
948 |
if (d->last_sec != now) {
|
949 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
950 |
d->last_sec = now; |
951 |
d->repeat_count = 0;
|
952 |
} |
953 |
} else {
|
954 |
if (d->repeat_count) {
|
955 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
956 |
} |
957 |
dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); |
958 |
d->last_write = 1;
|
959 |
d->last_reg = reg; |
960 |
d->last_val = val; |
961 |
d->last_sec = now; |
962 |
d->repeat_count = 0;
|
963 |
} |
964 |
} |
965 |
assert(reg->offset != 0);
|
966 |
|
967 |
addr = intel_hda_reg_addr(d, reg); |
968 |
old = *addr; |
969 |
|
970 |
if (reg->shift) {
|
971 |
val <<= reg->shift; |
972 |
wmask <<= reg->shift; |
973 |
} |
974 |
wmask &= reg->wmask; |
975 |
*addr &= ~wmask; |
976 |
*addr |= wmask & val; |
977 |
*addr &= ~(val & reg->wclear); |
978 |
|
979 |
if (reg->whandler) {
|
980 |
reg->whandler(d, reg, old); |
981 |
} |
982 |
} |
983 |
|
984 |
static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, |
985 |
uint32_t rmask) |
986 |
{ |
987 |
uint32_t *addr, ret; |
988 |
|
989 |
if (!reg) {
|
990 |
return 0; |
991 |
} |
992 |
|
993 |
if (reg->rhandler) {
|
994 |
reg->rhandler(d, reg); |
995 |
} |
996 |
|
997 |
if (reg->offset == 0) { |
998 |
/* constant read-only register */
|
999 |
ret = reg->reset; |
1000 |
} else {
|
1001 |
addr = intel_hda_reg_addr(d, reg); |
1002 |
ret = *addr; |
1003 |
if (reg->shift) {
|
1004 |
ret >>= reg->shift; |
1005 |
} |
1006 |
ret &= rmask; |
1007 |
} |
1008 |
if (d->debug) {
|
1009 |
time_t now = time(NULL);
|
1010 |
if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
|
1011 |
d->repeat_count++; |
1012 |
if (d->last_sec != now) {
|
1013 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
1014 |
d->last_sec = now; |
1015 |
d->repeat_count = 0;
|
1016 |
} |
1017 |
} else {
|
1018 |
if (d->repeat_count) {
|
1019 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
1020 |
} |
1021 |
dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); |
1022 |
d->last_write = 0;
|
1023 |
d->last_reg = reg; |
1024 |
d->last_val = ret; |
1025 |
d->last_sec = now; |
1026 |
d->repeat_count = 0;
|
1027 |
} |
1028 |
} |
1029 |
return ret;
|
1030 |
} |
1031 |
|
1032 |
static void intel_hda_regs_reset(IntelHDAState *d) |
1033 |
{ |
1034 |
uint32_t *addr; |
1035 |
int i;
|
1036 |
|
1037 |
for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) { |
1038 |
if (regtab[i].name == NULL) { |
1039 |
continue;
|
1040 |
} |
1041 |
if (regtab[i].offset == 0) { |
1042 |
continue;
|
1043 |
} |
1044 |
addr = intel_hda_reg_addr(d, regtab + i); |
1045 |
*addr = regtab[i].reset; |
1046 |
} |
1047 |
} |
1048 |
|
1049 |
/* --------------------------------------------------------------------- */
|
1050 |
|
1051 |
static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
1052 |
{ |
1053 |
IntelHDAState *d = opaque; |
1054 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
1055 |
|
1056 |
intel_hda_reg_write(d, reg, val, 0xff);
|
1057 |
} |
1058 |
|
1059 |
static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
1060 |
{ |
1061 |
IntelHDAState *d = opaque; |
1062 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
1063 |
|
1064 |
intel_hda_reg_write(d, reg, val, 0xffff);
|
1065 |
} |
1066 |
|
1067 |
static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
1068 |
{ |
1069 |
IntelHDAState *d = opaque; |
1070 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
1071 |
|
1072 |
intel_hda_reg_write(d, reg, val, 0xffffffff);
|
1073 |
} |
1074 |
|
1075 |
static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr) |
1076 |
{ |
1077 |
IntelHDAState *d = opaque; |
1078 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
1079 |
|
1080 |
return intel_hda_reg_read(d, reg, 0xff); |
1081 |
} |
1082 |
|
1083 |
static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr) |
1084 |
{ |
1085 |
IntelHDAState *d = opaque; |
1086 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
1087 |
|
1088 |
return intel_hda_reg_read(d, reg, 0xffff); |
1089 |
} |
1090 |
|
1091 |
static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr) |
1092 |
{ |
1093 |
IntelHDAState *d = opaque; |
1094 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
1095 |
|
1096 |
return intel_hda_reg_read(d, reg, 0xffffffff); |
1097 |
} |
1098 |
|
1099 |
static CPUReadMemoryFunc * const intel_hda_mmio_read[3] = { |
1100 |
intel_hda_mmio_readb, |
1101 |
intel_hda_mmio_readw, |
1102 |
intel_hda_mmio_readl, |
1103 |
}; |
1104 |
|
1105 |
static CPUWriteMemoryFunc * const intel_hda_mmio_write[3] = { |
1106 |
intel_hda_mmio_writeb, |
1107 |
intel_hda_mmio_writew, |
1108 |
intel_hda_mmio_writel, |
1109 |
}; |
1110 |
|
1111 |
static void intel_hda_map(PCIDevice *pci, int region_num, |
1112 |
pcibus_t addr, pcibus_t size, int type)
|
1113 |
{ |
1114 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
1115 |
|
1116 |
cpu_register_physical_memory(addr, 0x4000, d->mmio_addr);
|
1117 |
} |
1118 |
|
1119 |
/* --------------------------------------------------------------------- */
|
1120 |
|
1121 |
static void intel_hda_reset(DeviceState *dev) |
1122 |
{ |
1123 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev); |
1124 |
DeviceState *qdev; |
1125 |
HDACodecDevice *cdev; |
1126 |
|
1127 |
intel_hda_regs_reset(d); |
1128 |
d->wall_base_ns = qemu_get_clock(vm_clock); |
1129 |
|
1130 |
/* reset codecs */
|
1131 |
QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) { |
1132 |
cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
1133 |
if (qdev->info->reset) {
|
1134 |
qdev->info->reset(qdev); |
1135 |
} |
1136 |
d->state_sts |= (1 << cdev->cad);
|
1137 |
} |
1138 |
intel_hda_update_irq(d); |
1139 |
} |
1140 |
|
1141 |
static int intel_hda_init(PCIDevice *pci) |
1142 |
{ |
1143 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
1144 |
uint8_t *conf = d->pci.config; |
1145 |
|
1146 |
d->name = d->pci.qdev.info->name; |
1147 |
|
1148 |
pci_config_set_vendor_id(conf, PCI_VENDOR_ID_INTEL); |
1149 |
pci_config_set_device_id(conf, 0x2668);
|
1150 |
pci_config_set_revision(conf, 1);
|
1151 |
pci_config_set_class(conf, PCI_CLASS_MULTIMEDIA_HD_AUDIO); |
1152 |
pci_config_set_interrupt_pin(conf, 1);
|
1153 |
|
1154 |
/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
|
1155 |
conf[0x40] = 0x01; |
1156 |
|
1157 |
d->mmio_addr = cpu_register_io_memory(intel_hda_mmio_read, |
1158 |
intel_hda_mmio_write, d); |
1159 |
pci_register_bar(&d->pci, 0, 0x4000, PCI_BASE_ADDRESS_SPACE_MEMORY, |
1160 |
intel_hda_map); |
1161 |
if (d->msi) {
|
1162 |
msi_init(&d->pci, 0x50, 1, true, false); |
1163 |
} |
1164 |
|
1165 |
hda_codec_bus_init(&d->pci.qdev, &d->codecs, |
1166 |
intel_hda_response, intel_hda_xfer); |
1167 |
|
1168 |
return 0; |
1169 |
} |
1170 |
|
1171 |
static int intel_hda_exit(PCIDevice *pci) |
1172 |
{ |
1173 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
1174 |
|
1175 |
if (d->msi) {
|
1176 |
msi_uninit(&d->pci); |
1177 |
} |
1178 |
cpu_unregister_io_memory(d->mmio_addr); |
1179 |
return 0; |
1180 |
} |
1181 |
|
1182 |
static void intel_hda_write_config(PCIDevice *pci, uint32_t addr, |
1183 |
uint32_t val, int len)
|
1184 |
{ |
1185 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
1186 |
|
1187 |
pci_default_write_config(pci, addr, val, len); |
1188 |
if (d->msi) {
|
1189 |
msi_write_config(pci, addr, val, len); |
1190 |
} |
1191 |
} |
1192 |
|
1193 |
static int intel_hda_post_load(void *opaque, int version) |
1194 |
{ |
1195 |
IntelHDAState* d = opaque; |
1196 |
int i;
|
1197 |
|
1198 |
dprint(d, 1, "%s\n", __FUNCTION__); |
1199 |
for (i = 0; i < ARRAY_SIZE(d->st); i++) { |
1200 |
if (d->st[i].ctl & 0x02) { |
1201 |
intel_hda_parse_bdl(d, &d->st[i]); |
1202 |
} |
1203 |
} |
1204 |
intel_hda_update_irq(d); |
1205 |
return 0; |
1206 |
} |
1207 |
|
1208 |
static const VMStateDescription vmstate_intel_hda_stream = { |
1209 |
.name = "intel-hda-stream",
|
1210 |
.version_id = 1,
|
1211 |
.fields = (VMStateField []) { |
1212 |
VMSTATE_UINT32(ctl, IntelHDAStream), |
1213 |
VMSTATE_UINT32(lpib, IntelHDAStream), |
1214 |
VMSTATE_UINT32(cbl, IntelHDAStream), |
1215 |
VMSTATE_UINT32(lvi, IntelHDAStream), |
1216 |
VMSTATE_UINT32(fmt, IntelHDAStream), |
1217 |
VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), |
1218 |
VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), |
1219 |
VMSTATE_END_OF_LIST() |
1220 |
} |
1221 |
}; |
1222 |
|
1223 |
static const VMStateDescription vmstate_intel_hda = { |
1224 |
.name = "intel-hda",
|
1225 |
.version_id = 1,
|
1226 |
.post_load = intel_hda_post_load, |
1227 |
.fields = (VMStateField []) { |
1228 |
VMSTATE_PCI_DEVICE(pci, IntelHDAState), |
1229 |
|
1230 |
/* registers */
|
1231 |
VMSTATE_UINT32(g_ctl, IntelHDAState), |
1232 |
VMSTATE_UINT32(wake_en, IntelHDAState), |
1233 |
VMSTATE_UINT32(state_sts, IntelHDAState), |
1234 |
VMSTATE_UINT32(int_ctl, IntelHDAState), |
1235 |
VMSTATE_UINT32(int_sts, IntelHDAState), |
1236 |
VMSTATE_UINT32(wall_clk, IntelHDAState), |
1237 |
VMSTATE_UINT32(corb_lbase, IntelHDAState), |
1238 |
VMSTATE_UINT32(corb_ubase, IntelHDAState), |
1239 |
VMSTATE_UINT32(corb_rp, IntelHDAState), |
1240 |
VMSTATE_UINT32(corb_wp, IntelHDAState), |
1241 |
VMSTATE_UINT32(corb_ctl, IntelHDAState), |
1242 |
VMSTATE_UINT32(corb_sts, IntelHDAState), |
1243 |
VMSTATE_UINT32(corb_size, IntelHDAState), |
1244 |
VMSTATE_UINT32(rirb_lbase, IntelHDAState), |
1245 |
VMSTATE_UINT32(rirb_ubase, IntelHDAState), |
1246 |
VMSTATE_UINT32(rirb_wp, IntelHDAState), |
1247 |
VMSTATE_UINT32(rirb_cnt, IntelHDAState), |
1248 |
VMSTATE_UINT32(rirb_ctl, IntelHDAState), |
1249 |
VMSTATE_UINT32(rirb_sts, IntelHDAState), |
1250 |
VMSTATE_UINT32(rirb_size, IntelHDAState), |
1251 |
VMSTATE_UINT32(dp_lbase, IntelHDAState), |
1252 |
VMSTATE_UINT32(dp_ubase, IntelHDAState), |
1253 |
VMSTATE_UINT32(icw, IntelHDAState), |
1254 |
VMSTATE_UINT32(irr, IntelHDAState), |
1255 |
VMSTATE_UINT32(ics, IntelHDAState), |
1256 |
VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, |
1257 |
vmstate_intel_hda_stream, |
1258 |
IntelHDAStream), |
1259 |
|
1260 |
/* additional state info */
|
1261 |
VMSTATE_UINT32(rirb_count, IntelHDAState), |
1262 |
VMSTATE_INT64(wall_base_ns, IntelHDAState), |
1263 |
|
1264 |
VMSTATE_END_OF_LIST() |
1265 |
} |
1266 |
}; |
1267 |
|
1268 |
static PCIDeviceInfo intel_hda_info = {
|
1269 |
.qdev.name = "intel-hda",
|
1270 |
.qdev.desc = "Intel HD Audio Controller",
|
1271 |
.qdev.size = sizeof(IntelHDAState),
|
1272 |
.qdev.vmsd = &vmstate_intel_hda, |
1273 |
.qdev.reset = intel_hda_reset, |
1274 |
.init = intel_hda_init, |
1275 |
.exit = intel_hda_exit, |
1276 |
.config_write = intel_hda_write_config, |
1277 |
.qdev.props = (Property[]) { |
1278 |
DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), |
1279 |
DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1), |
1280 |
DEFINE_PROP_END_OF_LIST(), |
1281 |
} |
1282 |
}; |
1283 |
|
1284 |
static void intel_hda_register(void) |
1285 |
{ |
1286 |
pci_qdev_register(&intel_hda_info); |
1287 |
} |
1288 |
device_init(intel_hda_register); |
1289 |
|
1290 |
/*
|
1291 |
* create intel hda controller with codec attached to it,
|
1292 |
* so '-soundhw hda' works.
|
1293 |
*/
|
1294 |
int intel_hda_and_codec_init(PCIBus *bus)
|
1295 |
{ |
1296 |
PCIDevice *controller; |
1297 |
BusState *hdabus; |
1298 |
DeviceState *codec; |
1299 |
|
1300 |
controller = pci_create_simple(bus, -1, "intel-hda"); |
1301 |
hdabus = QLIST_FIRST(&controller->qdev.child_bus); |
1302 |
codec = qdev_create(hdabus, "hda-duplex");
|
1303 |
qdev_init_nofail(codec); |
1304 |
return 0; |
1305 |
} |
1306 |
|