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/*
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 * QEMU System Emulator
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 *
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 * Copyright (c) 2003-2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * splitted out ioport related stuffs from vl.c.
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 */
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#include "ioport.h"
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#include "trace.h"
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/***********************************************************/
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/* IO Port */
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//#define DEBUG_UNUSED_IOPORT
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//#define DEBUG_IOPORT
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#ifdef DEBUG_UNUSED_IOPORT
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#  define LOG_UNUSED_IOPORT(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
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#else
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#  define LOG_UNUSED_IOPORT(fmt, ...) do{ } while (0)
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#endif
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#ifdef DEBUG_IOPORT
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#  define LOG_IOPORT(...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__)
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#else
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#  define LOG_IOPORT(...) do { } while (0)
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#endif
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/* XXX: use a two level table to limit memory usage */
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static void *ioport_opaque[MAX_IOPORTS];
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static IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
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static IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
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static IOPortReadFunc default_ioport_readb, default_ioport_readw, default_ioport_readl;
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static IOPortWriteFunc default_ioport_writeb, default_ioport_writew, default_ioport_writel;
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static uint32_t ioport_read(int index, uint32_t address)
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{
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    static IOPortReadFunc * const default_func[3] = {
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        default_ioport_readb,
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        default_ioport_readw,
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        default_ioport_readl
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    };
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    IOPortReadFunc *func = ioport_read_table[index][address];
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    if (!func)
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        func = default_func[index];
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    return func(ioport_opaque[address], address);
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}
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static void ioport_write(int index, uint32_t address, uint32_t data)
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{
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    static IOPortWriteFunc * const default_func[3] = {
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        default_ioport_writeb,
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        default_ioport_writew,
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        default_ioport_writel
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    };
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    IOPortWriteFunc *func = ioport_write_table[index][address];
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    if (!func)
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        func = default_func[index];
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    func(ioport_opaque[address], address, data);
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}
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static uint32_t default_ioport_readb(void *opaque, uint32_t address)
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{
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    LOG_UNUSED_IOPORT("unused inb: port=0x%04"PRIx32"\n", address);
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    return 0xff;
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}
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static void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data)
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{
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    LOG_UNUSED_IOPORT("unused outb: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
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                      address, data);
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}
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/* default is to make two byte accesses */
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static uint32_t default_ioport_readw(void *opaque, uint32_t address)
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{
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    uint32_t data;
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    data = ioport_read(0, address);
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    address = (address + 1) & IOPORTS_MASK;
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    data |= ioport_read(0, address) << 8;
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    return data;
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}
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static void default_ioport_writew(void *opaque, uint32_t address, uint32_t data)
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{
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    ioport_write(0, address, data & 0xff);
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    address = (address + 1) & IOPORTS_MASK;
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    ioport_write(0, address, (data >> 8) & 0xff);
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}
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static uint32_t default_ioport_readl(void *opaque, uint32_t address)
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{
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    LOG_UNUSED_IOPORT("unused inl: port=0x%04"PRIx32"\n", address);
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    return 0xffffffff;
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}
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static void default_ioport_writel(void *opaque, uint32_t address, uint32_t data)
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{
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    LOG_UNUSED_IOPORT("unused outl: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
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                      address, data);
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}
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static int ioport_bsize(int size, int *bsize)
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{
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    if (size == 1) {
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        *bsize = 0;
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    } else if (size == 2) {
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        *bsize = 1;
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    } else if (size == 4) {
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        *bsize = 2;
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    } else {
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        return -1;
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    }
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    return 0;
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}
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/* size is the word size in byte */
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int register_ioport_read(pio_addr_t start, int length, int size,
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                         IOPortReadFunc *func, void *opaque)
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{
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    int i, bsize;
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    if (ioport_bsize(size, &bsize)) {
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        hw_error("register_ioport_read: invalid size");
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        return -1;
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    }
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    for(i = start; i < start + length; i += size) {
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        ioport_read_table[bsize][i] = func;
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        if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
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            hw_error("register_ioport_read: invalid opaque");
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        ioport_opaque[i] = opaque;
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    }
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    return 0;
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}
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/* size is the word size in byte */
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int register_ioport_write(pio_addr_t start, int length, int size,
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                          IOPortWriteFunc *func, void *opaque)
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{
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    int i, bsize;
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    if (ioport_bsize(size, &bsize)) {
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        hw_error("register_ioport_write: invalid size");
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        return -1;
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    }
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    for(i = start; i < start + length; i += size) {
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        ioport_write_table[bsize][i] = func;
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        if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
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            hw_error("register_ioport_write: invalid opaque");
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        ioport_opaque[i] = opaque;
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    }
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    return 0;
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}
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static uint32_t ioport_readb_thunk(void *opaque, uint32_t addr)
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{
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    IORange *ioport = opaque;
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    uint64_t data;
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    ioport->ops->read(ioport, addr - ioport->base, 1, &data);
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    return data;
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}
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static uint32_t ioport_readw_thunk(void *opaque, uint32_t addr)
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{
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    IORange *ioport = opaque;
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    uint64_t data;
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    ioport->ops->read(ioport, addr - ioport->base, 2, &data);
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    return data;
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}
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static uint32_t ioport_readl_thunk(void *opaque, uint32_t addr)
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{
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    IORange *ioport = opaque;
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    uint64_t data;
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    ioport->ops->read(ioport, addr - ioport->base, 4, &data);
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    return data;
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}
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static void ioport_writeb_thunk(void *opaque, uint32_t addr, uint32_t data)
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{
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    IORange *ioport = opaque;
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    ioport->ops->write(ioport, addr - ioport->base, 1, data);
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}
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static void ioport_writew_thunk(void *opaque, uint32_t addr, uint32_t data)
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{
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    IORange *ioport = opaque;
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    ioport->ops->write(ioport, addr - ioport->base, 2, data);
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}
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static void ioport_writel_thunk(void *opaque, uint32_t addr, uint32_t data)
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{
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    IORange *ioport = opaque;
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    ioport->ops->write(ioport, addr - ioport->base, 4, data);
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}
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void ioport_register(IORange *ioport)
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{
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    register_ioport_read(ioport->base, ioport->len, 1,
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                         ioport_readb_thunk, ioport);
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    register_ioport_read(ioport->base, ioport->len, 2,
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                         ioport_readw_thunk, ioport);
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    register_ioport_read(ioport->base, ioport->len, 4,
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                         ioport_readl_thunk, ioport);
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    register_ioport_write(ioport->base, ioport->len, 1,
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                          ioport_writeb_thunk, ioport);
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    register_ioport_write(ioport->base, ioport->len, 2,
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                          ioport_writew_thunk, ioport);
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    register_ioport_write(ioport->base, ioport->len, 4,
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                          ioport_writel_thunk, ioport);
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}
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void isa_unassign_ioport(pio_addr_t start, int length)
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{
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    int i;
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    for(i = start; i < start + length; i++) {
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        ioport_read_table[0][i] = default_ioport_readb;
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        ioport_read_table[1][i] = default_ioport_readw;
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        ioport_read_table[2][i] = default_ioport_readl;
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        ioport_write_table[0][i] = default_ioport_writeb;
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        ioport_write_table[1][i] = default_ioport_writew;
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        ioport_write_table[2][i] = default_ioport_writel;
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        ioport_opaque[i] = NULL;
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    }
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}
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/***********************************************************/
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void cpu_outb(pio_addr_t addr, uint8_t val)
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{
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    LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
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    trace_cpu_out(addr, val);
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    ioport_write(0, addr, val);
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}
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void cpu_outw(pio_addr_t addr, uint16_t val)
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{
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    LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
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    trace_cpu_out(addr, val);
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    ioport_write(1, addr, val);
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}
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void cpu_outl(pio_addr_t addr, uint32_t val)
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{
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    LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
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    trace_cpu_out(addr, val);
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    ioport_write(2, addr, val);
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}
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uint8_t cpu_inb(pio_addr_t addr)
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{
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    uint8_t val;
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    val = ioport_read(0, addr);
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    trace_cpu_in(addr, val);
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    LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
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    return val;
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}
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uint16_t cpu_inw(pio_addr_t addr)
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{
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    uint16_t val;
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    val = ioport_read(1, addr);
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    trace_cpu_in(addr, val);
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    LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
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    return val;
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}
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uint32_t cpu_inl(pio_addr_t addr)
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{
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    uint32_t val;
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    val = ioport_read(2, addr);
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    trace_cpu_in(addr, val);
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    LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
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    return val;
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}