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/*
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* QEMU i8255x (PRO100) emulation
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*
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* Copyright (C) 2006-2011 Stefan Weil
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*
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* Portions of the code are copies from grub / etherboot eepro100.c
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* and linux e100.c.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) version 3 or any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Tested features (i82559):
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* PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
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* Linux networking (i386) ok
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*
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* Untested:
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* Windows networking
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*
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* References:
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*
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* Intel 8255x 10/100 Mbps Ethernet Controller Family
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* Open Source Software Developer Manual
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*
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* TODO:
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* * PHY emulation should be separated from nic emulation.
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* Most nic emulations could share the same phy code.
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* * i82550 is untested. It is programmed like the i82559.
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* * i82562 is untested. It is programmed like the i82559.
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* * Power management (i82558 and later) is not implemented.
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* * Wake-on-LAN is not implemented.
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*/
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#include <stddef.h> /* offsetof */ |
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#include "hw.h" |
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#include "pci.h" |
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#include "net.h" |
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#include "eeprom93xx.h" |
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#include "sysemu.h" |
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/* QEMU sends frames smaller than 60 bytes to ethernet nics.
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* Such frames are rejected by real nics and their emulations.
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* To avoid this behaviour, other nic emulations pad received
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* frames. The following definition enables this padding for
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* eepro100, too. We keep the define around in case it might
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* become useful the future if the core networking is ever
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* changed to pad short packets itself. */
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#define CONFIG_PAD_RECEIVED_FRAMES
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#define KiB 1024 |
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/* Debug EEPRO100 card. */
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#if 0
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# define DEBUG_EEPRO100
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#endif
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#ifdef DEBUG_EEPRO100
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#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__) |
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#else
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#define logout(fmt, ...) ((void)0) |
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#endif
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/* Set flags to 0 to disable debug output. */
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#define INT 1 /* interrupt related actions */ |
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#define MDI 1 /* mdi related actions */ |
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#define OTHER 1 |
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#define RXTX 1 |
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#define EEPROM 1 /* eeprom related actions */ |
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#define TRACE(flag, command) ((flag) ? (command) : (void)0) |
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#define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n") |
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#define MAX_ETH_FRAME_SIZE 1514 |
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/* This driver supports several different devices which are declared here. */
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#define i82550 0x82550 |
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#define i82551 0x82551 |
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#define i82557A 0x82557a |
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#define i82557B 0x82557b |
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#define i82557C 0x82557c |
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#define i82558A 0x82558a |
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#define i82558B 0x82558b |
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#define i82559A 0x82559a |
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#define i82559B 0x82559b |
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#define i82559C 0x82559c |
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#define i82559ER 0x82559e |
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#define i82562 0x82562 |
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#define i82801 0x82801 |
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/* Use 64 word EEPROM. TODO: could be a runtime option. */
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#define EEPROM_SIZE 64 |
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#define PCI_MEM_SIZE (4 * KiB) |
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#define PCI_IO_SIZE 64 |
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#define PCI_FLASH_SIZE (128 * KiB) |
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#define BIT(n) (1 << (n)) |
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#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) |
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/* The SCB accepts the following controls for the Tx and Rx units: */
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#define CU_NOP 0x0000 /* No operation. */ |
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#define CU_START 0x0010 /* CU start. */ |
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#define CU_RESUME 0x0020 /* CU resume. */ |
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#define CU_STATSADDR 0x0040 /* Load dump counters address. */ |
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#define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ |
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#define CU_CMD_BASE 0x0060 /* Load CU base address. */ |
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#define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ |
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#define CU_SRESUME 0x00a0 /* CU static resume. */ |
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#define RU_NOP 0x0000 |
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#define RX_START 0x0001 |
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#define RX_RESUME 0x0002 |
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#define RU_ABORT 0x0004 |
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#define RX_ADDR_LOAD 0x0006 |
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#define RX_RESUMENR 0x0007 |
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#define INT_MASK 0x0100 |
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#define DRVR_INT 0x0200 /* Driver generated interrupt. */ |
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typedef struct { |
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PCIDeviceInfo pci; |
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uint32_t device; |
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uint8_t stats_size; |
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bool has_extended_tcb_support;
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bool power_management;
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} E100PCIDeviceInfo; |
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/* Offsets to the various registers.
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All accesses need not be longword aligned. */
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typedef enum { |
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SCBStatus = 0, /* Status Word. */ |
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SCBAck = 1,
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SCBCmd = 2, /* Rx/Command Unit command and status. */ |
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SCBIntmask = 3,
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SCBPointer = 4, /* General purpose pointer. */ |
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SCBPort = 8, /* Misc. commands and operands. */ |
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SCBflash = 12, /* Flash memory control. */ |
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SCBeeprom = 14, /* EEPROM control. */ |
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SCBCtrlMDI = 16, /* MDI interface control. */ |
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SCBEarlyRx = 20, /* Early receive byte count. */ |
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SCBFlow = 24, /* Flow Control. */ |
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SCBpmdr = 27, /* Power Management Driver. */ |
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SCBgctrl = 28, /* General Control. */ |
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SCBgstat = 29, /* General Status. */ |
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} E100RegisterOffset; |
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/* A speedo3 transmit buffer descriptor with two buffers... */
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typedef struct { |
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uint16_t status; |
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uint16_t command; |
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uint32_t link; /* void * */
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uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
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uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
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uint8_t tx_threshold; /* transmit threshold */
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uint8_t tbd_count; /* TBD number */
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#if 0
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/* This constitutes two "TBD" entries: hdr and data */
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uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
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int32_t tx_buf_size0; /* Length of Tx hdr. */
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uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
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int32_t tx_buf_size1; /* Length of Tx data. */
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#endif
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} eepro100_tx_t; |
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/* Receive frame descriptor. */
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typedef struct { |
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int16_t status; |
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uint16_t command; |
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uint32_t link; /* struct RxFD * */
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uint32_t rx_buf_addr; /* void * */
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uint16_t count; |
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uint16_t size; |
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/* Ethernet frame data follows. */
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} eepro100_rx_t; |
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typedef enum { |
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COMMAND_EL = BIT(15),
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COMMAND_S = BIT(14),
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COMMAND_I = BIT(13),
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COMMAND_NC = BIT(4),
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COMMAND_SF = BIT(3),
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COMMAND_CMD = BITS(2, 0), |
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} scb_command_bit; |
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typedef enum { |
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STATUS_C = BIT(15),
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STATUS_OK = BIT(13),
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} scb_status_bit; |
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typedef struct { |
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uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, |
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tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, |
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tx_multiple_collisions, tx_total_collisions; |
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uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, |
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rx_resource_errors, rx_overrun_errors, rx_cdt_errors, |
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rx_short_frame_errors; |
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uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; |
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uint16_t xmt_tco_frames, rcv_tco_frames; |
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/* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
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uint32_t reserved[4];
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} eepro100_stats_t; |
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typedef enum { |
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cu_idle = 0,
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cu_suspended = 1,
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cu_active = 2,
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cu_lpq_active = 2,
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cu_hqp_active = 3
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} cu_state_t; |
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typedef enum { |
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ru_idle = 0,
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ru_suspended = 1,
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ru_no_resources = 2,
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ru_ready = 4
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} ru_state_t; |
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typedef struct { |
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PCIDevice dev; |
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/* Hash register (multicast mask array, multiple individual addresses). */
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uint8_t mult[8];
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int mmio_index;
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NICState *nic; |
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NICConf conf; |
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uint8_t scb_stat; /* SCB stat/ack byte */
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uint8_t int_stat; /* PCI interrupt status */
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/* region must not be saved by nic_save. */
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uint32_t region1; /* PCI region 1 address */
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uint16_t mdimem[32];
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eeprom_t *eeprom; |
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uint32_t device; /* device variant */
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/* (cu_base + cu_offset) address the next command block in the command block list. */
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uint32_t cu_base; /* CU base address */
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uint32_t cu_offset; /* CU address offset */
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/* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
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uint32_t ru_base; /* RU base address */
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uint32_t ru_offset; /* RU address offset */
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uint32_t statsaddr; /* pointer to eepro100_stats_t */
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/* Temporary status information (no need to save these values),
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* used while processing CU commands. */
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eepro100_tx_t tx; /* transmit buffer descriptor */
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uint32_t cb_address; /* = cu_base + cu_offset */
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/* Statistical counters. Also used for wake-up packet (i82559). */
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eepro100_stats_t statistics; |
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/* Data in mem is always in the byte order of the controller (le).
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* It must be dword aligned to allow direct access to 32 bit values. */
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uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));;
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|
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/* Configuration bytes. */
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uint8_t configuration[22];
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/* vmstate for each particular nic */
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VMStateDescription *vmstate; |
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/* Quasi static device properties (no need to save them). */
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uint16_t stats_size; |
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bool has_extended_tcb_support;
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} EEPRO100State; |
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|
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/* Word indices in EEPROM. */
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typedef enum { |
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EEPROM_CNFG_MDIX = 0x03,
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EEPROM_ID = 0x05,
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EEPROM_PHY_ID = 0x06,
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EEPROM_VENDOR_ID = 0x0c,
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EEPROM_CONFIG_ASF = 0x0d,
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EEPROM_DEVICE_ID = 0x23,
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EEPROM_SMBUS_ADDR = 0x90,
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} EEPROMOffset; |
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|
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/* Bit values for EEPROM ID word. */
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typedef enum { |
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EEPROM_ID_MDM = BIT(0), /* Modem */ |
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EEPROM_ID_STB = BIT(1), /* Standby Enable */ |
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EEPROM_ID_WMR = BIT(2), /* ??? */ |
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EEPROM_ID_WOL = BIT(5), /* Wake on LAN */ |
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EEPROM_ID_DPD = BIT(6), /* Deep Power Down */ |
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EEPROM_ID_ALT = BIT(7), /* */ |
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/* BITS(10, 8) device revision */
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EEPROM_ID_BD = BIT(11), /* boot disable */ |
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EEPROM_ID_ID = BIT(13), /* id bit */ |
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/* BITS(15, 14) signature */
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EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */ |
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} eeprom_id_bit; |
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|
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/* Default values for MDI (PHY) registers */
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static const uint16_t eepro100_mdi_default[] = { |
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/* MDI Registers 0 - 6, 7 */
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0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, |
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/* MDI Registers 8 - 15 */
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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/* MDI Registers 16 - 31 */
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0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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}; |
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|
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/* Readonly mask for MDI (PHY) registers */
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static const uint16_t eepro100_mdi_mask[] = { |
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0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, |
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, |
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0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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}; |
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|
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/* Read a 16 bit little endian value from physical memory. */
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static uint16_t e100_ldw_le_phys(target_phys_addr_t addr)
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{
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/* Load 16 bit (little endian) word from emulated hardware. */
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uint16_t val; |
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cpu_physical_memory_read(addr, &val, sizeof(val));
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return le16_to_cpu(val);
|
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} |
| 325 |
|
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/* Read a 32 bit little endian value from physical memory. */
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static uint32_t e100_ldl_le_phys(target_phys_addr_t addr)
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{
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/* Load 32 bit (little endian) word from emulated hardware. */
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uint32_t val; |
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cpu_physical_memory_read(addr, &val, sizeof(val));
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return le32_to_cpu(val);
|
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} |
| 334 |
|
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/* Write a 16 bit little endian value to physical memory. */
|
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static void e100_stw_le_phys(target_phys_addr_t addr, uint16_t val) |
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{
|
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val = cpu_to_le16(val); |
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cpu_physical_memory_write(addr, &val, sizeof(val));
|
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} |
| 341 |
|
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/* Write a 32 bit little endian value to physical memory. */
|
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static void e100_stl_le_phys(target_phys_addr_t addr, uint32_t val) |
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{
|
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val = cpu_to_le32(val); |
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cpu_physical_memory_write(addr, &val, sizeof(val));
|
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} |
| 348 |
|
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#define POLYNOMIAL 0x04c11db6 |
| 350 |
|
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/* From FreeBSD */
|
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/* XXX: optimize */
|
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static unsigned compute_mcast_idx(const uint8_t * ep) |
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{
|
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uint32_t crc; |
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int carry, i, j;
|
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uint8_t b; |
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|
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crc = 0xffffffff;
|
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for (i = 0; i < 6; i++) { |
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b = *ep++; |
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for (j = 0; j < 8; j++) { |
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carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
| 364 |
crc <<= 1;
|
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b >>= 1;
|
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if (carry) {
|
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crc = ((crc ^ POLYNOMIAL) | carry); |
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} |
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} |
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} |
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return (crc & BITS(7, 2)) >> 2; |
| 372 |
} |
| 373 |
|
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/* Read a 16 bit control/status (CSR) register. */
|
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static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
|
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{
|
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assert(!((uintptr_t)&s->mem[addr] & 1));
|
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return le16_to_cpup((uint16_t *)&s->mem[addr]);
|
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} |
| 380 |
|
| 381 |
/* Read a 32 bit control/status (CSR) register. */
|
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static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
|
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{
|
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assert(!((uintptr_t)&s->mem[addr] & 3));
|
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return le32_to_cpup((uint32_t *)&s->mem[addr]);
|
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} |
| 387 |
|
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/* Write a 16 bit control/status (CSR) register. */
|
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static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr, |
| 390 |
uint16_t val) |
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{
|
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assert(!((uintptr_t)&s->mem[addr] & 1));
|
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cpu_to_le16w((uint16_t *)&s->mem[addr], val); |
| 394 |
} |
| 395 |
|
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/* Read a 32 bit control/status (CSR) register. */
|
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static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr, |
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uint32_t val) |
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{
|
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assert(!((uintptr_t)&s->mem[addr] & 3));
|
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cpu_to_le32w((uint32_t *)&s->mem[addr], val); |
| 402 |
} |
| 403 |
|
| 404 |
#if defined(DEBUG_EEPRO100)
|
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static const char *nic_dump(const uint8_t * buf, unsigned size) |
| 406 |
{
|
| 407 |
static char dump[3 * 16 + 1]; |
| 408 |
char *p = &dump[0]; |
| 409 |
if (size > 16) { |
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size = 16;
|
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} |
| 412 |
while (size-- > 0) { |
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p += sprintf(p, " %02x", *buf++);
|
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} |
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return dump;
|
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} |
| 417 |
#endif /* DEBUG_EEPRO100 */ |
| 418 |
|
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enum scb_stat_ack {
|
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stat_ack_not_ours = 0x00,
|
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stat_ack_sw_gen = 0x04,
|
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stat_ack_rnr = 0x10,
|
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stat_ack_cu_idle = 0x20,
|
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stat_ack_frame_rx = 0x40,
|
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stat_ack_cu_cmd_done = 0x80,
|
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stat_ack_not_present = 0xFF,
|
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stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), |
| 428 |
stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), |
| 429 |
}; |
| 430 |
|
| 431 |
static void disable_interrupt(EEPRO100State * s) |
| 432 |
{
|
| 433 |
if (s->int_stat) {
|
| 434 |
TRACE(INT, logout("interrupt disabled\n"));
|
| 435 |
qemu_irq_lower(s->dev.irq[0]);
|
| 436 |
s->int_stat = 0;
|
| 437 |
} |
| 438 |
} |
| 439 |
|
| 440 |
static void enable_interrupt(EEPRO100State * s) |
| 441 |
{
|
| 442 |
if (!s->int_stat) {
|
| 443 |
TRACE(INT, logout("interrupt enabled\n"));
|
| 444 |
qemu_irq_raise(s->dev.irq[0]);
|
| 445 |
s->int_stat = 1;
|
| 446 |
} |
| 447 |
} |
| 448 |
|
| 449 |
static void eepro100_acknowledge(EEPRO100State * s) |
| 450 |
{
|
| 451 |
s->scb_stat &= ~s->mem[SCBAck]; |
| 452 |
s->mem[SCBAck] = s->scb_stat; |
| 453 |
if (s->scb_stat == 0) { |
| 454 |
disable_interrupt(s); |
| 455 |
} |
| 456 |
} |
| 457 |
|
| 458 |
static void eepro100_interrupt(EEPRO100State * s, uint8_t status) |
| 459 |
{
|
| 460 |
uint8_t mask = ~s->mem[SCBIntmask]; |
| 461 |
s->mem[SCBAck] |= status; |
| 462 |
status = s->scb_stat = s->mem[SCBAck]; |
| 463 |
status &= (mask | 0x0f);
|
| 464 |
#if 0
|
| 465 |
status &= (~s->mem[SCBIntmask] | 0x0xf);
|
| 466 |
#endif
|
| 467 |
if (status && (mask & 0x01)) { |
| 468 |
/* SCB mask and SCB Bit M do not disable interrupt. */
|
| 469 |
enable_interrupt(s); |
| 470 |
} else if (s->int_stat) { |
| 471 |
disable_interrupt(s); |
| 472 |
} |
| 473 |
} |
| 474 |
|
| 475 |
static void eepro100_cx_interrupt(EEPRO100State * s) |
| 476 |
{
|
| 477 |
/* CU completed action command. */
|
| 478 |
/* Transmit not ok (82557 only, not in emulation). */
|
| 479 |
eepro100_interrupt(s, 0x80);
|
| 480 |
} |
| 481 |
|
| 482 |
static void eepro100_cna_interrupt(EEPRO100State * s) |
| 483 |
{
|
| 484 |
/* CU left the active state. */
|
| 485 |
eepro100_interrupt(s, 0x20);
|
| 486 |
} |
| 487 |
|
| 488 |
static void eepro100_fr_interrupt(EEPRO100State * s) |
| 489 |
{
|
| 490 |
/* RU received a complete frame. */
|
| 491 |
eepro100_interrupt(s, 0x40);
|
| 492 |
} |
| 493 |
|
| 494 |
static void eepro100_rnr_interrupt(EEPRO100State * s) |
| 495 |
{
|
| 496 |
/* RU is not ready. */
|
| 497 |
eepro100_interrupt(s, 0x10);
|
| 498 |
} |
| 499 |
|
| 500 |
static void eepro100_mdi_interrupt(EEPRO100State * s) |
| 501 |
{
|
| 502 |
/* MDI completed read or write cycle. */
|
| 503 |
eepro100_interrupt(s, 0x08);
|
| 504 |
} |
| 505 |
|
| 506 |
static void eepro100_swi_interrupt(EEPRO100State * s) |
| 507 |
{
|
| 508 |
/* Software has requested an interrupt. */
|
| 509 |
eepro100_interrupt(s, 0x04);
|
| 510 |
} |
| 511 |
|
| 512 |
#if 0
|
| 513 |
static void eepro100_fcp_interrupt(EEPRO100State * s)
|
| 514 |
{
|
| 515 |
/* Flow control pause interrupt (82558 and later). */
|
| 516 |
eepro100_interrupt(s, 0x01);
|
| 517 |
}
|
| 518 |
#endif
|
| 519 |
|
| 520 |
static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device) |
| 521 |
{
|
| 522 |
uint32_t device = s->device; |
| 523 |
uint8_t *pci_conf = s->dev.config; |
| 524 |
|
| 525 |
TRACE(OTHER, logout("%p\n", s));
|
| 526 |
|
| 527 |
/* PCI Status */
|
| 528 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
| 529 |
PCI_STATUS_FAST_BACK); |
| 530 |
/* PCI Latency Timer */
|
| 531 |
pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */ |
| 532 |
/* Capability Pointer is set by PCI framework. */
|
| 533 |
/* Interrupt Line */
|
| 534 |
/* Interrupt Pin */
|
| 535 |
pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */ |
| 536 |
/* Minimum Grant */
|
| 537 |
pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
|
| 538 |
/* Maximum Latency */
|
| 539 |
pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
|
| 540 |
|
| 541 |
s->stats_size = e100_device->stats_size; |
| 542 |
s->has_extended_tcb_support = e100_device->has_extended_tcb_support; |
| 543 |
|
| 544 |
switch (device) {
|
| 545 |
case i82550:
|
| 546 |
case i82551:
|
| 547 |
case i82557A:
|
| 548 |
case i82557B:
|
| 549 |
case i82557C:
|
| 550 |
case i82558A:
|
| 551 |
case i82558B:
|
| 552 |
case i82559A:
|
| 553 |
case i82559B:
|
| 554 |
case i82559ER:
|
| 555 |
case i82562:
|
| 556 |
case i82801:
|
| 557 |
case i82559C:
|
| 558 |
break;
|
| 559 |
default:
|
| 560 |
logout("Device %X is undefined!\n", device);
|
| 561 |
} |
| 562 |
|
| 563 |
/* Standard TxCB. */
|
| 564 |
s->configuration[6] |= BIT(4); |
| 565 |
|
| 566 |
/* Standard statistical counters. */
|
| 567 |
s->configuration[6] |= BIT(5); |
| 568 |
|
| 569 |
if (s->stats_size == 80) { |
| 570 |
/* TODO: check TCO Statistical Counters bit. Documentation not clear. */
|
| 571 |
if (s->configuration[6] & BIT(2)) { |
| 572 |
/* TCO statistical counters. */
|
| 573 |
assert(s->configuration[6] & BIT(5)); |
| 574 |
} else {
|
| 575 |
if (s->configuration[6] & BIT(5)) { |
| 576 |
/* No extended statistical counters, i82557 compatible. */
|
| 577 |
s->stats_size = 64;
|
| 578 |
} else {
|
| 579 |
/* i82558 compatible. */
|
| 580 |
s->stats_size = 76;
|
| 581 |
} |
| 582 |
} |
| 583 |
} else {
|
| 584 |
if (s->configuration[6] & BIT(5)) { |
| 585 |
/* No extended statistical counters. */
|
| 586 |
s->stats_size = 64;
|
| 587 |
} |
| 588 |
} |
| 589 |
assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics)); |
| 590 |
|
| 591 |
if (e100_device->power_management) {
|
| 592 |
/* Power Management Capabilities */
|
| 593 |
int cfg_offset = 0xdc; |
| 594 |
int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
|
| 595 |
cfg_offset, PCI_PM_SIZEOF); |
| 596 |
assert(r >= 0);
|
| 597 |
pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
|
| 598 |
#if 0 /* TODO: replace dummy code for power management emulation. */
|
| 599 |
/* TODO: Power Management Control / Status. */
|
| 600 |
pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
|
| 601 |
/* TODO: Ethernet Power Consumption Registers (i82559 and later). */
|
| 602 |
pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
|
| 603 |
#endif
|
| 604 |
} |
| 605 |
|
| 606 |
#if EEPROM_SIZE > 0 |
| 607 |
if (device == i82557C || device == i82558B || device == i82559C) {
|
| 608 |
/*
|
| 609 |
TODO: get vendor id from EEPROM for i82557C or later.
|
| 610 |
TODO: get device id from EEPROM for i82557C or later.
|
| 611 |
TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
|
| 612 |
TODO: header type is determined by EEPROM for i82559.
|
| 613 |
TODO: get subsystem id from EEPROM for i82557C or later.
|
| 614 |
TODO: get subsystem vendor id from EEPROM for i82557C or later.
|
| 615 |
TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
|
| 616 |
TODO: capability pointer depends on EEPROM for i82558.
|
| 617 |
*/
|
| 618 |
logout("Get device id and revision from EEPROM!!!\n");
|
| 619 |
} |
| 620 |
#endif /* EEPROM_SIZE > 0 */ |
| 621 |
} |
| 622 |
|
| 623 |
static void nic_selective_reset(EEPRO100State * s) |
| 624 |
{
|
| 625 |
size_t i; |
| 626 |
uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); |
| 627 |
#if 0
|
| 628 |
eeprom93xx_reset(s->eeprom);
|
| 629 |
#endif
|
| 630 |
memcpy(eeprom_contents, s->conf.macaddr.a, 6);
|
| 631 |
eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID; |
| 632 |
if (s->device == i82557B || s->device == i82557C)
|
| 633 |
eeprom_contents[5] = 0x0100; |
| 634 |
eeprom_contents[EEPROM_PHY_ID] = 1;
|
| 635 |
uint16_t sum = 0;
|
| 636 |
for (i = 0; i < EEPROM_SIZE - 1; i++) { |
| 637 |
sum += eeprom_contents[i]; |
| 638 |
} |
| 639 |
eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; |
| 640 |
TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1])); |
| 641 |
|
| 642 |
memset(s->mem, 0, sizeof(s->mem)); |
| 643 |
e100_write_reg4(s, SCBCtrlMDI, BIT(21));
|
| 644 |
|
| 645 |
assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); |
| 646 |
memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); |
| 647 |
} |
| 648 |
|
| 649 |
static void nic_reset(void *opaque) |
| 650 |
{
|
| 651 |
EEPRO100State *s = opaque; |
| 652 |
TRACE(OTHER, logout("%p\n", s));
|
| 653 |
/* TODO: Clearing of hash register for selective reset, too? */
|
| 654 |
memset(&s->mult[0], 0, sizeof(s->mult)); |
| 655 |
nic_selective_reset(s); |
| 656 |
} |
| 657 |
|
| 658 |
#if defined(DEBUG_EEPRO100)
|
| 659 |
static const char * const e100_reg[PCI_IO_SIZE / 4] = { |
| 660 |
"Command/Status",
|
| 661 |
"General Pointer",
|
| 662 |
"Port",
|
| 663 |
"EEPROM/Flash Control",
|
| 664 |
"MDI Control",
|
| 665 |
"Receive DMA Byte Count",
|
| 666 |
"Flow Control",
|
| 667 |
"General Status/Control"
|
| 668 |
}; |
| 669 |
|
| 670 |
static char *regname(uint32_t addr) |
| 671 |
{
|
| 672 |
static char buf[32]; |
| 673 |
if (addr < PCI_IO_SIZE) {
|
| 674 |
const char *r = e100_reg[addr / 4]; |
| 675 |
if (r != 0) { |
| 676 |
snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4); |
| 677 |
} else {
|
| 678 |
snprintf(buf, sizeof(buf), "0x%02x", addr); |
| 679 |
} |
| 680 |
} else {
|
| 681 |
snprintf(buf, sizeof(buf), "??? 0x%08x", addr); |
| 682 |
} |
| 683 |
return buf;
|
| 684 |
} |
| 685 |
#endif /* DEBUG_EEPRO100 */ |
| 686 |
|
| 687 |
/*****************************************************************************
|
| 688 |
*
|
| 689 |
* Command emulation.
|
| 690 |
*
|
| 691 |
****************************************************************************/
|
| 692 |
|
| 693 |
#if 0
|
| 694 |
static uint16_t eepro100_read_command(EEPRO100State * s)
|
| 695 |
{
|
| 696 |
uint16_t val = 0xffff;
|
| 697 |
TRACE(OTHER, logout("val=0x%04x\n", val));
|
| 698 |
return val;
|
| 699 |
}
|
| 700 |
#endif
|
| 701 |
|
| 702 |
/* Commands that can be put in a command list entry. */
|
| 703 |
enum commands {
|
| 704 |
CmdNOp = 0,
|
| 705 |
CmdIASetup = 1,
|
| 706 |
CmdConfigure = 2,
|
| 707 |
CmdMulticastList = 3,
|
| 708 |
CmdTx = 4,
|
| 709 |
CmdTDR = 5, /* load microcode */ |
| 710 |
CmdDump = 6,
|
| 711 |
CmdDiagnose = 7,
|
| 712 |
|
| 713 |
/* And some extra flags: */
|
| 714 |
CmdSuspend = 0x4000, /* Suspend after completion. */ |
| 715 |
CmdIntr = 0x2000, /* Interrupt after completion. */ |
| 716 |
CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ |
| 717 |
}; |
| 718 |
|
| 719 |
static cu_state_t get_cu_state(EEPRO100State * s)
|
| 720 |
{
|
| 721 |
return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6); |
| 722 |
} |
| 723 |
|
| 724 |
static void set_cu_state(EEPRO100State * s, cu_state_t state) |
| 725 |
{
|
| 726 |
s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6); |
| 727 |
} |
| 728 |
|
| 729 |
static ru_state_t get_ru_state(EEPRO100State * s)
|
| 730 |
{
|
| 731 |
return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2); |
| 732 |
} |
| 733 |
|
| 734 |
static void set_ru_state(EEPRO100State * s, ru_state_t state) |
| 735 |
{
|
| 736 |
s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2); |
| 737 |
} |
| 738 |
|
| 739 |
static void dump_statistics(EEPRO100State * s) |
| 740 |
{
|
| 741 |
/* Dump statistical data. Most data is never changed by the emulation
|
| 742 |
* and always 0, so we first just copy the whole block and then those
|
| 743 |
* values which really matter.
|
| 744 |
* Number of data should check configuration!!!
|
| 745 |
*/
|
| 746 |
cpu_physical_memory_write(s->statsaddr, &s->statistics, s->stats_size); |
| 747 |
e100_stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
|
| 748 |
e100_stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
|
| 749 |
e100_stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
|
| 750 |
e100_stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
|
| 751 |
#if 0
|
| 752 |
e100_stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
|
| 753 |
e100_stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
|
| 754 |
missing("CU dump statistical counters");
|
| 755 |
#endif
|
| 756 |
} |
| 757 |
|
| 758 |
static void read_cb(EEPRO100State *s) |
| 759 |
{
|
| 760 |
cpu_physical_memory_read(s->cb_address, &s->tx, sizeof(s->tx));
|
| 761 |
s->tx.status = le16_to_cpu(s->tx.status); |
| 762 |
s->tx.command = le16_to_cpu(s->tx.command); |
| 763 |
s->tx.link = le32_to_cpu(s->tx.link); |
| 764 |
s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr); |
| 765 |
s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes); |
| 766 |
} |
| 767 |
|
| 768 |
static void tx_command(EEPRO100State *s) |
| 769 |
{
|
| 770 |
uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr); |
| 771 |
uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
|
| 772 |
/* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
|
| 773 |
uint8_t buf[2600];
|
| 774 |
uint16_t size = 0;
|
| 775 |
uint32_t tbd_address = s->cb_address + 0x10;
|
| 776 |
TRACE(RXTX, logout |
| 777 |
("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
|
| 778 |
tbd_array, tcb_bytes, s->tx.tbd_count)); |
| 779 |
|
| 780 |
if (tcb_bytes > 2600) { |
| 781 |
logout("TCB byte count too large, using 2600\n");
|
| 782 |
tcb_bytes = 2600;
|
| 783 |
} |
| 784 |
if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { |
| 785 |
logout |
| 786 |
("illegal values of TBD array address and TCB byte count!\n");
|
| 787 |
} |
| 788 |
assert(tcb_bytes <= sizeof(buf));
|
| 789 |
while (size < tcb_bytes) {
|
| 790 |
uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address); |
| 791 |
uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
|
| 792 |
#if 0
|
| 793 |
uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
|
| 794 |
#endif
|
| 795 |
tbd_address += 8;
|
| 796 |
TRACE(RXTX, logout |
| 797 |
("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
|
| 798 |
tx_buffer_address, tx_buffer_size)); |
| 799 |
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
| 800 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
| 801 |
tx_buffer_size); |
| 802 |
size += tx_buffer_size; |
| 803 |
} |
| 804 |
if (tbd_array == 0xffffffff) { |
| 805 |
/* Simplified mode. Was already handled by code above. */
|
| 806 |
} else {
|
| 807 |
/* Flexible mode. */
|
| 808 |
uint8_t tbd_count = 0;
|
| 809 |
if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) { |
| 810 |
/* Extended Flexible TCB. */
|
| 811 |
for (; tbd_count < 2; tbd_count++) { |
| 812 |
uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address); |
| 813 |
uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
|
| 814 |
uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
|
| 815 |
tbd_address += 8;
|
| 816 |
TRACE(RXTX, logout |
| 817 |
("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
|
| 818 |
tx_buffer_address, tx_buffer_size)); |
| 819 |
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
| 820 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
| 821 |
tx_buffer_size); |
| 822 |
size += tx_buffer_size; |
| 823 |
if (tx_buffer_el & 1) { |
| 824 |
break;
|
| 825 |
} |
| 826 |
} |
| 827 |
} |
| 828 |
tbd_address = tbd_array; |
| 829 |
for (; tbd_count < s->tx.tbd_count; tbd_count++) {
|
| 830 |
uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address); |
| 831 |
uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
|
| 832 |
uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
|
| 833 |
tbd_address += 8;
|
| 834 |
TRACE(RXTX, logout |
| 835 |
("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
|
| 836 |
tx_buffer_address, tx_buffer_size)); |
| 837 |
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
| 838 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
| 839 |
tx_buffer_size); |
| 840 |
size += tx_buffer_size; |
| 841 |
if (tx_buffer_el & 1) { |
| 842 |
break;
|
| 843 |
} |
| 844 |
} |
| 845 |
} |
| 846 |
TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
|
| 847 |
qemu_send_packet(&s->nic->nc, buf, size); |
| 848 |
s->statistics.tx_good_frames++; |
| 849 |
/* Transmit with bad status would raise an CX/TNO interrupt.
|
| 850 |
* (82557 only). Emulation never has bad status. */
|
| 851 |
#if 0
|
| 852 |
eepro100_cx_interrupt(s);
|
| 853 |
#endif
|
| 854 |
} |
| 855 |
|
| 856 |
static void set_multicast_list(EEPRO100State *s) |
| 857 |
{
|
| 858 |
uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0); |
| 859 |
uint16_t i; |
| 860 |
memset(&s->mult[0], 0, sizeof(s->mult)); |
| 861 |
TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
|
| 862 |
for (i = 0; i < multicast_count; i += 6) { |
| 863 |
uint8_t multicast_addr[6];
|
| 864 |
cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6); |
| 865 |
TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6))); |
| 866 |
unsigned mcast_idx = compute_mcast_idx(multicast_addr);
|
| 867 |
assert(mcast_idx < 64);
|
| 868 |
s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7)); |
| 869 |
} |
| 870 |
} |
| 871 |
|
| 872 |
static void action_command(EEPRO100State *s) |
| 873 |
{
|
| 874 |
for (;;) {
|
| 875 |
bool bit_el;
|
| 876 |
bool bit_s;
|
| 877 |
bool bit_i;
|
| 878 |
bool bit_nc;
|
| 879 |
uint16_t ok_status = STATUS_OK; |
| 880 |
s->cb_address = s->cu_base + s->cu_offset; |
| 881 |
read_cb(s); |
| 882 |
bit_el = ((s->tx.command & COMMAND_EL) != 0);
|
| 883 |
bit_s = ((s->tx.command & COMMAND_S) != 0);
|
| 884 |
bit_i = ((s->tx.command & COMMAND_I) != 0);
|
| 885 |
bit_nc = ((s->tx.command & COMMAND_NC) != 0);
|
| 886 |
#if 0
|
| 887 |
bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
|
| 888 |
#endif
|
| 889 |
s->cu_offset = s->tx.link; |
| 890 |
TRACE(OTHER, |
| 891 |
logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
|
| 892 |
s->tx.status, s->tx.command, s->tx.link)); |
| 893 |
switch (s->tx.command & COMMAND_CMD) {
|
| 894 |
case CmdNOp:
|
| 895 |
/* Do nothing. */
|
| 896 |
break;
|
| 897 |
case CmdIASetup:
|
| 898 |
cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6); |
| 899 |
TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6))); |
| 900 |
break;
|
| 901 |
case CmdConfigure:
|
| 902 |
cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0], |
| 903 |
sizeof(s->configuration));
|
| 904 |
TRACE(OTHER, logout("configuration: %s\n",
|
| 905 |
nic_dump(&s->configuration[0], 16))); |
| 906 |
TRACE(OTHER, logout("configuration: %s\n",
|
| 907 |
nic_dump(&s->configuration[16],
|
| 908 |
ARRAY_SIZE(s->configuration) - 16)));
|
| 909 |
if (s->configuration[20] & BIT(6)) { |
| 910 |
TRACE(OTHER, logout("Multiple IA bit\n"));
|
| 911 |
} |
| 912 |
break;
|
| 913 |
case CmdMulticastList:
|
| 914 |
set_multicast_list(s); |
| 915 |
break;
|
| 916 |
case CmdTx:
|
| 917 |
if (bit_nc) {
|
| 918 |
missing("CmdTx: NC = 0");
|
| 919 |
ok_status = 0;
|
| 920 |
break;
|
| 921 |
} |
| 922 |
tx_command(s); |
| 923 |
break;
|
| 924 |
case CmdTDR:
|
| 925 |
TRACE(OTHER, logout("load microcode\n"));
|
| 926 |
/* Starting with offset 8, the command contains
|
| 927 |
* 64 dwords microcode which we just ignore here. */
|
| 928 |
break;
|
| 929 |
case CmdDiagnose:
|
| 930 |
TRACE(OTHER, logout("diagnose\n"));
|
| 931 |
/* Make sure error flag is not set. */
|
| 932 |
s->tx.status = 0;
|
| 933 |
break;
|
| 934 |
default:
|
| 935 |
missing("undefined command");
|
| 936 |
ok_status = 0;
|
| 937 |
break;
|
| 938 |
} |
| 939 |
/* Write new status. */
|
| 940 |
e100_stw_le_phys(s->cb_address, s->tx.status | ok_status | STATUS_C); |
| 941 |
if (bit_i) {
|
| 942 |
/* CU completed action. */
|
| 943 |
eepro100_cx_interrupt(s); |
| 944 |
} |
| 945 |
if (bit_el) {
|
| 946 |
/* CU becomes idle. Terminate command loop. */
|
| 947 |
set_cu_state(s, cu_idle); |
| 948 |
eepro100_cna_interrupt(s); |
| 949 |
break;
|
| 950 |
} else if (bit_s) { |
| 951 |
/* CU becomes suspended. Terminate command loop. */
|
| 952 |
set_cu_state(s, cu_suspended); |
| 953 |
eepro100_cna_interrupt(s); |
| 954 |
break;
|
| 955 |
} else {
|
| 956 |
/* More entries in list. */
|
| 957 |
TRACE(OTHER, logout("CU list with at least one more entry\n"));
|
| 958 |
} |
| 959 |
} |
| 960 |
TRACE(OTHER, logout("CU list empty\n"));
|
| 961 |
/* List is empty. Now CU is idle or suspended. */
|
| 962 |
} |
| 963 |
|
| 964 |
static void eepro100_cu_command(EEPRO100State * s, uint8_t val) |
| 965 |
{
|
| 966 |
cu_state_t cu_state; |
| 967 |
switch (val) {
|
| 968 |
case CU_NOP:
|
| 969 |
/* No operation. */
|
| 970 |
break;
|
| 971 |
case CU_START:
|
| 972 |
cu_state = get_cu_state(s); |
| 973 |
if (cu_state != cu_idle && cu_state != cu_suspended) {
|
| 974 |
/* Intel documentation says that CU must be idle or suspended
|
| 975 |
* for the CU start command. */
|
| 976 |
logout("unexpected CU state is %u\n", cu_state);
|
| 977 |
} |
| 978 |
set_cu_state(s, cu_active); |
| 979 |
s->cu_offset = e100_read_reg4(s, SCBPointer); |
| 980 |
action_command(s); |
| 981 |
break;
|
| 982 |
case CU_RESUME:
|
| 983 |
if (get_cu_state(s) != cu_suspended) {
|
| 984 |
logout("bad CU resume from CU state %u\n", get_cu_state(s));
|
| 985 |
/* Workaround for bad Linux eepro100 driver which resumes
|
| 986 |
* from idle state. */
|
| 987 |
#if 0
|
| 988 |
missing("cu resume");
|
| 989 |
#endif
|
| 990 |
set_cu_state(s, cu_suspended); |
| 991 |
} |
| 992 |
if (get_cu_state(s) == cu_suspended) {
|
| 993 |
TRACE(OTHER, logout("CU resuming\n"));
|
| 994 |
set_cu_state(s, cu_active); |
| 995 |
action_command(s); |
| 996 |
} |
| 997 |
break;
|
| 998 |
case CU_STATSADDR:
|
| 999 |
/* Load dump counters address. */
|
| 1000 |
s->statsaddr = e100_read_reg4(s, SCBPointer); |
| 1001 |
TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
|
| 1002 |
break;
|
| 1003 |
case CU_SHOWSTATS:
|
| 1004 |
/* Dump statistical counters. */
|
| 1005 |
TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
|
| 1006 |
dump_statistics(s); |
| 1007 |
e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
|
| 1008 |
break;
|
| 1009 |
case CU_CMD_BASE:
|
| 1010 |
/* Load CU base. */
|
| 1011 |
TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
|
| 1012 |
s->cu_base = e100_read_reg4(s, SCBPointer); |
| 1013 |
break;
|
| 1014 |
case CU_DUMPSTATS:
|
| 1015 |
/* Dump and reset statistical counters. */
|
| 1016 |
TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
|
| 1017 |
dump_statistics(s); |
| 1018 |
e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
|
| 1019 |
memset(&s->statistics, 0, sizeof(s->statistics)); |
| 1020 |
break;
|
| 1021 |
case CU_SRESUME:
|
| 1022 |
/* CU static resume. */
|
| 1023 |
missing("CU static resume");
|
| 1024 |
break;
|
| 1025 |
default:
|
| 1026 |
missing("Undefined CU command");
|
| 1027 |
} |
| 1028 |
} |
| 1029 |
|
| 1030 |
static void eepro100_ru_command(EEPRO100State * s, uint8_t val) |
| 1031 |
{
|
| 1032 |
switch (val) {
|
| 1033 |
case RU_NOP:
|
| 1034 |
/* No operation. */
|
| 1035 |
break;
|
| 1036 |
case RX_START:
|
| 1037 |
/* RU start. */
|
| 1038 |
if (get_ru_state(s) != ru_idle) {
|
| 1039 |
logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
|
| 1040 |
#if 0
|
| 1041 |
assert(!"wrong RU state");
|
| 1042 |
#endif
|
| 1043 |
} |
| 1044 |
set_ru_state(s, ru_ready); |
| 1045 |
s->ru_offset = e100_read_reg4(s, SCBPointer); |
| 1046 |
TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
|
| 1047 |
break;
|
| 1048 |
case RX_RESUME:
|
| 1049 |
/* Restart RU. */
|
| 1050 |
if (get_ru_state(s) != ru_suspended) {
|
| 1051 |
logout("RU state is %u, should be %u\n", get_ru_state(s),
|
| 1052 |
ru_suspended); |
| 1053 |
#if 0
|
| 1054 |
assert(!"wrong RU state");
|
| 1055 |
#endif
|
| 1056 |
} |
| 1057 |
set_ru_state(s, ru_ready); |
| 1058 |
break;
|
| 1059 |
case RU_ABORT:
|
| 1060 |
/* RU abort. */
|
| 1061 |
if (get_ru_state(s) == ru_ready) {
|
| 1062 |
eepro100_rnr_interrupt(s); |
| 1063 |
} |
| 1064 |
set_ru_state(s, ru_idle); |
| 1065 |
break;
|
| 1066 |
case RX_ADDR_LOAD:
|
| 1067 |
/* Load RU base. */
|
| 1068 |
TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
|
| 1069 |
s->ru_base = e100_read_reg4(s, SCBPointer); |
| 1070 |
break;
|
| 1071 |
default:
|
| 1072 |
logout("val=0x%02x (undefined RU command)\n", val);
|
| 1073 |
missing("Undefined SU command");
|
| 1074 |
} |
| 1075 |
} |
| 1076 |
|
| 1077 |
static void eepro100_write_command(EEPRO100State * s, uint8_t val) |
| 1078 |
{
|
| 1079 |
eepro100_ru_command(s, val & 0x0f);
|
| 1080 |
eepro100_cu_command(s, val & 0xf0);
|
| 1081 |
if ((val) == 0) { |
| 1082 |
TRACE(OTHER, logout("val=0x%02x\n", val));
|
| 1083 |
} |
| 1084 |
/* Clear command byte after command was accepted. */
|
| 1085 |
s->mem[SCBCmd] = 0;
|
| 1086 |
} |
| 1087 |
|
| 1088 |
/*****************************************************************************
|
| 1089 |
*
|
| 1090 |
* EEPROM emulation.
|
| 1091 |
*
|
| 1092 |
****************************************************************************/
|
| 1093 |
|
| 1094 |
#define EEPROM_CS 0x02 |
| 1095 |
#define EEPROM_SK 0x01 |
| 1096 |
#define EEPROM_DI 0x04 |
| 1097 |
#define EEPROM_DO 0x08 |
| 1098 |
|
| 1099 |
static uint16_t eepro100_read_eeprom(EEPRO100State * s)
|
| 1100 |
{
|
| 1101 |
uint16_t val = e100_read_reg2(s, SCBeeprom); |
| 1102 |
if (eeprom93xx_read(s->eeprom)) {
|
| 1103 |
val |= EEPROM_DO; |
| 1104 |
} else {
|
| 1105 |
val &= ~EEPROM_DO; |
| 1106 |
} |
| 1107 |
TRACE(EEPROM, logout("val=0x%04x\n", val));
|
| 1108 |
return val;
|
| 1109 |
} |
| 1110 |
|
| 1111 |
static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
| 1112 |
{
|
| 1113 |
TRACE(EEPROM, logout("val=0x%02x\n", val));
|
| 1114 |
|
| 1115 |
/* mask unwriteable bits */
|
| 1116 |
#if 0
|
| 1117 |
val = SET_MASKED(val, 0x31, eeprom->value);
|
| 1118 |
#endif
|
| 1119 |
|
| 1120 |
int eecs = ((val & EEPROM_CS) != 0); |
| 1121 |
int eesk = ((val & EEPROM_SK) != 0); |
| 1122 |
int eedi = ((val & EEPROM_DI) != 0); |
| 1123 |
eeprom93xx_write(eeprom, eecs, eesk, eedi); |
| 1124 |
} |
| 1125 |
|
| 1126 |
/*****************************************************************************
|
| 1127 |
*
|
| 1128 |
* MDI emulation.
|
| 1129 |
*
|
| 1130 |
****************************************************************************/
|
| 1131 |
|
| 1132 |
#if defined(DEBUG_EEPRO100)
|
| 1133 |
static const char * const mdi_op_name[] = { |
| 1134 |
"opcode 0",
|
| 1135 |
"write",
|
| 1136 |
"read",
|
| 1137 |
"opcode 3"
|
| 1138 |
}; |
| 1139 |
|
| 1140 |
static const char * const mdi_reg_name[] = { |
| 1141 |
"Control",
|
| 1142 |
"Status",
|
| 1143 |
"PHY Identification (Word 1)",
|
| 1144 |
"PHY Identification (Word 2)",
|
| 1145 |
"Auto-Negotiation Advertisement",
|
| 1146 |
"Auto-Negotiation Link Partner Ability",
|
| 1147 |
"Auto-Negotiation Expansion"
|
| 1148 |
}; |
| 1149 |
|
| 1150 |
static const char *reg2name(uint8_t reg) |
| 1151 |
{
|
| 1152 |
static char buffer[10]; |
| 1153 |
const char *p = buffer; |
| 1154 |
if (reg < ARRAY_SIZE(mdi_reg_name)) {
|
| 1155 |
p = mdi_reg_name[reg]; |
| 1156 |
} else {
|
| 1157 |
snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg); |
| 1158 |
} |
| 1159 |
return p;
|
| 1160 |
} |
| 1161 |
#endif /* DEBUG_EEPRO100 */ |
| 1162 |
|
| 1163 |
static uint32_t eepro100_read_mdi(EEPRO100State * s)
|
| 1164 |
{
|
| 1165 |
uint32_t val = e100_read_reg4(s, SCBCtrlMDI); |
| 1166 |
|
| 1167 |
#ifdef DEBUG_EEPRO100
|
| 1168 |
uint8_t raiseint = (val & BIT(29)) >> 29; |
| 1169 |
uint8_t opcode = (val & BITS(27, 26)) >> 26; |
| 1170 |
uint8_t phy = (val & BITS(25, 21)) >> 21; |
| 1171 |
uint8_t reg = (val & BITS(20, 16)) >> 16; |
| 1172 |
uint16_t data = (val & BITS(15, 0)); |
| 1173 |
#endif
|
| 1174 |
/* Emulation takes no time to finish MDI transaction. */
|
| 1175 |
val |= BIT(28);
|
| 1176 |
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
| 1177 |
val, raiseint, mdi_op_name[opcode], phy, |
| 1178 |
reg2name(reg), data)); |
| 1179 |
return val;
|
| 1180 |
} |
| 1181 |
|
| 1182 |
static void eepro100_write_mdi(EEPRO100State *s) |
| 1183 |
{
|
| 1184 |
uint32_t val = e100_read_reg4(s, SCBCtrlMDI); |
| 1185 |
uint8_t raiseint = (val & BIT(29)) >> 29; |
| 1186 |
uint8_t opcode = (val & BITS(27, 26)) >> 26; |
| 1187 |
uint8_t phy = (val & BITS(25, 21)) >> 21; |
| 1188 |
uint8_t reg = (val & BITS(20, 16)) >> 16; |
| 1189 |
uint16_t data = (val & BITS(15, 0)); |
| 1190 |
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
| 1191 |
val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); |
| 1192 |
if (phy != 1) { |
| 1193 |
/* Unsupported PHY address. */
|
| 1194 |
#if 0
|
| 1195 |
logout("phy must be 1 but is %u\n", phy);
|
| 1196 |
#endif
|
| 1197 |
data = 0;
|
| 1198 |
} else if (opcode != 1 && opcode != 2) { |
| 1199 |
/* Unsupported opcode. */
|
| 1200 |
logout("opcode must be 1 or 2 but is %u\n", opcode);
|
| 1201 |
data = 0;
|
| 1202 |
} else if (reg > 6) { |
| 1203 |
/* Unsupported register. */
|
| 1204 |
logout("register must be 0...6 but is %u\n", reg);
|
| 1205 |
data = 0;
|
| 1206 |
} else {
|
| 1207 |
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
| 1208 |
val, raiseint, mdi_op_name[opcode], phy, |
| 1209 |
reg2name(reg), data)); |
| 1210 |
if (opcode == 1) { |
| 1211 |
/* MDI write */
|
| 1212 |
switch (reg) {
|
| 1213 |
case 0: /* Control Register */ |
| 1214 |
if (data & 0x8000) { |
| 1215 |
/* Reset status and control registers to default. */
|
| 1216 |
s->mdimem[0] = eepro100_mdi_default[0]; |
| 1217 |
s->mdimem[1] = eepro100_mdi_default[1]; |
| 1218 |
data = s->mdimem[reg]; |
| 1219 |
} else {
|
| 1220 |
/* Restart Auto Configuration = Normal Operation */
|
| 1221 |
data &= ~0x0200;
|
| 1222 |
} |
| 1223 |
break;
|
| 1224 |
case 1: /* Status Register */ |
| 1225 |
missing("not writable");
|
| 1226 |
data = s->mdimem[reg]; |
| 1227 |
break;
|
| 1228 |
case 2: /* PHY Identification Register (Word 1) */ |
| 1229 |
case 3: /* PHY Identification Register (Word 2) */ |
| 1230 |
missing("not implemented");
|
| 1231 |
break;
|
| 1232 |
case 4: /* Auto-Negotiation Advertisement Register */ |
| 1233 |
case 5: /* Auto-Negotiation Link Partner Ability Register */ |
| 1234 |
break;
|
| 1235 |
case 6: /* Auto-Negotiation Expansion Register */ |
| 1236 |
default:
|
| 1237 |
missing("not implemented");
|
| 1238 |
} |
| 1239 |
s->mdimem[reg] = data; |
| 1240 |
} else if (opcode == 2) { |
| 1241 |
/* MDI read */
|
| 1242 |
switch (reg) {
|
| 1243 |
case 0: /* Control Register */ |
| 1244 |
if (data & 0x8000) { |
| 1245 |
/* Reset status and control registers to default. */
|
| 1246 |
s->mdimem[0] = eepro100_mdi_default[0]; |
| 1247 |
s->mdimem[1] = eepro100_mdi_default[1]; |
| 1248 |
} |
| 1249 |
break;
|
| 1250 |
case 1: /* Status Register */ |
| 1251 |
s->mdimem[reg] |= 0x0020;
|
| 1252 |
break;
|
| 1253 |
case 2: /* PHY Identification Register (Word 1) */ |
| 1254 |
case 3: /* PHY Identification Register (Word 2) */ |
| 1255 |
case 4: /* Auto-Negotiation Advertisement Register */ |
| 1256 |
break;
|
| 1257 |
case 5: /* Auto-Negotiation Link Partner Ability Register */ |
| 1258 |
s->mdimem[reg] = 0x41fe;
|
| 1259 |
break;
|
| 1260 |
case 6: /* Auto-Negotiation Expansion Register */ |
| 1261 |
s->mdimem[reg] = 0x0001;
|
| 1262 |
break;
|
| 1263 |
} |
| 1264 |
data = s->mdimem[reg]; |
| 1265 |
} |
| 1266 |
/* Emulation takes no time to finish MDI transaction.
|
| 1267 |
* Set MDI bit in SCB status register. */
|
| 1268 |
s->mem[SCBAck] |= 0x08;
|
| 1269 |
val |= BIT(28);
|
| 1270 |
if (raiseint) {
|
| 1271 |
eepro100_mdi_interrupt(s); |
| 1272 |
} |
| 1273 |
} |
| 1274 |
val = (val & 0xffff0000) + data;
|
| 1275 |
e100_write_reg4(s, SCBCtrlMDI, val); |
| 1276 |
} |
| 1277 |
|
| 1278 |
/*****************************************************************************
|
| 1279 |
*
|
| 1280 |
* Port emulation.
|
| 1281 |
*
|
| 1282 |
****************************************************************************/
|
| 1283 |
|
| 1284 |
#define PORT_SOFTWARE_RESET 0 |
| 1285 |
#define PORT_SELFTEST 1 |
| 1286 |
#define PORT_SELECTIVE_RESET 2 |
| 1287 |
#define PORT_DUMP 3 |
| 1288 |
#define PORT_SELECTION_MASK 3 |
| 1289 |
|
| 1290 |
typedef struct { |
| 1291 |
uint32_t st_sign; /* Self Test Signature */
|
| 1292 |
uint32_t st_result; /* Self Test Results */
|
| 1293 |
} eepro100_selftest_t; |
| 1294 |
|
| 1295 |
static uint32_t eepro100_read_port(EEPRO100State * s)
|
| 1296 |
{
|
| 1297 |
return 0; |
| 1298 |
} |
| 1299 |
|
| 1300 |
static void eepro100_write_port(EEPRO100State *s) |
| 1301 |
{
|
| 1302 |
uint32_t val = e100_read_reg4(s, SCBPort); |
| 1303 |
uint32_t address = (val & ~PORT_SELECTION_MASK); |
| 1304 |
uint8_t selection = (val & PORT_SELECTION_MASK); |
| 1305 |
switch (selection) {
|
| 1306 |
case PORT_SOFTWARE_RESET:
|
| 1307 |
nic_reset(s); |
| 1308 |
break;
|
| 1309 |
case PORT_SELFTEST:
|
| 1310 |
TRACE(OTHER, logout("selftest address=0x%08x\n", address));
|
| 1311 |
eepro100_selftest_t data; |
| 1312 |
cpu_physical_memory_read(address, &data, sizeof(data));
|
| 1313 |
data.st_sign = 0xffffffff;
|
| 1314 |
data.st_result = 0;
|
| 1315 |
cpu_physical_memory_write(address, &data, sizeof(data));
|
| 1316 |
break;
|
| 1317 |
case PORT_SELECTIVE_RESET:
|
| 1318 |
TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
|
| 1319 |
nic_selective_reset(s); |
| 1320 |
break;
|
| 1321 |
default:
|
| 1322 |
logout("val=0x%08x\n", val);
|
| 1323 |
missing("unknown port selection");
|
| 1324 |
} |
| 1325 |
} |
| 1326 |
|
| 1327 |
/*****************************************************************************
|
| 1328 |
*
|
| 1329 |
* General hardware emulation.
|
| 1330 |
*
|
| 1331 |
****************************************************************************/
|
| 1332 |
|
| 1333 |
static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
|
| 1334 |
{
|
| 1335 |
uint8_t val = 0;
|
| 1336 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
| 1337 |
val = s->mem[addr]; |
| 1338 |
} |
| 1339 |
|
| 1340 |
switch (addr) {
|
| 1341 |
case SCBStatus:
|
| 1342 |
case SCBAck:
|
| 1343 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1344 |
break;
|
| 1345 |
case SCBCmd:
|
| 1346 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1347 |
#if 0
|
| 1348 |
val = eepro100_read_command(s);
|
| 1349 |
#endif
|
| 1350 |
break;
|
| 1351 |
case SCBIntmask:
|
| 1352 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1353 |
break;
|
| 1354 |
case SCBPort + 3: |
| 1355 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1356 |
break;
|
| 1357 |
case SCBeeprom:
|
| 1358 |
val = eepro100_read_eeprom(s); |
| 1359 |
break;
|
| 1360 |
case SCBCtrlMDI:
|
| 1361 |
case SCBCtrlMDI + 1: |
| 1362 |
case SCBCtrlMDI + 2: |
| 1363 |
case SCBCtrlMDI + 3: |
| 1364 |
val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3))); |
| 1365 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1366 |
break;
|
| 1367 |
case SCBpmdr: /* Power Management Driver Register */ |
| 1368 |
val = 0;
|
| 1369 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1370 |
break;
|
| 1371 |
case SCBgctrl: /* General Control Register */ |
| 1372 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1373 |
break;
|
| 1374 |
case SCBgstat: /* General Status Register */ |
| 1375 |
/* 100 Mbps full duplex, valid link */
|
| 1376 |
val = 0x07;
|
| 1377 |
TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
|
| 1378 |
break;
|
| 1379 |
default:
|
| 1380 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1381 |
missing("unknown byte read");
|
| 1382 |
} |
| 1383 |
return val;
|
| 1384 |
} |
| 1385 |
|
| 1386 |
static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
|
| 1387 |
{
|
| 1388 |
uint16_t val = 0;
|
| 1389 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
| 1390 |
val = e100_read_reg2(s, addr); |
| 1391 |
} |
| 1392 |
|
| 1393 |
switch (addr) {
|
| 1394 |
case SCBStatus:
|
| 1395 |
case SCBCmd:
|
| 1396 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
| 1397 |
break;
|
| 1398 |
case SCBeeprom:
|
| 1399 |
val = eepro100_read_eeprom(s); |
| 1400 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
| 1401 |
break;
|
| 1402 |
case SCBCtrlMDI:
|
| 1403 |
case SCBCtrlMDI + 2: |
| 1404 |
val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3))); |
| 1405 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
| 1406 |
break;
|
| 1407 |
default:
|
| 1408 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
| 1409 |
missing("unknown word read");
|
| 1410 |
} |
| 1411 |
return val;
|
| 1412 |
} |
| 1413 |
|
| 1414 |
static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
|
| 1415 |
{
|
| 1416 |
uint32_t val = 0;
|
| 1417 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
| 1418 |
val = e100_read_reg4(s, addr); |
| 1419 |
} |
| 1420 |
|
| 1421 |
switch (addr) {
|
| 1422 |
case SCBStatus:
|
| 1423 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
| 1424 |
break;
|
| 1425 |
case SCBPointer:
|
| 1426 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
| 1427 |
break;
|
| 1428 |
case SCBPort:
|
| 1429 |
val = eepro100_read_port(s); |
| 1430 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
| 1431 |
break;
|
| 1432 |
case SCBflash:
|
| 1433 |
val = eepro100_read_eeprom(s); |
| 1434 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
| 1435 |
break;
|
| 1436 |
case SCBCtrlMDI:
|
| 1437 |
val = eepro100_read_mdi(s); |
| 1438 |
break;
|
| 1439 |
default:
|
| 1440 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
| 1441 |
missing("unknown longword read");
|
| 1442 |
} |
| 1443 |
return val;
|
| 1444 |
} |
| 1445 |
|
| 1446 |
static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) |
| 1447 |
{
|
| 1448 |
/* SCBStatus is readonly. */
|
| 1449 |
if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) { |
| 1450 |
s->mem[addr] = val; |
| 1451 |
} |
| 1452 |
|
| 1453 |
switch (addr) {
|
| 1454 |
case SCBStatus:
|
| 1455 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1456 |
break;
|
| 1457 |
case SCBAck:
|
| 1458 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1459 |
eepro100_acknowledge(s); |
| 1460 |
break;
|
| 1461 |
case SCBCmd:
|
| 1462 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1463 |
eepro100_write_command(s, val); |
| 1464 |
break;
|
| 1465 |
case SCBIntmask:
|
| 1466 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1467 |
if (val & BIT(1)) { |
| 1468 |
eepro100_swi_interrupt(s); |
| 1469 |
} |
| 1470 |
eepro100_interrupt(s, 0);
|
| 1471 |
break;
|
| 1472 |
case SCBPointer:
|
| 1473 |
case SCBPointer + 1: |
| 1474 |
case SCBPointer + 2: |
| 1475 |
case SCBPointer + 3: |
| 1476 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1477 |
break;
|
| 1478 |
case SCBPort:
|
| 1479 |
case SCBPort + 1: |
| 1480 |
case SCBPort + 2: |
| 1481 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1482 |
break;
|
| 1483 |
case SCBPort + 3: |
| 1484 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1485 |
eepro100_write_port(s); |
| 1486 |
break;
|
| 1487 |
case SCBFlow: /* does not exist on 82557 */ |
| 1488 |
case SCBFlow + 1: |
| 1489 |
case SCBFlow + 2: |
| 1490 |
case SCBpmdr: /* does not exist on 82557 */ |
| 1491 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1492 |
break;
|
| 1493 |
case SCBeeprom:
|
| 1494 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1495 |
eepro100_write_eeprom(s->eeprom, val); |
| 1496 |
break;
|
| 1497 |
case SCBCtrlMDI:
|
| 1498 |
case SCBCtrlMDI + 1: |
| 1499 |
case SCBCtrlMDI + 2: |
| 1500 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1501 |
break;
|
| 1502 |
case SCBCtrlMDI + 3: |
| 1503 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1504 |
eepro100_write_mdi(s); |
| 1505 |
break;
|
| 1506 |
default:
|
| 1507 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1508 |
missing("unknown byte write");
|
| 1509 |
} |
| 1510 |
} |
| 1511 |
|
| 1512 |
static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) |
| 1513 |
{
|
| 1514 |
/* SCBStatus is readonly. */
|
| 1515 |
if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) { |
| 1516 |
e100_write_reg2(s, addr, val); |
| 1517 |
} |
| 1518 |
|
| 1519 |
switch (addr) {
|
| 1520 |
case SCBStatus:
|
| 1521 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
| 1522 |
s->mem[SCBAck] = (val >> 8);
|
| 1523 |
eepro100_acknowledge(s); |
| 1524 |
break;
|
| 1525 |
case SCBCmd:
|
| 1526 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
| 1527 |
eepro100_write_command(s, val); |
| 1528 |
eepro100_write1(s, SCBIntmask, val >> 8);
|
| 1529 |
break;
|
| 1530 |
case SCBPointer:
|
| 1531 |
case SCBPointer + 2: |
| 1532 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
| 1533 |
break;
|
| 1534 |
case SCBPort:
|
| 1535 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
| 1536 |
break;
|
| 1537 |
case SCBPort + 2: |
| 1538 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
| 1539 |
eepro100_write_port(s); |
| 1540 |
break;
|
| 1541 |
case SCBeeprom:
|
| 1542 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
| 1543 |
eepro100_write_eeprom(s->eeprom, val); |
| 1544 |
break;
|
| 1545 |
case SCBCtrlMDI:
|
| 1546 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
| 1547 |
break;
|
| 1548 |
case SCBCtrlMDI + 2: |
| 1549 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
| 1550 |
eepro100_write_mdi(s); |
| 1551 |
break;
|
| 1552 |
default:
|
| 1553 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
| 1554 |
missing("unknown word write");
|
| 1555 |
} |
| 1556 |
} |
| 1557 |
|
| 1558 |
static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) |
| 1559 |
{
|
| 1560 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
| 1561 |
e100_write_reg4(s, addr, val); |
| 1562 |
} |
| 1563 |
|
| 1564 |
switch (addr) {
|
| 1565 |
case SCBPointer:
|
| 1566 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
| 1567 |
break;
|
| 1568 |
case SCBPort:
|
| 1569 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
| 1570 |
eepro100_write_port(s); |
| 1571 |
break;
|
| 1572 |
case SCBflash:
|
| 1573 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
| 1574 |
val = val >> 16;
|
| 1575 |
eepro100_write_eeprom(s->eeprom, val); |
| 1576 |
break;
|
| 1577 |
case SCBCtrlMDI:
|
| 1578 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
| 1579 |
eepro100_write_mdi(s); |
| 1580 |
break;
|
| 1581 |
default:
|
| 1582 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
| 1583 |
missing("unknown longword write");
|
| 1584 |
} |
| 1585 |
} |
| 1586 |
|
| 1587 |
/*****************************************************************************
|
| 1588 |
*
|
| 1589 |
* Port mapped I/O.
|
| 1590 |
*
|
| 1591 |
****************************************************************************/
|
| 1592 |
|
| 1593 |
static uint32_t ioport_read1(void *opaque, uint32_t addr) |
| 1594 |
{
|
| 1595 |
EEPRO100State *s = opaque; |
| 1596 |
#if 0
|
| 1597 |
logout("addr=%s\n", regname(addr));
|
| 1598 |
#endif
|
| 1599 |
return eepro100_read1(s, addr - s->region1);
|
| 1600 |
} |
| 1601 |
|
| 1602 |
static uint32_t ioport_read2(void *opaque, uint32_t addr) |
| 1603 |
{
|
| 1604 |
EEPRO100State *s = opaque; |
| 1605 |
return eepro100_read2(s, addr - s->region1);
|
| 1606 |
} |
| 1607 |
|
| 1608 |
static uint32_t ioport_read4(void *opaque, uint32_t addr) |
| 1609 |
{
|
| 1610 |
EEPRO100State *s = opaque; |
| 1611 |
return eepro100_read4(s, addr - s->region1);
|
| 1612 |
} |
| 1613 |
|
| 1614 |
static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) |
| 1615 |
{
|
| 1616 |
EEPRO100State *s = opaque; |
| 1617 |
#if 0
|
| 1618 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1619 |
#endif
|
| 1620 |
eepro100_write1(s, addr - s->region1, val); |
| 1621 |
} |
| 1622 |
|
| 1623 |
static void ioport_write2(void *opaque, uint32_t addr, uint32_t val) |
| 1624 |
{
|
| 1625 |
EEPRO100State *s = opaque; |
| 1626 |
eepro100_write2(s, addr - s->region1, val); |
| 1627 |
} |
| 1628 |
|
| 1629 |
static void ioport_write4(void *opaque, uint32_t addr, uint32_t val) |
| 1630 |
{
|
| 1631 |
EEPRO100State *s = opaque; |
| 1632 |
eepro100_write4(s, addr - s->region1, val); |
| 1633 |
} |
| 1634 |
|
| 1635 |
/***********************************************************/
|
| 1636 |
/* PCI EEPRO100 definitions */
|
| 1637 |
|
| 1638 |
static void pci_map(PCIDevice * pci_dev, int region_num, |
| 1639 |
pcibus_t addr, pcibus_t size, int type)
|
| 1640 |
{
|
| 1641 |
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
| 1642 |
|
| 1643 |
TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
| 1644 |
"size=0x%08"FMT_PCIBUS", type=%d\n", |
| 1645 |
region_num, addr, size, type)); |
| 1646 |
|
| 1647 |
assert(region_num == 1);
|
| 1648 |
register_ioport_write(addr, size, 1, ioport_write1, s);
|
| 1649 |
register_ioport_read(addr, size, 1, ioport_read1, s);
|
| 1650 |
register_ioport_write(addr, size, 2, ioport_write2, s);
|
| 1651 |
register_ioport_read(addr, size, 2, ioport_read2, s);
|
| 1652 |
register_ioport_write(addr, size, 4, ioport_write4, s);
|
| 1653 |
register_ioport_read(addr, size, 4, ioport_read4, s);
|
| 1654 |
|
| 1655 |
s->region1 = addr; |
| 1656 |
} |
| 1657 |
|
| 1658 |
/*****************************************************************************
|
| 1659 |
*
|
| 1660 |
* Memory mapped I/O.
|
| 1661 |
*
|
| 1662 |
****************************************************************************/
|
| 1663 |
|
| 1664 |
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1665 |
{
|
| 1666 |
EEPRO100State *s = opaque; |
| 1667 |
#if 0
|
| 1668 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1669 |
#endif
|
| 1670 |
eepro100_write1(s, addr, val); |
| 1671 |
} |
| 1672 |
|
| 1673 |
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1674 |
{
|
| 1675 |
EEPRO100State *s = opaque; |
| 1676 |
#if 0
|
| 1677 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1678 |
#endif
|
| 1679 |
eepro100_write2(s, addr, val); |
| 1680 |
} |
| 1681 |
|
| 1682 |
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1683 |
{
|
| 1684 |
EEPRO100State *s = opaque; |
| 1685 |
#if 0
|
| 1686 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1687 |
#endif
|
| 1688 |
eepro100_write4(s, addr, val); |
| 1689 |
} |
| 1690 |
|
| 1691 |
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
| 1692 |
{
|
| 1693 |
EEPRO100State *s = opaque; |
| 1694 |
#if 0
|
| 1695 |
logout("addr=%s\n", regname(addr));
|
| 1696 |
#endif
|
| 1697 |
return eepro100_read1(s, addr);
|
| 1698 |
} |
| 1699 |
|
| 1700 |
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
| 1701 |
{
|
| 1702 |
EEPRO100State *s = opaque; |
| 1703 |
#if 0
|
| 1704 |
logout("addr=%s\n", regname(addr));
|
| 1705 |
#endif
|
| 1706 |
return eepro100_read2(s, addr);
|
| 1707 |
} |
| 1708 |
|
| 1709 |
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
| 1710 |
{
|
| 1711 |
EEPRO100State *s = opaque; |
| 1712 |
#if 0
|
| 1713 |
logout("addr=%s\n", regname(addr));
|
| 1714 |
#endif
|
| 1715 |
return eepro100_read4(s, addr);
|
| 1716 |
} |
| 1717 |
|
| 1718 |
static CPUWriteMemoryFunc * const pci_mmio_write[] = { |
| 1719 |
pci_mmio_writeb, |
| 1720 |
pci_mmio_writew, |
| 1721 |
pci_mmio_writel |
| 1722 |
}; |
| 1723 |
|
| 1724 |
static CPUReadMemoryFunc * const pci_mmio_read[] = { |
| 1725 |
pci_mmio_readb, |
| 1726 |
pci_mmio_readw, |
| 1727 |
pci_mmio_readl |
| 1728 |
}; |
| 1729 |
|
| 1730 |
static int nic_can_receive(VLANClientState *nc) |
| 1731 |
{
|
| 1732 |
EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
| 1733 |
TRACE(RXTX, logout("%p\n", s));
|
| 1734 |
return get_ru_state(s) == ru_ready;
|
| 1735 |
#if 0
|
| 1736 |
return !eepro100_buffer_full(s);
|
| 1737 |
#endif
|
| 1738 |
} |
| 1739 |
|
| 1740 |
static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size) |
| 1741 |
{
|
| 1742 |
/* TODO:
|
| 1743 |
* - Magic packets should set bit 30 in power management driver register.
|
| 1744 |
* - Interesting packets should set bit 29 in power management driver register.
|
| 1745 |
*/
|
| 1746 |
EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
| 1747 |
uint16_t rfd_status = 0xa000;
|
| 1748 |
#if defined(CONFIG_PAD_RECEIVED_FRAMES)
|
| 1749 |
uint8_t min_buf[60];
|
| 1750 |
#endif
|
| 1751 |
static const uint8_t broadcast_macaddr[6] = |
| 1752 |
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
|
| 1753 |
|
| 1754 |
#if defined(CONFIG_PAD_RECEIVED_FRAMES)
|
| 1755 |
/* Pad to minimum Ethernet frame length */
|
| 1756 |
if (size < sizeof(min_buf)) { |
| 1757 |
memcpy(min_buf, buf, size); |
| 1758 |
memset(&min_buf[size], 0, sizeof(min_buf) - size); |
| 1759 |
buf = min_buf; |
| 1760 |
size = sizeof(min_buf);
|
| 1761 |
} |
| 1762 |
#endif
|
| 1763 |
|
| 1764 |
if (s->configuration[8] & 0x80) { |
| 1765 |
/* CSMA is disabled. */
|
| 1766 |
logout("%p received while CSMA is disabled\n", s);
|
| 1767 |
return -1; |
| 1768 |
#if !defined(CONFIG_PAD_RECEIVED_FRAMES)
|
| 1769 |
} else if (size < 64 && (s->configuration[7] & BIT(0))) { |
| 1770 |
/* Short frame and configuration byte 7/0 (discard short receive) set:
|
| 1771 |
* Short frame is discarded */
|
| 1772 |
logout("%p received short frame (%zu byte)\n", s, size);
|
| 1773 |
s->statistics.rx_short_frame_errors++; |
| 1774 |
return -1; |
| 1775 |
#endif
|
| 1776 |
} else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) { |
| 1777 |
/* Long frame and configuration byte 18/3 (long receive ok) not set:
|
| 1778 |
* Long frames are discarded. */
|
| 1779 |
logout("%p received long frame (%zu byte), ignored\n", s, size);
|
| 1780 |
return -1; |
| 1781 |
} else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */ |
| 1782 |
/* Frame matches individual address. */
|
| 1783 |
/* TODO: check configuration byte 15/4 (ignore U/L). */
|
| 1784 |
TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
|
| 1785 |
} else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
| 1786 |
/* Broadcast frame. */
|
| 1787 |
TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
|
| 1788 |
rfd_status |= 0x0002;
|
| 1789 |
} else if (buf[0] & 0x01) { |
| 1790 |
/* Multicast frame. */
|
| 1791 |
TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
|
| 1792 |
if (s->configuration[21] & BIT(3)) { |
| 1793 |
/* Multicast all bit is set, receive all multicast frames. */
|
| 1794 |
} else {
|
| 1795 |
unsigned mcast_idx = compute_mcast_idx(buf);
|
| 1796 |
assert(mcast_idx < 64);
|
| 1797 |
if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) { |
| 1798 |
/* Multicast frame is allowed in hash table. */
|
| 1799 |
} else if (s->configuration[15] & BIT(0)) { |
| 1800 |
/* Promiscuous: receive all. */
|
| 1801 |
rfd_status |= 0x0004;
|
| 1802 |
} else {
|
| 1803 |
TRACE(RXTX, logout("%p multicast ignored\n", s));
|
| 1804 |
return -1; |
| 1805 |
} |
| 1806 |
} |
| 1807 |
/* TODO: Next not for promiscuous mode? */
|
| 1808 |
rfd_status |= 0x0002;
|
| 1809 |
} else if (s->configuration[15] & BIT(0)) { |
| 1810 |
/* Promiscuous: receive all. */
|
| 1811 |
TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
|
| 1812 |
rfd_status |= 0x0004;
|
| 1813 |
} else if (s->configuration[20] & BIT(6)) { |
| 1814 |
/* Multiple IA bit set. */
|
| 1815 |
unsigned mcast_idx = compute_mcast_idx(buf);
|
| 1816 |
assert(mcast_idx < 64);
|
| 1817 |
if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) { |
| 1818 |
TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
|
| 1819 |
} else {
|
| 1820 |
TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
|
| 1821 |
return -1; |
| 1822 |
} |
| 1823 |
} else {
|
| 1824 |
TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
|
| 1825 |
nic_dump(buf, size))); |
| 1826 |
return size;
|
| 1827 |
} |
| 1828 |
|
| 1829 |
if (get_ru_state(s) != ru_ready) {
|
| 1830 |
/* No resources available. */
|
| 1831 |
logout("no resources, state=%u\n", get_ru_state(s));
|
| 1832 |
/* TODO: RNR interrupt only at first failed frame? */
|
| 1833 |
eepro100_rnr_interrupt(s); |
| 1834 |
s->statistics.rx_resource_errors++; |
| 1835 |
#if 0
|
| 1836 |
assert(!"no resources");
|
| 1837 |
#endif
|
| 1838 |
return -1; |
| 1839 |
} |
| 1840 |
/* !!! */
|
| 1841 |
eepro100_rx_t rx; |
| 1842 |
cpu_physical_memory_read(s->ru_base + s->ru_offset, &rx, |
| 1843 |
sizeof(eepro100_rx_t));
|
| 1844 |
uint16_t rfd_command = le16_to_cpu(rx.command); |
| 1845 |
uint16_t rfd_size = le16_to_cpu(rx.size); |
| 1846 |
|
| 1847 |
if (size > rfd_size) {
|
| 1848 |
logout("Receive buffer (%" PRId16 " bytes) too small for data " |
| 1849 |
"(%zu bytes); data truncated\n", rfd_size, size);
|
| 1850 |
size = rfd_size; |
| 1851 |
} |
| 1852 |
#if !defined(CONFIG_PAD_RECEIVED_FRAMES)
|
| 1853 |
if (size < 64) { |
| 1854 |
rfd_status |= 0x0080;
|
| 1855 |
} |
| 1856 |
#endif
|
| 1857 |
TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
|
| 1858 |
rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); |
| 1859 |
e100_stw_le_phys(s->ru_base + s->ru_offset + |
| 1860 |
offsetof(eepro100_rx_t, status), rfd_status); |
| 1861 |
e100_stw_le_phys(s->ru_base + s->ru_offset + |
| 1862 |
offsetof(eepro100_rx_t, count), size); |
| 1863 |
/* Early receive interrupt not supported. */
|
| 1864 |
#if 0
|
| 1865 |
eepro100_er_interrupt(s);
|
| 1866 |
#endif
|
| 1867 |
/* Receive CRC Transfer not supported. */
|
| 1868 |
if (s->configuration[18] & BIT(2)) { |
| 1869 |
missing("Receive CRC Transfer");
|
| 1870 |
return -1; |
| 1871 |
} |
| 1872 |
/* TODO: check stripping enable bit. */
|
| 1873 |
#if 0
|
| 1874 |
assert(!(s->configuration[17] & BIT(0)));
|
| 1875 |
#endif
|
| 1876 |
cpu_physical_memory_write(s->ru_base + s->ru_offset + |
| 1877 |
sizeof(eepro100_rx_t), buf, size);
|
| 1878 |
s->statistics.rx_good_frames++; |
| 1879 |
eepro100_fr_interrupt(s); |
| 1880 |
s->ru_offset = le32_to_cpu(rx.link); |
| 1881 |
if (rfd_command & COMMAND_EL) {
|
| 1882 |
/* EL bit is set, so this was the last frame. */
|
| 1883 |
logout("receive: Running out of frames\n");
|
| 1884 |
set_ru_state(s, ru_suspended); |
| 1885 |
} |
| 1886 |
if (rfd_command & COMMAND_S) {
|
| 1887 |
/* S bit is set. */
|
| 1888 |
set_ru_state(s, ru_suspended); |
| 1889 |
} |
| 1890 |
return size;
|
| 1891 |
} |
| 1892 |
|
| 1893 |
static const VMStateDescription vmstate_eepro100 = { |
| 1894 |
.version_id = 3,
|
| 1895 |
.minimum_version_id = 2,
|
| 1896 |
.minimum_version_id_old = 2,
|
| 1897 |
.fields = (VMStateField []) {
|
| 1898 |
VMSTATE_PCI_DEVICE(dev, EEPRO100State), |
| 1899 |
VMSTATE_UNUSED(32),
|
| 1900 |
VMSTATE_BUFFER(mult, EEPRO100State), |
| 1901 |
VMSTATE_BUFFER(mem, EEPRO100State), |
| 1902 |
/* Save all members of struct between scb_stat and mem. */
|
| 1903 |
VMSTATE_UINT8(scb_stat, EEPRO100State), |
| 1904 |
VMSTATE_UINT8(int_stat, EEPRO100State), |
| 1905 |
VMSTATE_UNUSED(3*4), |
| 1906 |
VMSTATE_MACADDR(conf.macaddr, EEPRO100State), |
| 1907 |
VMSTATE_UNUSED(19*4), |
| 1908 |
VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
|
| 1909 |
/* The eeprom should be saved and restored by its own routines. */
|
| 1910 |
VMSTATE_UINT32(device, EEPRO100State), |
| 1911 |
/* TODO check device. */
|
| 1912 |
VMSTATE_UINT32(cu_base, EEPRO100State), |
| 1913 |
VMSTATE_UINT32(cu_offset, EEPRO100State), |
| 1914 |
VMSTATE_UINT32(ru_base, EEPRO100State), |
| 1915 |
VMSTATE_UINT32(ru_offset, EEPRO100State), |
| 1916 |
VMSTATE_UINT32(statsaddr, EEPRO100State), |
| 1917 |
/* Save eepro100_stats_t statistics. */
|
| 1918 |
VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State), |
| 1919 |
VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State), |
| 1920 |
VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State), |
| 1921 |
VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State), |
| 1922 |
VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State), |
| 1923 |
VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State), |
| 1924 |
VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State), |
| 1925 |
VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State), |
| 1926 |
VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State), |
| 1927 |
VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State), |
| 1928 |
VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State), |
| 1929 |
VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State), |
| 1930 |
VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State), |
| 1931 |
VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State), |
| 1932 |
VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State), |
| 1933 |
VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State), |
| 1934 |
VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State), |
| 1935 |
VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State), |
| 1936 |
VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State), |
| 1937 |
VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State), |
| 1938 |
VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State), |
| 1939 |
/* Configuration bytes. */
|
| 1940 |
VMSTATE_BUFFER(configuration, EEPRO100State), |
| 1941 |
VMSTATE_END_OF_LIST() |
| 1942 |
} |
| 1943 |
}; |
| 1944 |
|
| 1945 |
static void nic_cleanup(VLANClientState *nc) |
| 1946 |
{
|
| 1947 |
EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
| 1948 |
|
| 1949 |
s->nic = NULL;
|
| 1950 |
} |
| 1951 |
|
| 1952 |
static int pci_nic_uninit(PCIDevice *pci_dev) |
| 1953 |
{
|
| 1954 |
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
| 1955 |
|
| 1956 |
cpu_unregister_io_memory(s->mmio_index); |
| 1957 |
vmstate_unregister(&pci_dev->qdev, s->vmstate, s); |
| 1958 |
eeprom93xx_free(&pci_dev->qdev, s->eeprom); |
| 1959 |
qemu_del_vlan_client(&s->nic->nc); |
| 1960 |
return 0; |
| 1961 |
} |
| 1962 |
|
| 1963 |
static NetClientInfo net_eepro100_info = {
|
| 1964 |
.type = NET_CLIENT_TYPE_NIC, |
| 1965 |
.size = sizeof(NICState),
|
| 1966 |
.can_receive = nic_can_receive, |
| 1967 |
.receive = nic_receive, |
| 1968 |
.cleanup = nic_cleanup, |
| 1969 |
}; |
| 1970 |
|
| 1971 |
static int e100_nic_init(PCIDevice *pci_dev) |
| 1972 |
{
|
| 1973 |
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
| 1974 |
E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev, |
| 1975 |
pci_dev->qdev.info); |
| 1976 |
|
| 1977 |
TRACE(OTHER, logout("\n"));
|
| 1978 |
|
| 1979 |
s->device = e100_device->device; |
| 1980 |
|
| 1981 |
e100_pci_reset(s, e100_device); |
| 1982 |
|
| 1983 |
/* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
|
| 1984 |
* i82559 and later support 64 or 256 word EEPROM. */
|
| 1985 |
s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE); |
| 1986 |
|
| 1987 |
/* Handler for memory-mapped I/O */
|
| 1988 |
s->mmio_index = |
| 1989 |
cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s, |
| 1990 |
DEVICE_LITTLE_ENDIAN); |
| 1991 |
|
| 1992 |
pci_register_bar_simple(&s->dev, 0, PCI_MEM_SIZE,
|
| 1993 |
PCI_BASE_ADDRESS_MEM_PREFETCH, s->mmio_index); |
| 1994 |
|
| 1995 |
pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
|
| 1996 |
pci_map); |
| 1997 |
pci_register_bar_simple(&s->dev, 2, PCI_FLASH_SIZE, 0, s->mmio_index); |
| 1998 |
|
| 1999 |
qemu_macaddr_default_if_unset(&s->conf.macaddr); |
| 2000 |
logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)); |
| 2001 |
assert(s->region1 == 0);
|
| 2002 |
|
| 2003 |
nic_reset(s); |
| 2004 |
|
| 2005 |
s->nic = qemu_new_nic(&net_eepro100_info, &s->conf, |
| 2006 |
pci_dev->qdev.info->name, pci_dev->qdev.id, s); |
| 2007 |
|
| 2008 |
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
| 2009 |
TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
|
| 2010 |
|
| 2011 |
qemu_register_reset(nic_reset, s); |
| 2012 |
|
| 2013 |
s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
|
| 2014 |
memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
|
| 2015 |
s->vmstate->name = s->nic->nc.model; |
| 2016 |
vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
|
| 2017 |
|
| 2018 |
add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
|
| 2019 |
|
| 2020 |
return 0; |
| 2021 |
} |
| 2022 |
|
| 2023 |
static E100PCIDeviceInfo e100_devices[] = {
|
| 2024 |
{
|
| 2025 |
.pci.qdev.name = "i82550",
|
| 2026 |
.pci.qdev.desc = "Intel i82550 Ethernet",
|
| 2027 |
.device = i82550, |
| 2028 |
/* TODO: check device id. */
|
| 2029 |
.pci.device_id = PCI_DEVICE_ID_INTEL_82551IT, |
| 2030 |
/* Revision ID: 0x0c, 0x0d, 0x0e. */
|
| 2031 |
.pci.revision = 0x0e,
|
| 2032 |
/* TODO: check size of statistical counters. */
|
| 2033 |
.stats_size = 80,
|
| 2034 |
/* TODO: check extended tcb support. */
|
| 2035 |
.has_extended_tcb_support = true,
|
| 2036 |
.power_management = true,
|
| 2037 |
},{
|
| 2038 |
.pci.qdev.name = "i82551",
|
| 2039 |
.pci.qdev.desc = "Intel i82551 Ethernet",
|
| 2040 |
.device = i82551, |
| 2041 |
.pci.device_id = PCI_DEVICE_ID_INTEL_82551IT, |
| 2042 |
/* Revision ID: 0x0f, 0x10. */
|
| 2043 |
.pci.revision = 0x0f,
|
| 2044 |
/* TODO: check size of statistical counters. */
|
| 2045 |
.stats_size = 80,
|
| 2046 |
.has_extended_tcb_support = true,
|
| 2047 |
.power_management = true,
|
| 2048 |
},{
|
| 2049 |
.pci.qdev.name = "i82557a",
|
| 2050 |
.pci.qdev.desc = "Intel i82557A Ethernet",
|
| 2051 |
.device = i82557A, |
| 2052 |
.pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
| 2053 |
.pci.revision = 0x01,
|
| 2054 |
.power_management = false,
|
| 2055 |
},{
|
| 2056 |
.pci.qdev.name = "i82557b",
|
| 2057 |
.pci.qdev.desc = "Intel i82557B Ethernet",
|
| 2058 |
.device = i82557B, |
| 2059 |
.pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
| 2060 |
.pci.revision = 0x02,
|
| 2061 |
.power_management = false,
|
| 2062 |
},{
|
| 2063 |
.pci.qdev.name = "i82557c",
|
| 2064 |
.pci.qdev.desc = "Intel i82557C Ethernet",
|
| 2065 |
.device = i82557C, |
| 2066 |
.pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
| 2067 |
.pci.revision = 0x03,
|
| 2068 |
.power_management = false,
|
| 2069 |
},{
|
| 2070 |
.pci.qdev.name = "i82558a",
|
| 2071 |
.pci.qdev.desc = "Intel i82558A Ethernet",
|
| 2072 |
.device = i82558A, |
| 2073 |
.pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
| 2074 |
.pci.revision = 0x04,
|
| 2075 |
.stats_size = 76,
|
| 2076 |
.has_extended_tcb_support = true,
|
| 2077 |
.power_management = true,
|
| 2078 |
},{
|
| 2079 |
.pci.qdev.name = "i82558b",
|
| 2080 |
.pci.qdev.desc = "Intel i82558B Ethernet",
|
| 2081 |
.device = i82558B, |
| 2082 |
.pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
| 2083 |
.pci.revision = 0x05,
|
| 2084 |
.stats_size = 76,
|
| 2085 |
.has_extended_tcb_support = true,
|
| 2086 |
.power_management = true,
|
| 2087 |
},{
|
| 2088 |
.pci.qdev.name = "i82559a",
|
| 2089 |
.pci.qdev.desc = "Intel i82559A Ethernet",
|
| 2090 |
.device = i82559A, |
| 2091 |
.pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
| 2092 |
.pci.revision = 0x06,
|
| 2093 |
.stats_size = 80,
|
| 2094 |
.has_extended_tcb_support = true,
|
| 2095 |
.power_management = true,
|
| 2096 |
},{
|
| 2097 |
.pci.qdev.name = "i82559b",
|
| 2098 |
.pci.qdev.desc = "Intel i82559B Ethernet",
|
| 2099 |
.device = i82559B, |
| 2100 |
.pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
| 2101 |
.pci.revision = 0x07,
|
| 2102 |
.stats_size = 80,
|
| 2103 |
.has_extended_tcb_support = true,
|
| 2104 |
.power_management = true,
|
| 2105 |
},{
|
| 2106 |
.pci.qdev.name = "i82559c",
|
| 2107 |
.pci.qdev.desc = "Intel i82559C Ethernet",
|
| 2108 |
.device = i82559C, |
| 2109 |
.pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
| 2110 |
#if 0
|
| 2111 |
.pci.revision = 0x08,
|
| 2112 |
#endif
|
| 2113 |
/* TODO: Windows wants revision id 0x0c. */
|
| 2114 |
.pci.revision = 0x0c,
|
| 2115 |
#if EEPROM_SIZE > 0 |
| 2116 |
.pci.subsystem_vendor_id = PCI_VENDOR_ID_INTEL, |
| 2117 |
.pci.subsystem_id = 0x0040,
|
| 2118 |
#endif
|
| 2119 |
.stats_size = 80,
|
| 2120 |
.has_extended_tcb_support = true,
|
| 2121 |
.power_management = true,
|
| 2122 |
},{
|
| 2123 |
.pci.qdev.name = "i82559er",
|
| 2124 |
.pci.qdev.desc = "Intel i82559ER Ethernet",
|
| 2125 |
.device = i82559ER, |
| 2126 |
.pci.device_id = PCI_DEVICE_ID_INTEL_82551IT, |
| 2127 |
.pci.revision = 0x09,
|
| 2128 |
.stats_size = 80,
|
| 2129 |
.has_extended_tcb_support = true,
|
| 2130 |
.power_management = true,
|
| 2131 |
},{
|
| 2132 |
.pci.qdev.name = "i82562",
|
| 2133 |
.pci.qdev.desc = "Intel i82562 Ethernet",
|
| 2134 |
.device = i82562, |
| 2135 |
/* TODO: check device id. */
|
| 2136 |
.pci.device_id = PCI_DEVICE_ID_INTEL_82551IT, |
| 2137 |
/* TODO: wrong revision id. */
|
| 2138 |
.pci.revision = 0x0e,
|
| 2139 |
.stats_size = 80,
|
| 2140 |
.has_extended_tcb_support = true,
|
| 2141 |
.power_management = true,
|
| 2142 |
},{
|
| 2143 |
/* Toshiba Tecra 8200. */
|
| 2144 |
.pci.qdev.name = "i82801",
|
| 2145 |
.pci.qdev.desc = "Intel i82801 Ethernet",
|
| 2146 |
.device = i82801, |
| 2147 |
.pci.device_id = 0x2449,
|
| 2148 |
.pci.revision = 0x03,
|
| 2149 |
.stats_size = 80,
|
| 2150 |
.has_extended_tcb_support = true,
|
| 2151 |
.power_management = true,
|
| 2152 |
} |
| 2153 |
}; |
| 2154 |
|
| 2155 |
static Property e100_properties[] = {
|
| 2156 |
DEFINE_NIC_PROPERTIES(EEPRO100State, conf), |
| 2157 |
DEFINE_PROP_END_OF_LIST(), |
| 2158 |
}; |
| 2159 |
|
| 2160 |
static void eepro100_register_devices(void) |
| 2161 |
{
|
| 2162 |
size_t i; |
| 2163 |
for (i = 0; i < ARRAY_SIZE(e100_devices); i++) { |
| 2164 |
PCIDeviceInfo *pci_dev = &e100_devices[i].pci; |
| 2165 |
/* We use the same rom file for all device ids.
|
| 2166 |
QEMU fixes the device id during rom load. */
|
| 2167 |
pci_dev->vendor_id = PCI_VENDOR_ID_INTEL; |
| 2168 |
pci_dev->class_id = PCI_CLASS_NETWORK_ETHERNET; |
| 2169 |
pci_dev->romfile = "pxe-eepro100.rom";
|
| 2170 |
pci_dev->init = e100_nic_init; |
| 2171 |
pci_dev->exit = pci_nic_uninit; |
| 2172 |
pci_dev->qdev.props = e100_properties; |
| 2173 |
pci_dev->qdev.size = sizeof(EEPRO100State);
|
| 2174 |
pci_qdev_register(pci_dev); |
| 2175 |
} |
| 2176 |
} |
| 2177 |
|
| 2178 |
device_init(eepro100_register_devices) |