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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "tcg.h"
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int gen_new_label(void);
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static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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}
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static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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}
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static inline void tcg_gen_op1i(int opc, TCGArg arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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}
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static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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}
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static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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}
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static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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}
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static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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}
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static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base,
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                                       TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base,
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                                       TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr,
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                                                TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I32(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr,
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                                                TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I64(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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}
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static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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}
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static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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}
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static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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}
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static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
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                                   TCGv_i32 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
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}
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static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
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                                   TCGv_i64 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
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}
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static inline void tcg_gen_op6i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGv_i32 arg4,
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                                    TCGv_i32 arg5, TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void tcg_gen_op6i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGv_i64 arg4,
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                                    TCGv_i64 arg5, TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                     TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5,
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                                     TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = arg5;
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
323 a7812ae4 pbrook
                                     TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5,
324 a7812ae4 pbrook
                                     TCGArg arg6)
325 a7812ae4 pbrook
{
326 a7812ae4 pbrook
    *gen_opc_ptr++ = opc;
327 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
328 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
329 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
330 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
331 c896fe29 bellard
    *gen_opparam_ptr++ = arg5;
332 c896fe29 bellard
    *gen_opparam_ptr++ = arg6;
333 c896fe29 bellard
}
334 c896fe29 bellard
335 c896fe29 bellard
static inline void gen_set_label(int n)
336 c896fe29 bellard
{
337 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_set_label, n);
338 c896fe29 bellard
}
339 c896fe29 bellard
340 fb50d413 blueswir1
static inline void tcg_gen_br(int label)
341 fb50d413 blueswir1
{
342 fb50d413 blueswir1
    tcg_gen_op1i(INDEX_op_br, label);
343 fb50d413 blueswir1
}
344 fb50d413 blueswir1
345 a7812ae4 pbrook
static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
346 c896fe29 bellard
{
347 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I32(ret, arg))
348 a7812ae4 pbrook
        tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
349 c896fe29 bellard
}
350 c896fe29 bellard
351 a7812ae4 pbrook
static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
352 c896fe29 bellard
{
353 a7812ae4 pbrook
    tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
354 c896fe29 bellard
}
355 c896fe29 bellard
356 c896fe29 bellard
/* helper calls */
357 a7812ae4 pbrook
static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
358 a7812ae4 pbrook
                                   TCGArg ret, int nargs, TCGArg *args)
359 a7812ae4 pbrook
{
360 a7812ae4 pbrook
    TCGv_ptr fn;
361 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
362 a7812ae4 pbrook
    tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
363 a7812ae4 pbrook
                  nargs, args);
364 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
365 a7812ae4 pbrook
}
366 c896fe29 bellard
367 a7812ae4 pbrook
/* FIXME: Should this be pure?  */
368 a7812ae4 pbrook
static inline void tcg_gen_helper64(void *func, TCGv_i64 ret,
369 a7812ae4 pbrook
                                    TCGv_i64 a, TCGv_i64 b)
370 c896fe29 bellard
{
371 a7812ae4 pbrook
    TCGv_ptr fn;
372 a7812ae4 pbrook
    TCGArg args[2];
373 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
374 a7812ae4 pbrook
    args[0] = GET_TCGV_I64(a);
375 a7812ae4 pbrook
    args[1] = GET_TCGV_I64(b);
376 a7812ae4 pbrook
    tcg_gen_callN(&tcg_ctx, fn, 0, 7, GET_TCGV_I64(ret), 2, args);
377 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
378 f8422f52 blueswir1
}
379 f8422f52 blueswir1
380 c896fe29 bellard
/* 32 bit ops */
381 c896fe29 bellard
382 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
383 c896fe29 bellard
{
384 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
385 c896fe29 bellard
}
386 c896fe29 bellard
387 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
388 c896fe29 bellard
{
389 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
390 c896fe29 bellard
}
391 c896fe29 bellard
392 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
393 c896fe29 bellard
{
394 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
395 c896fe29 bellard
}
396 c896fe29 bellard
397 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
398 c896fe29 bellard
{
399 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
400 c896fe29 bellard
}
401 c896fe29 bellard
402 a7812ae4 pbrook
static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
403 c896fe29 bellard
{
404 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
405 c896fe29 bellard
}
406 c896fe29 bellard
407 a7812ae4 pbrook
static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
408 c896fe29 bellard
{
409 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
410 c896fe29 bellard
}
411 c896fe29 bellard
412 a7812ae4 pbrook
static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
413 c896fe29 bellard
{
414 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
415 c896fe29 bellard
}
416 c896fe29 bellard
417 a7812ae4 pbrook
static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
418 c896fe29 bellard
{
419 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
420 c896fe29 bellard
}
421 c896fe29 bellard
422 a7812ae4 pbrook
static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
423 c896fe29 bellard
{
424 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
425 c896fe29 bellard
}
426 c896fe29 bellard
427 a7812ae4 pbrook
static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
428 c896fe29 bellard
{
429 7089442c blueswir1
    /* some cases can be optimized here */
430 7089442c blueswir1
    if (arg2 == 0) {
431 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
432 7089442c blueswir1
    } else {
433 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
434 e8996ee0 bellard
        tcg_gen_add_i32(ret, arg1, t0);
435 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
436 7089442c blueswir1
    }
437 c896fe29 bellard
}
438 c896fe29 bellard
439 a7812ae4 pbrook
static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
440 c896fe29 bellard
{
441 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
442 c896fe29 bellard
}
443 c896fe29 bellard
444 a7812ae4 pbrook
static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
445 0045734a aurel32
{
446 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg1);
447 0045734a aurel32
    tcg_gen_sub_i32(ret, t0, arg2);
448 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
449 0045734a aurel32
}
450 0045734a aurel32
451 a7812ae4 pbrook
static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
452 c896fe29 bellard
{
453 7089442c blueswir1
    /* some cases can be optimized here */
454 7089442c blueswir1
    if (arg2 == 0) {
455 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
456 7089442c blueswir1
    } else {
457 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
458 e8996ee0 bellard
        tcg_gen_sub_i32(ret, arg1, t0);
459 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
460 7089442c blueswir1
    }
461 c896fe29 bellard
}
462 c896fe29 bellard
463 a7812ae4 pbrook
static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
464 c896fe29 bellard
{
465 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
466 7fc81051 aurel32
        tcg_gen_mov_i32(ret, arg1);
467 7fc81051 aurel32
    } else {
468 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
469 7fc81051 aurel32
    }
470 c896fe29 bellard
}
471 c896fe29 bellard
472 a7812ae4 pbrook
static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
473 c896fe29 bellard
{
474 c896fe29 bellard
    /* some cases can be optimized here */
475 c896fe29 bellard
    if (arg2 == 0) {
476 c896fe29 bellard
        tcg_gen_movi_i32(ret, 0);
477 c896fe29 bellard
    } else if (arg2 == 0xffffffff) {
478 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
479 c896fe29 bellard
    } else {
480 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
481 e8996ee0 bellard
        tcg_gen_and_i32(ret, arg1, t0);
482 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
483 c896fe29 bellard
    }
484 c896fe29 bellard
}
485 c896fe29 bellard
486 a7812ae4 pbrook
static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
487 c896fe29 bellard
{
488 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
489 7fc81051 aurel32
        tcg_gen_mov_i32(ret, arg1);
490 7fc81051 aurel32
    } else {
491 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
492 7fc81051 aurel32
    }
493 c896fe29 bellard
}
494 c896fe29 bellard
495 a7812ae4 pbrook
static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
496 c896fe29 bellard
{
497 c896fe29 bellard
    /* some cases can be optimized here */
498 c896fe29 bellard
    if (arg2 == 0xffffffff) {
499 7089442c blueswir1
        tcg_gen_movi_i32(ret, 0xffffffff);
500 c896fe29 bellard
    } else if (arg2 == 0) {
501 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
502 c896fe29 bellard
    } else {
503 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
504 e8996ee0 bellard
        tcg_gen_or_i32(ret, arg1, t0);
505 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
506 c896fe29 bellard
    }
507 c896fe29 bellard
}
508 c896fe29 bellard
509 a7812ae4 pbrook
static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
510 c896fe29 bellard
{
511 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
512 7fc81051 aurel32
        tcg_gen_movi_i32(ret, 0);
513 7fc81051 aurel32
    } else {
514 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
515 7fc81051 aurel32
    }
516 c896fe29 bellard
}
517 c896fe29 bellard
518 a7812ae4 pbrook
static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
519 c896fe29 bellard
{
520 c896fe29 bellard
    /* some cases can be optimized here */
521 c896fe29 bellard
    if (arg2 == 0) {
522 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
523 c896fe29 bellard
    } else {
524 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
525 e8996ee0 bellard
        tcg_gen_xor_i32(ret, arg1, t0);
526 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
527 c896fe29 bellard
    }
528 c896fe29 bellard
}
529 c896fe29 bellard
530 a7812ae4 pbrook
static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
531 c896fe29 bellard
{
532 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
533 c896fe29 bellard
}
534 c896fe29 bellard
535 a7812ae4 pbrook
static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
536 c896fe29 bellard
{
537 34151a20 bellard
    if (arg2 == 0) {
538 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
539 34151a20 bellard
    } else {
540 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
541 e8996ee0 bellard
        tcg_gen_shl_i32(ret, arg1, t0);
542 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
543 34151a20 bellard
    }
544 c896fe29 bellard
}
545 c896fe29 bellard
546 a7812ae4 pbrook
static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
547 c896fe29 bellard
{
548 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
549 c896fe29 bellard
}
550 c896fe29 bellard
551 a7812ae4 pbrook
static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
552 c896fe29 bellard
{
553 34151a20 bellard
    if (arg2 == 0) {
554 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
555 34151a20 bellard
    } else {
556 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
557 e8996ee0 bellard
        tcg_gen_shr_i32(ret, arg1, t0);
558 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
559 34151a20 bellard
    }
560 c896fe29 bellard
}
561 c896fe29 bellard
562 a7812ae4 pbrook
static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
563 c896fe29 bellard
{
564 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
565 c896fe29 bellard
}
566 c896fe29 bellard
567 a7812ae4 pbrook
static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
568 c896fe29 bellard
{
569 34151a20 bellard
    if (arg2 == 0) {
570 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
571 34151a20 bellard
    } else {
572 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
573 e8996ee0 bellard
        tcg_gen_sar_i32(ret, arg1, t0);
574 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
575 34151a20 bellard
    }
576 c896fe29 bellard
}
577 c896fe29 bellard
578 a7812ae4 pbrook
static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2,
579 c896fe29 bellard
                                      int label_index)
580 c896fe29 bellard
{
581 a7812ae4 pbrook
    tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
582 c896fe29 bellard
}
583 c896fe29 bellard
584 a7812ae4 pbrook
static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2,
585 cb63669a pbrook
                                       int label_index)
586 cb63669a pbrook
{
587 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
588 cb63669a pbrook
    tcg_gen_brcond_i32(cond, arg1, t0, label_index);
589 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
590 cb63669a pbrook
}
591 cb63669a pbrook
592 a7812ae4 pbrook
static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
593 c896fe29 bellard
{
594 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
595 c896fe29 bellard
}
596 c896fe29 bellard
597 a7812ae4 pbrook
static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
598 f730fd27 ths
{
599 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
600 e8996ee0 bellard
    tcg_gen_mul_i32(ret, arg1, t0);
601 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
602 f730fd27 ths
}
603 f730fd27 ths
604 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i32
605 a7812ae4 pbrook
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
606 c896fe29 bellard
{
607 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
608 c896fe29 bellard
}
609 c896fe29 bellard
610 a7812ae4 pbrook
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
611 c896fe29 bellard
{
612 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
613 c896fe29 bellard
}
614 c896fe29 bellard
615 a7812ae4 pbrook
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
616 c896fe29 bellard
{
617 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
618 c896fe29 bellard
}
619 c896fe29 bellard
620 a7812ae4 pbrook
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
621 c896fe29 bellard
{
622 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
623 c896fe29 bellard
}
624 c896fe29 bellard
#else
625 a7812ae4 pbrook
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
626 c896fe29 bellard
{
627 a7812ae4 pbrook
    TCGv_i32 t0;
628 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
629 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
630 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
631 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
632 c896fe29 bellard
}
633 c896fe29 bellard
634 a7812ae4 pbrook
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
635 c896fe29 bellard
{
636 a7812ae4 pbrook
    TCGv_i32 t0;
637 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
638 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
639 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
640 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
641 c896fe29 bellard
}
642 c896fe29 bellard
643 a7812ae4 pbrook
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
644 c896fe29 bellard
{
645 a7812ae4 pbrook
    TCGv_i32 t0;
646 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
647 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
648 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
649 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
650 c896fe29 bellard
}
651 c896fe29 bellard
652 a7812ae4 pbrook
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
653 c896fe29 bellard
{
654 a7812ae4 pbrook
    TCGv_i32 t0;
655 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
656 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
657 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
658 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
659 c896fe29 bellard
}
660 c896fe29 bellard
#endif
661 c896fe29 bellard
662 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
663 c896fe29 bellard
664 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
665 c896fe29 bellard
{
666 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I64(ret, arg)) {
667 a7812ae4 pbrook
        tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
668 4d07272d blueswir1
        tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
669 4d07272d blueswir1
    }
670 c896fe29 bellard
}
671 c896fe29 bellard
672 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
673 c896fe29 bellard
{
674 a7812ae4 pbrook
    tcg_gen_movi_i32(TCGV_LOW(ret), arg);
675 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
676 c896fe29 bellard
}
677 c896fe29 bellard
678 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
679 a7812ae4 pbrook
                                    tcg_target_long offset)
680 c896fe29 bellard
{
681 a7812ae4 pbrook
    tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
682 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
683 c896fe29 bellard
}
684 c896fe29 bellard
685 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
686 a7812ae4 pbrook
                                    tcg_target_long offset)
687 c896fe29 bellard
{
688 a7812ae4 pbrook
    tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
689 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
690 c896fe29 bellard
}
691 c896fe29 bellard
692 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
693 a7812ae4 pbrook
                                     tcg_target_long offset)
694 c896fe29 bellard
{
695 a747723b aurel32
    tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
696 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
697 c896fe29 bellard
}
698 c896fe29 bellard
699 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
700 a7812ae4 pbrook
                                     tcg_target_long offset)
701 c896fe29 bellard
{
702 a7812ae4 pbrook
    tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
703 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
704 c896fe29 bellard
}
705 c896fe29 bellard
706 a7812ae4 pbrook
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
707 a7812ae4 pbrook
                                     tcg_target_long offset)
708 c896fe29 bellard
{
709 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
710 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
711 c896fe29 bellard
}
712 c896fe29 bellard
713 a7812ae4 pbrook
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
714 a7812ae4 pbrook
                                     tcg_target_long offset)
715 c896fe29 bellard
{
716 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
717 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
718 c896fe29 bellard
}
719 c896fe29 bellard
720 a7812ae4 pbrook
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
721 a7812ae4 pbrook
                                  tcg_target_long offset)
722 c896fe29 bellard
{
723 c896fe29 bellard
    /* since arg2 and ret have different types, they cannot be the
724 c896fe29 bellard
       same temporary */
725 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
726 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
727 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
728 c896fe29 bellard
#else
729 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
730 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
731 c896fe29 bellard
#endif
732 c896fe29 bellard
}
733 c896fe29 bellard
734 a7812ae4 pbrook
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
735 a7812ae4 pbrook
                                   tcg_target_long offset)
736 c896fe29 bellard
{
737 a7812ae4 pbrook
    tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
738 c896fe29 bellard
}
739 c896fe29 bellard
740 a7812ae4 pbrook
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
741 a7812ae4 pbrook
                                    tcg_target_long offset)
742 c896fe29 bellard
{
743 a7812ae4 pbrook
    tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
744 c896fe29 bellard
}
745 c896fe29 bellard
746 a7812ae4 pbrook
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
747 a7812ae4 pbrook
                                    tcg_target_long offset)
748 c896fe29 bellard
{
749 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
750 c896fe29 bellard
}
751 c896fe29 bellard
752 a7812ae4 pbrook
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
753 a7812ae4 pbrook
                                  tcg_target_long offset)
754 c896fe29 bellard
{
755 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
756 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
757 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
758 c896fe29 bellard
#else
759 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
760 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
761 c896fe29 bellard
#endif
762 c896fe29 bellard
}
763 c896fe29 bellard
764 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
765 c896fe29 bellard
{
766 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
767 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
768 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
769 c896fe29 bellard
}
770 c896fe29 bellard
771 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
772 c896fe29 bellard
{
773 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
774 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
775 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
776 c896fe29 bellard
}
777 c896fe29 bellard
778 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
779 c896fe29 bellard
{
780 a7812ae4 pbrook
    tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
781 ac56dd48 pbrook
    tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
782 c896fe29 bellard
}
783 c896fe29 bellard
784 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
785 c896fe29 bellard
{
786 e5105083 aurel32
    tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
787 e5105083 aurel32
    tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
788 c896fe29 bellard
}
789 c896fe29 bellard
790 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
791 c896fe29 bellard
{
792 e5105083 aurel32
    tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
793 e5105083 aurel32
    tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
794 c896fe29 bellard
}
795 c896fe29 bellard
796 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
797 c896fe29 bellard
{
798 a7812ae4 pbrook
    tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
799 ac56dd48 pbrook
    tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
800 c896fe29 bellard
}
801 c896fe29 bellard
802 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
803 c896fe29 bellard
{
804 e5105083 aurel32
    tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
805 e5105083 aurel32
    tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
806 c896fe29 bellard
}
807 c896fe29 bellard
808 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
809 c896fe29 bellard
{
810 a7812ae4 pbrook
    tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
811 ac56dd48 pbrook
    tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
812 c896fe29 bellard
}
813 c896fe29 bellard
814 c896fe29 bellard
/* XXX: use generic code when basic block handling is OK or CPU
815 c896fe29 bellard
   specific code (x86) */
816 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
817 c896fe29 bellard
{
818 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2);
819 c896fe29 bellard
}
820 c896fe29 bellard
821 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
822 c896fe29 bellard
{
823 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
824 c896fe29 bellard
}
825 c896fe29 bellard
826 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
827 c896fe29 bellard
{
828 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2);
829 c896fe29 bellard
}
830 c896fe29 bellard
831 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
832 c896fe29 bellard
{
833 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
834 c896fe29 bellard
}
835 c896fe29 bellard
836 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
837 c896fe29 bellard
{
838 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2);
839 c896fe29 bellard
}
840 c896fe29 bellard
841 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
842 c896fe29 bellard
{
843 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
844 c896fe29 bellard
}
845 c896fe29 bellard
846 a7812ae4 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
847 c896fe29 bellard
                                      int label_index)
848 c896fe29 bellard
{
849 a7812ae4 pbrook
    tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
850 a7812ae4 pbrook
                      TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
851 a7812ae4 pbrook
                      TCGV_HIGH(arg2), cond, label_index);
852 c896fe29 bellard
}
853 c896fe29 bellard
854 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
855 c896fe29 bellard
{
856 a7812ae4 pbrook
    TCGv_i64 t0;
857 a7812ae4 pbrook
    TCGv_i32 t1;
858 c896fe29 bellard
859 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
860 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
861 a7812ae4 pbrook
862 a7812ae4 pbrook
    tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
863 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_LOW(arg2));
864 a7812ae4 pbrook
865 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
866 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
867 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
868 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
869 a7812ae4 pbrook
870 c896fe29 bellard
    tcg_gen_mov_i64(ret, t0);
871 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
872 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
873 c896fe29 bellard
}
874 c896fe29 bellard
875 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
876 c896fe29 bellard
{
877 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2);
878 c896fe29 bellard
}
879 c896fe29 bellard
880 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
881 c896fe29 bellard
{
882 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2);
883 c896fe29 bellard
}
884 c896fe29 bellard
885 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
886 c896fe29 bellard
{
887 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2);
888 c896fe29 bellard
}
889 c896fe29 bellard
890 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
891 c896fe29 bellard
{
892 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2);
893 c896fe29 bellard
}
894 c896fe29 bellard
895 c896fe29 bellard
#else
896 c896fe29 bellard
897 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
898 c896fe29 bellard
{
899 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I64(ret, arg))
900 a7812ae4 pbrook
        tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
901 c896fe29 bellard
}
902 c896fe29 bellard
903 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
904 c896fe29 bellard
{
905 a7812ae4 pbrook
    tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
906 c896fe29 bellard
}
907 c896fe29 bellard
908 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2,
909 ac56dd48 pbrook
                                    tcg_target_long offset)
910 c896fe29 bellard
{
911 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
912 c896fe29 bellard
}
913 c896fe29 bellard
914 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2,
915 ac56dd48 pbrook
                                    tcg_target_long offset)
916 c896fe29 bellard
{
917 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
918 c896fe29 bellard
}
919 c896fe29 bellard
920 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2,
921 ac56dd48 pbrook
                                     tcg_target_long offset)
922 c896fe29 bellard
{
923 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
924 c896fe29 bellard
}
925 c896fe29 bellard
926 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2,
927 ac56dd48 pbrook
                                     tcg_target_long offset)
928 c896fe29 bellard
{
929 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
930 c896fe29 bellard
}
931 c896fe29 bellard
932 a7812ae4 pbrook
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2,
933 ac56dd48 pbrook
                                     tcg_target_long offset)
934 c896fe29 bellard
{
935 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
936 c896fe29 bellard
}
937 c896fe29 bellard
938 a7812ae4 pbrook
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2,
939 ac56dd48 pbrook
                                     tcg_target_long offset)
940 c896fe29 bellard
{
941 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
942 c896fe29 bellard
}
943 c896fe29 bellard
944 a7812ae4 pbrook
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset)
945 c896fe29 bellard
{
946 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
947 c896fe29 bellard
}
948 c896fe29 bellard
949 a7812ae4 pbrook
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2,
950 ac56dd48 pbrook
                                   tcg_target_long offset)
951 c896fe29 bellard
{
952 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
953 c896fe29 bellard
}
954 c896fe29 bellard
955 a7812ae4 pbrook
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2,
956 ac56dd48 pbrook
                                    tcg_target_long offset)
957 c896fe29 bellard
{
958 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
959 c896fe29 bellard
}
960 c896fe29 bellard
961 a7812ae4 pbrook
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2,
962 ac56dd48 pbrook
                                    tcg_target_long offset)
963 c896fe29 bellard
{
964 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
965 c896fe29 bellard
}
966 c896fe29 bellard
967 a7812ae4 pbrook
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset)
968 c896fe29 bellard
{
969 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
970 c896fe29 bellard
}
971 c896fe29 bellard
972 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
973 c896fe29 bellard
{
974 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
975 c896fe29 bellard
}
976 c896fe29 bellard
977 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
978 c896fe29 bellard
{
979 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
980 c896fe29 bellard
}
981 c896fe29 bellard
982 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
983 c896fe29 bellard
{
984 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
985 7fc81051 aurel32
        tcg_gen_mov_i64(ret, arg1);
986 7fc81051 aurel32
    } else {
987 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
988 7fc81051 aurel32
    }
989 c896fe29 bellard
}
990 c896fe29 bellard
991 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
992 c896fe29 bellard
{
993 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
994 e8996ee0 bellard
    tcg_gen_and_i64(ret, arg1, t0);
995 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
996 c896fe29 bellard
}
997 c896fe29 bellard
998 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
999 c896fe29 bellard
{
1000 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
1001 7fc81051 aurel32
        tcg_gen_mov_i64(ret, arg1);
1002 7fc81051 aurel32
    } else {
1003 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
1004 7fc81051 aurel32
    }
1005 c896fe29 bellard
}
1006 c896fe29 bellard
1007 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1008 c896fe29 bellard
{
1009 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1010 e8996ee0 bellard
    tcg_gen_or_i64(ret, arg1, t0);
1011 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1012 c896fe29 bellard
}
1013 c896fe29 bellard
1014 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1015 c896fe29 bellard
{
1016 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
1017 7fc81051 aurel32
        tcg_gen_movi_i64(ret, 0);
1018 7fc81051 aurel32
    } else {
1019 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
1020 7fc81051 aurel32
    }
1021 c896fe29 bellard
}
1022 c896fe29 bellard
1023 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1024 c896fe29 bellard
{
1025 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1026 e8996ee0 bellard
    tcg_gen_xor_i64(ret, arg1, t0);
1027 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1028 c896fe29 bellard
}
1029 c896fe29 bellard
1030 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1031 c896fe29 bellard
{
1032 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
1033 c896fe29 bellard
}
1034 c896fe29 bellard
1035 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1036 c896fe29 bellard
{
1037 34151a20 bellard
    if (arg2 == 0) {
1038 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1039 34151a20 bellard
    } else {
1040 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1041 e8996ee0 bellard
        tcg_gen_shl_i64(ret, arg1, t0);
1042 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1043 34151a20 bellard
    }
1044 c896fe29 bellard
}
1045 c896fe29 bellard
1046 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1047 c896fe29 bellard
{
1048 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1049 c896fe29 bellard
}
1050 c896fe29 bellard
1051 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1052 c896fe29 bellard
{
1053 34151a20 bellard
    if (arg2 == 0) {
1054 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1055 34151a20 bellard
    } else {
1056 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1057 e8996ee0 bellard
        tcg_gen_shr_i64(ret, arg1, t0);
1058 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1059 34151a20 bellard
    }
1060 c896fe29 bellard
}
1061 c896fe29 bellard
1062 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1063 c896fe29 bellard
{
1064 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1065 c896fe29 bellard
}
1066 c896fe29 bellard
1067 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1068 c896fe29 bellard
{
1069 34151a20 bellard
    if (arg2 == 0) {
1070 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1071 34151a20 bellard
    } else {
1072 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1073 e8996ee0 bellard
        tcg_gen_sar_i64(ret, arg1, t0);
1074 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1075 34151a20 bellard
    }
1076 c896fe29 bellard
}
1077 c896fe29 bellard
1078 a7812ae4 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
1079 c896fe29 bellard
                                      int label_index)
1080 c896fe29 bellard
{
1081 a7812ae4 pbrook
    tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1082 c896fe29 bellard
}
1083 c896fe29 bellard
1084 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1085 c896fe29 bellard
{
1086 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1087 c896fe29 bellard
}
1088 c896fe29 bellard
1089 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i64
1090 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1091 c896fe29 bellard
{
1092 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1093 c896fe29 bellard
}
1094 c896fe29 bellard
1095 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1096 c896fe29 bellard
{
1097 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1098 c896fe29 bellard
}
1099 c896fe29 bellard
1100 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1101 c896fe29 bellard
{
1102 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1103 c896fe29 bellard
}
1104 c896fe29 bellard
1105 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1106 c896fe29 bellard
{
1107 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1108 c896fe29 bellard
}
1109 c896fe29 bellard
#else
1110 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1111 c896fe29 bellard
{
1112 a7812ae4 pbrook
    TCGv_i64 t0;
1113 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1114 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1115 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1116 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1117 c896fe29 bellard
}
1118 c896fe29 bellard
1119 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1120 c896fe29 bellard
{
1121 a7812ae4 pbrook
    TCGv_i64 t0;
1122 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1123 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1124 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1125 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1126 c896fe29 bellard
}
1127 c896fe29 bellard
1128 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1129 c896fe29 bellard
{
1130 a7812ae4 pbrook
    TCGv_i64 t0;
1131 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1132 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1133 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1134 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1135 c896fe29 bellard
}
1136 c896fe29 bellard
1137 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1138 c896fe29 bellard
{
1139 a7812ae4 pbrook
    TCGv_i64 t0;
1140 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1141 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1142 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1143 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1144 c896fe29 bellard
}
1145 c896fe29 bellard
#endif
1146 c896fe29 bellard
1147 c896fe29 bellard
#endif
1148 c896fe29 bellard
1149 a7812ae4 pbrook
static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1150 6359706f aurel32
{
1151 6359706f aurel32
    /* some cases can be optimized here */
1152 6359706f aurel32
    if (arg2 == 0) {
1153 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1154 6359706f aurel32
    } else {
1155 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1156 6359706f aurel32
        tcg_gen_add_i64(ret, arg1, t0);
1157 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1158 6359706f aurel32
    }
1159 6359706f aurel32
}
1160 6359706f aurel32
1161 a7812ae4 pbrook
static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1162 0045734a aurel32
{
1163 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg1);
1164 0045734a aurel32
    tcg_gen_sub_i64(ret, t0, arg2);
1165 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1166 0045734a aurel32
}
1167 0045734a aurel32
1168 a7812ae4 pbrook
static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1169 6359706f aurel32
{
1170 6359706f aurel32
    /* some cases can be optimized here */
1171 6359706f aurel32
    if (arg2 == 0) {
1172 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1173 6359706f aurel32
    } else {
1174 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1175 6359706f aurel32
        tcg_gen_sub_i64(ret, arg1, t0);
1176 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1177 6359706f aurel32
    }
1178 6359706f aurel32
}
1179 a7812ae4 pbrook
static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2,
1180 f02bb954 aurel32
                                       int label_index)
1181 f02bb954 aurel32
{
1182 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1183 f02bb954 aurel32
    tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1184 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1185 f02bb954 aurel32
}
1186 f02bb954 aurel32
1187 a7812ae4 pbrook
static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1188 f02bb954 aurel32
{
1189 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1190 f02bb954 aurel32
    tcg_gen_mul_i64(ret, arg1, t0);
1191 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1192 f02bb954 aurel32
}
1193 f02bb954 aurel32
1194 6359706f aurel32
1195 c896fe29 bellard
/***************************************/
1196 c896fe29 bellard
/* optional operations */
1197 c896fe29 bellard
1198 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1199 c896fe29 bellard
{
1200 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i32
1201 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1202 c896fe29 bellard
#else
1203 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 24);
1204 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 24);
1205 c896fe29 bellard
#endif
1206 c896fe29 bellard
}
1207 c896fe29 bellard
1208 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1209 c896fe29 bellard
{
1210 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i32
1211 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1212 c896fe29 bellard
#else
1213 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 16);
1214 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 16);
1215 c896fe29 bellard
#endif
1216 c896fe29 bellard
}
1217 c896fe29 bellard
1218 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1219 86831435 pbrook
{
1220 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext8u_i32
1221 cfc86988 Aurelien Jarno
    tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1222 cfc86988 Aurelien Jarno
#else
1223 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffu);
1224 cfc86988 Aurelien Jarno
#endif
1225 86831435 pbrook
}
1226 86831435 pbrook
1227 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1228 86831435 pbrook
{
1229 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext16u_i32
1230 cfc86988 Aurelien Jarno
    tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1231 cfc86988 Aurelien Jarno
#else
1232 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffffu);
1233 cfc86988 Aurelien Jarno
#endif
1234 86831435 pbrook
}
1235 86831435 pbrook
1236 c896fe29 bellard
/* Note: we assume the two high bytes are set to zero */
1237 a7812ae4 pbrook
static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1238 c896fe29 bellard
{
1239 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap16_i32
1240 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1241 c896fe29 bellard
#else
1242 dfa1a3f1 aurel32
    TCGv_i32 t0 = tcg_temp_new_i32();
1243 c896fe29 bellard
    
1244 dfa1a3f1 aurel32
    tcg_gen_ext8u_i32(t0, arg);
1245 dfa1a3f1 aurel32
    tcg_gen_shli_i32(t0, t0, 8);
1246 dfa1a3f1 aurel32
    tcg_gen_shri_i32(ret, arg, 8);
1247 dfa1a3f1 aurel32
    tcg_gen_or_i32(ret, ret, t0);
1248 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1249 c896fe29 bellard
#endif
1250 c896fe29 bellard
}
1251 c896fe29 bellard
1252 66896cb8 aurel32
static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1253 c896fe29 bellard
{
1254 66896cb8 aurel32
#ifdef TCG_TARGET_HAS_bswap32_i32
1255 66896cb8 aurel32
    tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1256 c896fe29 bellard
#else
1257 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1258 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1259 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1260 c896fe29 bellard
    
1261 c896fe29 bellard
    tcg_gen_shli_i32(t0, arg, 24);
1262 c896fe29 bellard
    
1263 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1264 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
1265 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1266 c896fe29 bellard
    
1267 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 8);
1268 c896fe29 bellard
    tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1269 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1270 c896fe29 bellard
    
1271 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 24);
1272 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
1273 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1274 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1275 c896fe29 bellard
#endif
1276 c896fe29 bellard
}
1277 c896fe29 bellard
1278 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1279 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1280 c896fe29 bellard
{
1281 a7812ae4 pbrook
    tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1282 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1283 c896fe29 bellard
}
1284 c896fe29 bellard
1285 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1286 c896fe29 bellard
{
1287 a7812ae4 pbrook
    tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1288 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1289 c896fe29 bellard
}
1290 c896fe29 bellard
1291 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1292 c896fe29 bellard
{
1293 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1294 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1295 c896fe29 bellard
}
1296 c896fe29 bellard
1297 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1298 86831435 pbrook
{
1299 a7812ae4 pbrook
    tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1300 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1301 86831435 pbrook
}
1302 86831435 pbrook
1303 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1304 86831435 pbrook
{
1305 a7812ae4 pbrook
    tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1306 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1307 86831435 pbrook
}
1308 86831435 pbrook
1309 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1310 86831435 pbrook
{
1311 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1312 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1313 86831435 pbrook
}
1314 86831435 pbrook
1315 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1316 c896fe29 bellard
{
1317 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1318 c896fe29 bellard
}
1319 c896fe29 bellard
1320 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1321 c896fe29 bellard
{
1322 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1323 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1324 c896fe29 bellard
}
1325 c896fe29 bellard
1326 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1327 c896fe29 bellard
{
1328 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1329 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1330 c896fe29 bellard
}
1331 c896fe29 bellard
1332 9a5c57fd aurel32
/* Note: we assume the six high bytes are set to zero */
1333 9a5c57fd aurel32
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1334 9a5c57fd aurel32
{
1335 9a5c57fd aurel32
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1336 9a5c57fd aurel32
    tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1337 9a5c57fd aurel32
}
1338 9a5c57fd aurel32
1339 9a5c57fd aurel32
/* Note: we assume the four high bytes are set to zero */
1340 9a5c57fd aurel32
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1341 9a5c57fd aurel32
{
1342 9a5c57fd aurel32
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1343 9a5c57fd aurel32
    tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1344 9a5c57fd aurel32
}
1345 9a5c57fd aurel32
1346 66896cb8 aurel32
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1347 c896fe29 bellard
{
1348 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1349 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1350 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1351 c896fe29 bellard
1352 66896cb8 aurel32
    tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1353 66896cb8 aurel32
    tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1354 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1355 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1356 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1357 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1358 c896fe29 bellard
}
1359 c896fe29 bellard
#else
1360 c896fe29 bellard
1361 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1362 c896fe29 bellard
{
1363 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i64
1364 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1365 c896fe29 bellard
#else
1366 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 56);
1367 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 56);
1368 c896fe29 bellard
#endif
1369 c896fe29 bellard
}
1370 c896fe29 bellard
1371 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1372 c896fe29 bellard
{
1373 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i64
1374 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1375 c896fe29 bellard
#else
1376 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 48);
1377 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 48);
1378 c896fe29 bellard
#endif
1379 c896fe29 bellard
}
1380 c896fe29 bellard
1381 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1382 c896fe29 bellard
{
1383 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext32s_i64
1384 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1385 c896fe29 bellard
#else
1386 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 32);
1387 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 32);
1388 c896fe29 bellard
#endif
1389 c896fe29 bellard
}
1390 c896fe29 bellard
1391 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1392 86831435 pbrook
{
1393 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext8u_i64
1394 cfc86988 Aurelien Jarno
    tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1395 cfc86988 Aurelien Jarno
#else
1396 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffu);
1397 cfc86988 Aurelien Jarno
#endif
1398 86831435 pbrook
}
1399 86831435 pbrook
1400 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1401 86831435 pbrook
{
1402 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext16u_i64
1403 cfc86988 Aurelien Jarno
    tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1404 cfc86988 Aurelien Jarno
#else
1405 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffu);
1406 cfc86988 Aurelien Jarno
#endif
1407 86831435 pbrook
}
1408 86831435 pbrook
1409 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1410 86831435 pbrook
{
1411 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext32u_i64
1412 cfc86988 Aurelien Jarno
    tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1413 cfc86988 Aurelien Jarno
#else
1414 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1415 cfc86988 Aurelien Jarno
#endif
1416 86831435 pbrook
}
1417 86831435 pbrook
1418 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1419 ac56dd48 pbrook
   registers.  This will probably break MIPS64 targets.  */
1420 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1421 c896fe29 bellard
{
1422 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1423 c896fe29 bellard
}
1424 c896fe29 bellard
1425 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1426 c896fe29 bellard
   registers */
1427 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1428 c896fe29 bellard
{
1429 cfc86988 Aurelien Jarno
    tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1430 c896fe29 bellard
}
1431 c896fe29 bellard
1432 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1433 c896fe29 bellard
   registers */
1434 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1435 c896fe29 bellard
{
1436 a7812ae4 pbrook
    tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1437 c896fe29 bellard
}
1438 c896fe29 bellard
1439 9a5c57fd aurel32
/* Note: we assume the six high bytes are set to zero */
1440 9a5c57fd aurel32
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1441 9a5c57fd aurel32
{
1442 9a5c57fd aurel32
#ifdef TCG_TARGET_HAS_bswap16_i64
1443 9a5c57fd aurel32
    tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1444 9a5c57fd aurel32
#else
1445 9a5c57fd aurel32
    TCGv_i64 t0 = tcg_temp_new_i64();
1446 9a5c57fd aurel32
1447 9a5c57fd aurel32
    tcg_gen_ext8u_i64(t0, arg);
1448 9a5c57fd aurel32
    tcg_gen_shli_i64(t0, t0, 8);
1449 9a5c57fd aurel32
    tcg_gen_shri_i64(ret, arg, 8);
1450 9a5c57fd aurel32
    tcg_gen_or_i64(ret, ret, t0);
1451 9a5c57fd aurel32
    tcg_temp_free_i64(t0);
1452 9a5c57fd aurel32
#endif
1453 9a5c57fd aurel32
}
1454 9a5c57fd aurel32
1455 9a5c57fd aurel32
/* Note: we assume the four high bytes are set to zero */
1456 9a5c57fd aurel32
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1457 9a5c57fd aurel32
{
1458 9a5c57fd aurel32
#ifdef TCG_TARGET_HAS_bswap32_i64
1459 9a5c57fd aurel32
    tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1460 9a5c57fd aurel32
#else
1461 9a5c57fd aurel32
    TCGv_i64 t0, t1;
1462 9a5c57fd aurel32
    t0 = tcg_temp_new_i64();
1463 9a5c57fd aurel32
    t1 = tcg_temp_new_i64();
1464 9a5c57fd aurel32
1465 9a5c57fd aurel32
    tcg_gen_shli_i64(t0, arg, 24);
1466 9a5c57fd aurel32
    tcg_gen_ext32u_i64(t0, t0);
1467 9a5c57fd aurel32
1468 9a5c57fd aurel32
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1469 9a5c57fd aurel32
    tcg_gen_shli_i64(t1, t1, 8);
1470 9a5c57fd aurel32
    tcg_gen_or_i64(t0, t0, t1);
1471 9a5c57fd aurel32
1472 9a5c57fd aurel32
    tcg_gen_shri_i64(t1, arg, 8);
1473 9a5c57fd aurel32
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1474 9a5c57fd aurel32
    tcg_gen_or_i64(t0, t0, t1);
1475 9a5c57fd aurel32
1476 9a5c57fd aurel32
    tcg_gen_shri_i64(t1, arg, 24);
1477 9a5c57fd aurel32
    tcg_gen_or_i64(ret, t0, t1);
1478 9a5c57fd aurel32
    tcg_temp_free_i64(t0);
1479 9a5c57fd aurel32
    tcg_temp_free_i64(t1);
1480 9a5c57fd aurel32
#endif
1481 9a5c57fd aurel32
}
1482 9a5c57fd aurel32
1483 66896cb8 aurel32
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1484 c896fe29 bellard
{
1485 66896cb8 aurel32
#ifdef TCG_TARGET_HAS_bswap64_i64
1486 66896cb8 aurel32
    tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1487 c896fe29 bellard
#else
1488 b348113d Stefan Weil
    TCGv_i64 t0 = tcg_temp_new_i64();
1489 b348113d Stefan Weil
    TCGv_i64 t1 = tcg_temp_new_i64();
1490 c896fe29 bellard
    
1491 c896fe29 bellard
    tcg_gen_shli_i64(t0, arg, 56);
1492 c896fe29 bellard
    
1493 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1494 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 40);
1495 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1496 c896fe29 bellard
    
1497 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1498 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 24);
1499 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1500 c896fe29 bellard
1501 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0xff000000);
1502 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 8);
1503 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1504 c896fe29 bellard
1505 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 8);
1506 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0xff000000);
1507 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1508 c896fe29 bellard
    
1509 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 24);
1510 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1511 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1512 c896fe29 bellard
1513 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 40);
1514 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1515 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1516 c896fe29 bellard
1517 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 56);
1518 c896fe29 bellard
    tcg_gen_or_i64(ret, t0, t1);
1519 b348113d Stefan Weil
    tcg_temp_free_i64(t0);
1520 b348113d Stefan Weil
    tcg_temp_free_i64(t1);
1521 c896fe29 bellard
#endif
1522 c896fe29 bellard
}
1523 c896fe29 bellard
1524 c896fe29 bellard
#endif
1525 c896fe29 bellard
1526 a7812ae4 pbrook
static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1527 390efc54 pbrook
{
1528 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i32
1529 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1530 390efc54 pbrook
#else
1531 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(0);
1532 e8996ee0 bellard
    tcg_gen_sub_i32(ret, t0, arg);
1533 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1534 390efc54 pbrook
#endif
1535 390efc54 pbrook
}
1536 390efc54 pbrook
1537 a7812ae4 pbrook
static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1538 390efc54 pbrook
{
1539 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i64
1540 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1541 390efc54 pbrook
#else
1542 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(0);
1543 e8996ee0 bellard
    tcg_gen_sub_i64(ret, t0, arg);
1544 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1545 390efc54 pbrook
#endif
1546 390efc54 pbrook
}
1547 390efc54 pbrook
1548 a7812ae4 pbrook
static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1549 0b6ce4cf bellard
{
1550 d2604285 aurel32
#ifdef TCG_TARGET_HAS_not_i32
1551 d2604285 aurel32
    tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1552 d2604285 aurel32
#else
1553 e8996ee0 bellard
    tcg_gen_xori_i32(ret, arg, -1);
1554 d2604285 aurel32
#endif
1555 0b6ce4cf bellard
}
1556 0b6ce4cf bellard
1557 a7812ae4 pbrook
static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1558 0b6ce4cf bellard
{
1559 d2604285 aurel32
#ifdef TCG_TARGET_HAS_not_i64
1560 43e860ef aurel32
    tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1561 d2604285 aurel32
#else
1562 e8996ee0 bellard
    tcg_gen_xori_i64(ret, arg, -1);
1563 d2604285 aurel32
#endif
1564 0b6ce4cf bellard
}
1565 5ff9d6a4 bellard
1566 a7812ae4 pbrook
static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1567 5ff9d6a4 bellard
{
1568 a7812ae4 pbrook
    tcg_gen_op1_i32(INDEX_op_discard, arg);
1569 5ff9d6a4 bellard
}
1570 5ff9d6a4 bellard
1571 5ff9d6a4 bellard
#if TCG_TARGET_REG_BITS == 32
1572 a7812ae4 pbrook
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1573 5ff9d6a4 bellard
{
1574 a7812ae4 pbrook
    tcg_gen_discard_i32(TCGV_LOW(arg));
1575 5ff9d6a4 bellard
    tcg_gen_discard_i32(TCGV_HIGH(arg));
1576 5ff9d6a4 bellard
}
1577 5ff9d6a4 bellard
#else
1578 a7812ae4 pbrook
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1579 5ff9d6a4 bellard
{
1580 a7812ae4 pbrook
    tcg_gen_op1_i64(INDEX_op_discard, arg);
1581 5ff9d6a4 bellard
}
1582 5ff9d6a4 bellard
#endif
1583 5ff9d6a4 bellard
1584 a7812ae4 pbrook
static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
1585 36aa55dc pbrook
{
1586 36aa55dc pbrook
#if TCG_TARGET_REG_BITS == 32
1587 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(dest), low);
1588 36aa55dc pbrook
    tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1589 36aa55dc pbrook
#else
1590 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1591 36aa55dc pbrook
    /* This extension is only needed for type correctness.
1592 36aa55dc pbrook
       We may be able to do better given target specific information.  */
1593 36aa55dc pbrook
    tcg_gen_extu_i32_i64(tmp, high);
1594 36aa55dc pbrook
    tcg_gen_shli_i64(tmp, tmp, 32);
1595 36aa55dc pbrook
    tcg_gen_extu_i32_i64(dest, low);
1596 36aa55dc pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1597 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1598 36aa55dc pbrook
#endif
1599 36aa55dc pbrook
}
1600 36aa55dc pbrook
1601 a7812ae4 pbrook
static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
1602 945ca823 blueswir1
{
1603 945ca823 blueswir1
#if TCG_TARGET_REG_BITS == 32
1604 a7812ae4 pbrook
    tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1605 945ca823 blueswir1
#else
1606 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1607 88422e2e pbrook
    tcg_gen_ext32u_i64(dest, low);
1608 945ca823 blueswir1
    tcg_gen_shli_i64(tmp, high, 32);
1609 88422e2e pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1610 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1611 945ca823 blueswir1
#endif
1612 945ca823 blueswir1
}
1613 945ca823 blueswir1
1614 a7812ae4 pbrook
static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1615 f24cb33e aurel32
{
1616 a7812ae4 pbrook
    TCGv_i32 t0;
1617 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1618 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1619 f24cb33e aurel32
    tcg_gen_and_i32(ret, arg1, t0);
1620 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1621 f24cb33e aurel32
}
1622 f24cb33e aurel32
1623 a7812ae4 pbrook
static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1624 f24cb33e aurel32
{
1625 a7812ae4 pbrook
    TCGv_i64 t0;
1626 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1627 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1628 f24cb33e aurel32
    tcg_gen_and_i64(ret, arg1, t0);
1629 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1630 f24cb33e aurel32
}
1631 f24cb33e aurel32
1632 a7812ae4 pbrook
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1633 f24cb33e aurel32
{
1634 7fc81051 aurel32
    tcg_gen_xor_i32(ret, arg1, arg2);
1635 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1636 f24cb33e aurel32
}
1637 f24cb33e aurel32
1638 a7812ae4 pbrook
static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1639 f24cb33e aurel32
{
1640 7fc81051 aurel32
    tcg_gen_xor_i64(ret, arg1, arg2);
1641 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1642 f24cb33e aurel32
}
1643 f24cb33e aurel32
1644 a7812ae4 pbrook
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1645 f24cb33e aurel32
{
1646 7fc81051 aurel32
    tcg_gen_and_i32(ret, arg1, arg2);
1647 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1648 f24cb33e aurel32
}
1649 f24cb33e aurel32
1650 a7812ae4 pbrook
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1651 f24cb33e aurel32
{
1652 7fc81051 aurel32
    tcg_gen_and_i64(ret, arg1, arg2);
1653 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1654 f24cb33e aurel32
}
1655 f24cb33e aurel32
1656 a7812ae4 pbrook
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1657 f24cb33e aurel32
{
1658 7fc81051 aurel32
    tcg_gen_or_i32(ret, arg1, arg2);
1659 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1660 f24cb33e aurel32
}
1661 f24cb33e aurel32
1662 a7812ae4 pbrook
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1663 f24cb33e aurel32
{
1664 7fc81051 aurel32
    tcg_gen_or_i64(ret, arg1, arg2);
1665 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1666 f24cb33e aurel32
}
1667 f24cb33e aurel32
1668 a7812ae4 pbrook
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1669 f24cb33e aurel32
{
1670 a7812ae4 pbrook
    TCGv_i32 t0;
1671 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1672 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1673 f24cb33e aurel32
    tcg_gen_or_i32(ret, arg1, t0);
1674 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1675 f24cb33e aurel32
}
1676 f24cb33e aurel32
1677 a7812ae4 pbrook
static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1678 f24cb33e aurel32
{
1679 a7812ae4 pbrook
    TCGv_i64 t0;
1680 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1681 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1682 f24cb33e aurel32
    tcg_gen_or_i64(ret, arg1, t0);
1683 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1684 f24cb33e aurel32
}
1685 f24cb33e aurel32
1686 a7812ae4 pbrook
static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1687 15824571 aurel32
{
1688 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
1689 d42f183c aurel32
    tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
1690 d42f183c aurel32
#else
1691 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1692 15824571 aurel32
1693 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1694 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1695 15824571 aurel32
    tcg_gen_shl_i32(t0, arg1, arg2);
1696 15824571 aurel32
    tcg_gen_subfi_i32(t1, 32, arg2);
1697 15824571 aurel32
    tcg_gen_shr_i32(t1, arg1, t1);
1698 15824571 aurel32
    tcg_gen_or_i32(ret, t0, t1);
1699 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1700 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1701 d42f183c aurel32
#endif
1702 15824571 aurel32
}
1703 15824571 aurel32
1704 a7812ae4 pbrook
static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1705 15824571 aurel32
{
1706 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
1707 d42f183c aurel32
    tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
1708 d42f183c aurel32
#else
1709 a7812ae4 pbrook
    TCGv_i64 t0, t1;
1710 15824571 aurel32
1711 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1712 a7812ae4 pbrook
    t1 = tcg_temp_new_i64();
1713 15824571 aurel32
    tcg_gen_shl_i64(t0, arg1, arg2);
1714 15824571 aurel32
    tcg_gen_subfi_i64(t1, 64, arg2);
1715 15824571 aurel32
    tcg_gen_shr_i64(t1, arg1, t1);
1716 15824571 aurel32
    tcg_gen_or_i64(ret, t0, t1);
1717 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1718 a7812ae4 pbrook
    tcg_temp_free_i64(t1);
1719 d42f183c aurel32
#endif
1720 15824571 aurel32
}
1721 15824571 aurel32
1722 a7812ae4 pbrook
static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1723 15824571 aurel32
{
1724 15824571 aurel32
    /* some cases can be optimized here */
1725 15824571 aurel32
    if (arg2 == 0) {
1726 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
1727 15824571 aurel32
    } else {
1728 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
1729 d42f183c aurel32
        TCGv_i32 t0 = tcg_const_i32(arg2);
1730 d42f183c aurel32
        tcg_gen_rotl_i32(ret, arg1, t0);
1731 d42f183c aurel32
        tcg_temp_free_i32(t0);
1732 d42f183c aurel32
#else
1733 a7812ae4 pbrook
        TCGv_i32 t0, t1;
1734 a7812ae4 pbrook
        t0 = tcg_temp_new_i32();
1735 a7812ae4 pbrook
        t1 = tcg_temp_new_i32();
1736 15824571 aurel32
        tcg_gen_shli_i32(t0, arg1, arg2);
1737 15824571 aurel32
        tcg_gen_shri_i32(t1, arg1, 32 - arg2);
1738 15824571 aurel32
        tcg_gen_or_i32(ret, t0, t1);
1739 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
1740 a7812ae4 pbrook
        tcg_temp_free_i32(t1);
1741 d42f183c aurel32
#endif
1742 15824571 aurel32
    }
1743 15824571 aurel32
}
1744 15824571 aurel32
1745 a7812ae4 pbrook
static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1746 15824571 aurel32
{
1747 15824571 aurel32
    /* some cases can be optimized here */
1748 15824571 aurel32
    if (arg2 == 0) {
1749 15824571 aurel32
        tcg_gen_mov_i64(ret, arg1);
1750 15824571 aurel32
    } else {
1751 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
1752 d42f183c aurel32
        TCGv_i64 t0 = tcg_const_i64(arg2);
1753 d42f183c aurel32
        tcg_gen_rotl_i64(ret, arg1, t0);
1754 d42f183c aurel32
        tcg_temp_free_i64(t0);
1755 d42f183c aurel32
#else
1756 a7812ae4 pbrook
        TCGv_i64 t0, t1;
1757 a7812ae4 pbrook
        t0 = tcg_temp_new_i64();
1758 a7812ae4 pbrook
        t1 = tcg_temp_new_i64();
1759 15824571 aurel32
        tcg_gen_shli_i64(t0, arg1, arg2);
1760 15824571 aurel32
        tcg_gen_shri_i64(t1, arg1, 64 - arg2);
1761 15824571 aurel32
        tcg_gen_or_i64(ret, t0, t1);
1762 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1763 a7812ae4 pbrook
        tcg_temp_free_i64(t1);
1764 d42f183c aurel32
#endif
1765 15824571 aurel32
    }
1766 15824571 aurel32
}
1767 15824571 aurel32
1768 a7812ae4 pbrook
static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1769 15824571 aurel32
{
1770 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
1771 d42f183c aurel32
    tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
1772 d42f183c aurel32
#else
1773 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1774 15824571 aurel32
1775 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1776 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1777 15824571 aurel32
    tcg_gen_shr_i32(t0, arg1, arg2);
1778 15824571 aurel32
    tcg_gen_subfi_i32(t1, 32, arg2);
1779 15824571 aurel32
    tcg_gen_shl_i32(t1, arg1, t1);
1780 15824571 aurel32
    tcg_gen_or_i32(ret, t0, t1);
1781 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1782 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1783 d42f183c aurel32
#endif
1784 15824571 aurel32
}
1785 15824571 aurel32
1786 a7812ae4 pbrook
static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1787 15824571 aurel32
{
1788 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
1789 d42f183c aurel32
    tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
1790 d42f183c aurel32
#else
1791 a7812ae4 pbrook
    TCGv_i64 t0, t1;
1792 15824571 aurel32
1793 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1794 a7812ae4 pbrook
    t1 = tcg_temp_new_i64();
1795 d9885a0b Aurelien Jarno
    tcg_gen_shr_i64(t0, arg1, arg2);
1796 15824571 aurel32
    tcg_gen_subfi_i64(t1, 64, arg2);
1797 15824571 aurel32
    tcg_gen_shl_i64(t1, arg1, t1);
1798 15824571 aurel32
    tcg_gen_or_i64(ret, t0, t1);
1799 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1800 a7812ae4 pbrook
    tcg_temp_free_i64(t1);
1801 d42f183c aurel32
#endif
1802 15824571 aurel32
}
1803 15824571 aurel32
1804 a7812ae4 pbrook
static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1805 15824571 aurel32
{
1806 15824571 aurel32
    /* some cases can be optimized here */
1807 15824571 aurel32
    if (arg2 == 0) {
1808 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
1809 15824571 aurel32
    } else {
1810 15824571 aurel32
        tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
1811 15824571 aurel32
    }
1812 15824571 aurel32
}
1813 15824571 aurel32
1814 a7812ae4 pbrook
static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1815 15824571 aurel32
{
1816 15824571 aurel32
    /* some cases can be optimized here */
1817 15824571 aurel32
    if (arg2 == 0) {
1818 de3526b2 pbrook
        tcg_gen_mov_i64(ret, arg1);
1819 15824571 aurel32
    } else {
1820 15824571 aurel32
        tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
1821 15824571 aurel32
    }
1822 15824571 aurel32
}
1823 15824571 aurel32
1824 be210acb Richard Henderson
static inline void tcg_gen_setcond_i32(int cond, TCGv_i32 ret,
1825 be210acb Richard Henderson
                                       TCGv_i32 arg1, TCGv_i32 arg2)
1826 be210acb Richard Henderson
{
1827 be210acb Richard Henderson
    tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
1828 be210acb Richard Henderson
}
1829 be210acb Richard Henderson
1830 add1e7ea Aurelien Jarno
static inline void tcg_gen_setcondi_i32(int cond, TCGv_i32 ret, TCGv_i32 arg1,
1831 add1e7ea Aurelien Jarno
                                        int32_t arg2)
1832 add1e7ea Aurelien Jarno
{
1833 add1e7ea Aurelien Jarno
    TCGv_i32 t0 = tcg_const_i32(arg2);
1834 add1e7ea Aurelien Jarno
    tcg_gen_setcond_i32(cond, ret, arg1, t0);
1835 add1e7ea Aurelien Jarno
    tcg_temp_free_i32(t0);
1836 add1e7ea Aurelien Jarno
}
1837 add1e7ea Aurelien Jarno
1838 be210acb Richard Henderson
static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret,
1839 be210acb Richard Henderson
                                       TCGv_i64 arg1, TCGv_i64 arg2)
1840 be210acb Richard Henderson
{
1841 be210acb Richard Henderson
#if TCG_TARGET_REG_BITS == 64
1842 be210acb Richard Henderson
    tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
1843 be210acb Richard Henderson
#else
1844 be210acb Richard Henderson
    tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
1845 be210acb Richard Henderson
                     TCGV_LOW(arg1), TCGV_HIGH(arg1),
1846 be210acb Richard Henderson
                     TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
1847 be210acb Richard Henderson
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1848 be210acb Richard Henderson
#endif
1849 be210acb Richard Henderson
}
1850 be210acb Richard Henderson
1851 add1e7ea Aurelien Jarno
static inline void tcg_gen_setcondi_i64(int cond, TCGv_i64 ret, TCGv_i64 arg1,
1852 add1e7ea Aurelien Jarno
                                        int64_t arg2)
1853 add1e7ea Aurelien Jarno
{
1854 add1e7ea Aurelien Jarno
    TCGv_i64 t0 = tcg_const_i64(arg2);
1855 add1e7ea Aurelien Jarno
    tcg_gen_setcond_i64(cond, ret, arg1, t0);
1856 add1e7ea Aurelien Jarno
    tcg_temp_free_i64(t0);
1857 add1e7ea Aurelien Jarno
}
1858 add1e7ea Aurelien Jarno
1859 c896fe29 bellard
/***************************************/
1860 c896fe29 bellard
/* QEMU specific operations. Their type depend on the QEMU CPU
1861 c896fe29 bellard
   type. */
1862 c896fe29 bellard
#ifndef TARGET_LONG_BITS
1863 c896fe29 bellard
#error must include QEMU headers
1864 c896fe29 bellard
#endif
1865 c896fe29 bellard
1866 a7812ae4 pbrook
#if TARGET_LONG_BITS == 32
1867 a7812ae4 pbrook
#define TCGv TCGv_i32
1868 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i32()
1869 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i32
1870 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i32
1871 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i32()
1872 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i32
1873 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
1874 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
1875 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
1876 fe75bcf7 aurel32
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
1877 a7812ae4 pbrook
#else
1878 a7812ae4 pbrook
#define TCGv TCGv_i64
1879 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i64()
1880 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i64
1881 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i64
1882 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i64()
1883 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i64
1884 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
1885 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
1886 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
1887 fe75bcf7 aurel32
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
1888 a7812ae4 pbrook
#endif
1889 a7812ae4 pbrook
1890 7e4597d7 bellard
/* debug info: write the PC of the corresponding QEMU CPU instruction */
1891 7e4597d7 bellard
static inline void tcg_gen_debug_insn_start(uint64_t pc)
1892 7e4597d7 bellard
{
1893 7e4597d7 bellard
    /* XXX: must really use a 32 bit size for TCGArg in all cases */
1894 7e4597d7 bellard
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1895 bcb0126f pbrook
    tcg_gen_op2ii(INDEX_op_debug_insn_start, 
1896 bcb0126f pbrook
                  (uint32_t)(pc), (uint32_t)(pc >> 32));
1897 7e4597d7 bellard
#else
1898 7e4597d7 bellard
    tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
1899 7e4597d7 bellard
#endif
1900 7e4597d7 bellard
}
1901 7e4597d7 bellard
1902 c896fe29 bellard
static inline void tcg_gen_exit_tb(tcg_target_long val)
1903 c896fe29 bellard
{
1904 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_exit_tb, val);
1905 c896fe29 bellard
}
1906 c896fe29 bellard
1907 c896fe29 bellard
static inline void tcg_gen_goto_tb(int idx)
1908 c896fe29 bellard
{
1909 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_goto_tb, idx);
1910 c896fe29 bellard
}
1911 c896fe29 bellard
1912 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1913 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1914 c896fe29 bellard
{
1915 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1916 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1917 c896fe29 bellard
#else
1918 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
1919 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1920 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1921 c896fe29 bellard
#endif
1922 c896fe29 bellard
}
1923 c896fe29 bellard
1924 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1925 c896fe29 bellard
{
1926 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1927 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1928 c896fe29 bellard
#else
1929 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
1930 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1931 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1932 c896fe29 bellard
#endif
1933 c896fe29 bellard
}
1934 c896fe29 bellard
1935 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1936 c896fe29 bellard
{
1937 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1938 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1939 c896fe29 bellard
#else
1940 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
1941 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1942 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1943 c896fe29 bellard
#endif
1944 c896fe29 bellard
}
1945 c896fe29 bellard
1946 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1947 c896fe29 bellard
{
1948 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1949 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1950 c896fe29 bellard
#else
1951 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
1952 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1953 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1954 c896fe29 bellard
#endif
1955 c896fe29 bellard
}
1956 c896fe29 bellard
1957 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1958 c896fe29 bellard
{
1959 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1960 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1961 c896fe29 bellard
#else
1962 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1963 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1964 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1965 c896fe29 bellard
#endif
1966 c896fe29 bellard
}
1967 c896fe29 bellard
1968 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1969 c896fe29 bellard
{
1970 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1971 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1972 c896fe29 bellard
#else
1973 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1974 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1975 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1976 c896fe29 bellard
#endif
1977 c896fe29 bellard
}
1978 c896fe29 bellard
1979 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
1980 c896fe29 bellard
{
1981 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1982 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
1983 c896fe29 bellard
#else
1984 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
1985 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
1986 c896fe29 bellard
#endif
1987 c896fe29 bellard
}
1988 c896fe29 bellard
1989 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1990 c896fe29 bellard
{
1991 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1992 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
1993 c896fe29 bellard
#else
1994 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
1995 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1996 c896fe29 bellard
#endif
1997 c896fe29 bellard
}
1998 c896fe29 bellard
1999 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2000 c896fe29 bellard
{
2001 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2002 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
2003 c896fe29 bellard
#else
2004 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
2005 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2006 c896fe29 bellard
#endif
2007 c896fe29 bellard
}
2008 c896fe29 bellard
2009 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2010 c896fe29 bellard
{
2011 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2012 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
2013 c896fe29 bellard
#else
2014 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
2015 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2016 c896fe29 bellard
#endif
2017 c896fe29 bellard
}
2018 c896fe29 bellard
2019 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2020 c896fe29 bellard
{
2021 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2022 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
2023 a7812ae4 pbrook
                     mem_index);
2024 c896fe29 bellard
#else
2025 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
2026 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2027 c896fe29 bellard
#endif
2028 c896fe29 bellard
}
2029 c896fe29 bellard
2030 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i32
2031 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i32
2032 f8422f52 blueswir1
2033 c896fe29 bellard
#else /* TCG_TARGET_REG_BITS == 32 */
2034 c896fe29 bellard
2035 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2036 c896fe29 bellard
{
2037 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2038 c896fe29 bellard
}
2039 c896fe29 bellard
2040 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2041 c896fe29 bellard
{
2042 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2043 c896fe29 bellard
}
2044 c896fe29 bellard
2045 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2046 c896fe29 bellard
{
2047 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2048 c896fe29 bellard
}
2049 c896fe29 bellard
2050 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2051 c896fe29 bellard
{
2052 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2053 c896fe29 bellard
}
2054 c896fe29 bellard
2055 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2056 c896fe29 bellard
{
2057 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
2058 c896fe29 bellard
}
2059 c896fe29 bellard
2060 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2061 c896fe29 bellard
{
2062 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
2063 c896fe29 bellard
}
2064 c896fe29 bellard
2065 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2066 c896fe29 bellard
{
2067 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
2068 c896fe29 bellard
}
2069 c896fe29 bellard
2070 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2071 c896fe29 bellard
{
2072 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
2073 c896fe29 bellard
}
2074 c896fe29 bellard
2075 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2076 c896fe29 bellard
{
2077 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
2078 c896fe29 bellard
}
2079 c896fe29 bellard
2080 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2081 c896fe29 bellard
{
2082 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
2083 c896fe29 bellard
}
2084 c896fe29 bellard
2085 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2086 c896fe29 bellard
{
2087 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
2088 c896fe29 bellard
}
2089 c896fe29 bellard
2090 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i64
2091 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i64
2092 f8422f52 blueswir1
2093 c896fe29 bellard
#endif /* TCG_TARGET_REG_BITS != 32 */
2094 f8422f52 blueswir1
2095 f8422f52 blueswir1
#if TARGET_LONG_BITS == 64
2096 f8422f52 blueswir1
#define TCG_TYPE_TL TCG_TYPE_I64
2097 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i64
2098 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i64
2099 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2100 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2101 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2102 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2103 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2104 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2105 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i64
2106 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i64
2107 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i64
2108 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st32_i64
2109 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i64
2110 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i64
2111 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i64
2112 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i64
2113 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i64
2114 10460c8a pbrook
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
2115 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i64
2116 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i64
2117 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i64
2118 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i64
2119 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i64
2120 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i64
2121 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i64
2122 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i64
2123 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i64
2124 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i64
2125 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i64
2126 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i64
2127 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i64
2128 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i64
2129 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
2130 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
2131 be210acb Richard Henderson
#define tcg_gen_setcond_tl tcg_gen_setcond_i64
2132 add1e7ea Aurelien Jarno
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
2133 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i64
2134 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i64
2135 ab36421e aurel32
#define tcg_gen_div_tl tcg_gen_div_i64
2136 ab36421e aurel32
#define tcg_gen_rem_tl tcg_gen_rem_i64
2137 864951af aurel32
#define tcg_gen_divu_tl tcg_gen_divu_i64
2138 864951af aurel32
#define tcg_gen_remu_tl tcg_gen_remu_i64
2139 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i64
2140 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2141 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2142 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2143 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2144 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2145 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2146 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2147 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2148 0b6ce4cf bellard
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2149 0b6ce4cf bellard
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2150 0b6ce4cf bellard
#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2151 0b6ce4cf bellard
#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2152 911d79ba aurel32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2153 911d79ba aurel32
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2154 911d79ba aurel32
#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
2155 945ca823 blueswir1
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2156 f24cb33e aurel32
#define tcg_gen_andc_tl tcg_gen_andc_i64
2157 f24cb33e aurel32
#define tcg_gen_eqv_tl tcg_gen_eqv_i64
2158 f24cb33e aurel32
#define tcg_gen_nand_tl tcg_gen_nand_i64
2159 f24cb33e aurel32
#define tcg_gen_nor_tl tcg_gen_nor_i64
2160 f24cb33e aurel32
#define tcg_gen_orc_tl tcg_gen_orc_i64
2161 15824571 aurel32
#define tcg_gen_rotl_tl tcg_gen_rotl_i64
2162 15824571 aurel32
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
2163 15824571 aurel32
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
2164 15824571 aurel32
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
2165 a98824ac blueswir1
#define tcg_const_tl tcg_const_i64
2166 bdffd4a9 aurel32
#define tcg_const_local_tl tcg_const_local_i64
2167 f8422f52 blueswir1
#else
2168 f8422f52 blueswir1
#define TCG_TYPE_TL TCG_TYPE_I32
2169 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i32
2170 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i32
2171 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2172 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2173 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2174 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2175 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
2176 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
2177 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i32
2178 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i32
2179 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i32
2180 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st_i32
2181 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i32
2182 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i32
2183 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i32
2184 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i32
2185 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i32
2186 0045734a aurel32
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
2187 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i32
2188 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i32
2189 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i32
2190 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i32
2191 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i32
2192 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i32
2193 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i32
2194 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i32
2195 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i32
2196 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i32
2197 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i32
2198 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i32
2199 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i32
2200 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i32
2201 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
2202 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2203 be210acb Richard Henderson
#define tcg_gen_setcond_tl tcg_gen_setcond_i32
2204 add1e7ea Aurelien Jarno
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
2205 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i32
2206 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i32
2207 ab36421e aurel32
#define tcg_gen_div_tl tcg_gen_div_i32
2208 ab36421e aurel32
#define tcg_gen_rem_tl tcg_gen_rem_i32
2209 864951af aurel32
#define tcg_gen_divu_tl tcg_gen_divu_i32
2210 864951af aurel32
#define tcg_gen_remu_tl tcg_gen_remu_i32
2211 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i32
2212 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2213 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2214 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2215 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2216 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2217 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2218 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2219 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2220 0b6ce4cf bellard
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2221 0b6ce4cf bellard
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
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#define tcg_gen_ext32u_tl tcg_gen_mov_i32
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#define tcg_gen_ext32s_tl tcg_gen_mov_i32
2224 911d79ba aurel32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
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#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
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#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
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#define tcg_gen_andc_tl tcg_gen_andc_i32
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#define tcg_gen_eqv_tl tcg_gen_eqv_i32
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#define tcg_gen_nand_tl tcg_gen_nand_i32
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#define tcg_gen_nor_tl tcg_gen_nor_i32
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#define tcg_gen_orc_tl tcg_gen_orc_i32
2232 15824571 aurel32
#define tcg_gen_rotl_tl tcg_gen_rotl_i32
2233 15824571 aurel32
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
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#define tcg_gen_rotr_tl tcg_gen_rotr_i32
2235 15824571 aurel32
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
2236 a98824ac blueswir1
#define tcg_const_tl tcg_const_i32
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#define tcg_const_local_tl tcg_const_local_i32
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#endif
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#if TCG_TARGET_REG_BITS == 32
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#define tcg_gen_add_ptr tcg_gen_add_i32
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#define tcg_gen_addi_ptr tcg_gen_addi_i32
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#define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
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#else /* TCG_TARGET_REG_BITS == 32 */
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#define tcg_gen_add_ptr tcg_gen_add_i64
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#define tcg_gen_addi_ptr tcg_gen_addi_i64
2247 48d38ca5 ths
#define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
2248 6ddbc6e4 pbrook
#endif /* TCG_TARGET_REG_BITS != 32 */