Statistics
| Branch: | Revision:

root / tcg @ add1e7ea

# Date Author Comment
add1e7ea 02/08/2010 01:06 pm Aurelien Jarno

tcg: add setcondi pseudo-op

Signed-off-by: Aurelien Jarno <>
1cd62ae9 02/07/2010 01:48 am malc

tcg/ppc64: implement setcond

Signed-off-by: malc <>
27a7797b 02/07/2010 01:48 am malc

tcg/ppc32: proper setcond implementation

Signed-off-by: malc <>
b0809bf7 02/07/2010 01:18 am malc

tcg/ppc32: implement setcond2

Signed-off-by: malc <>
1d2699ae 02/06/2010 11:23 pm Richard Henderson

tcg-i386: Implement setcond.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
f75b56c1 02/06/2010 11:23 pm Richard Henderson

tcg-i386: Implement small forward branches.

There are places, like brcond2, where we know that the destination
of a forward branch will be within 127 bytes.

Add the R_386_PC8 relocation type to support this. Add a flag to
tcg_out_jxx and tcg_out_brcond* to enable it. Set the flag in the...
a38e609c 02/06/2010 06:14 pm Richard Henderson

tcg: document double-word support opcodes.

The internal opcodes brcond2, add2, sub2, mulu2 were undocumented.
Place these in a new section that clearly indicates that they are
not to be emitted by translators.

Signed-off-by: Richard Henderson <>...
be210acb 02/06/2010 06:14 pm Richard Henderson

tcg: generic support for conditional set

Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
401d466d 02/06/2010 06:14 pm Richard Henderson

tcg: add tcg_invert_cond

It is very handy to have a reliable mapping of a condition to its inverse.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
8f9db67c 02/06/2010 06:14 pm Richard Henderson

tcg-x86_64: implement setcond

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
09aac126 01/15/2010 08:32 am Richard Henderson

tcg/x86_64: Avoid unnecessary REX.B prefixes.

The existing P_REXB internal opcode flag unconditionally emits
the REX prefix. Technically it's not needed if the register in
question is %al, %bl, %cl, %dl.

Eliding the prefix requires splitting the P_REXB flag into two,...
57169903 01/14/2010 07:16 pm Richard Henderson

tcg/x86_64: Special-case all 32-bit AND operands.

This avoids an unnecessary REX.W prefix when dealing with AND
operands that fit into a 32-bit quantity. The most common change
actually seen is movz[wb]q -> movz[wb]l.

Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes....
cc6dfecf 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Implement ext32[su]_i64

The 32-bit right-shift instructions is defined to extend the shifted
output to 64-bits. A shift count of zero therefore is a simple
extension without actually shifting.

Signed-off-by: Richard Henderson <>...
583d1215 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Implement division properly.

The {div,divu}2 opcodes are intended for systems for which the
division instruction produces both quotient and remainder. Sparc
is not such a system. Indeed, the remainder must be computed as

quot = a / b
  rem = a - (quot * b)...
5e143c43 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Do not remove %o012 from 'r' constraint.

Only 'L' constraint needs that.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
7a3766f3 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Implement add2, sub2, mulu2.

Add missing 32-bit double-word support opcodes.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
ba225198 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Add tcg_out_arithc.

Add a function to handle the register-vs-immediate test for arithmetic.

Also, adjust the OP_32_64 macro so that it auto-indents properly.
Rename the gen_arith32 label to gen_arith, since it handles 64-bit
arithmetic as well....
ff44c2f3 12/27/2009 11:09 am Richard Henderson

tcg: Add tcg_unsigned_cond.

Returns an unsigned version of a signed condition;
returns the original condition otherwise.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
56f4927e 12/21/2009 10:52 pm Richard Henderson

tcg-sparc: Implement brcond2.

Split out tcg_out_cmp and properly handle immediate arguments.
Fix constraints on brcond to match what SUBCC accepts.
Add tcg_out_brcond2_i32 for 32-bit host.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
a212ea75 12/21/2009 10:52 pm Richard Henderson

tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.

The test TCG_TARGET_REG_BITS==64 is exactly the feature that we
are checking for, whereas something involving sparc_v9 or
sparc_v8plus should be reserved for something ISA related,
as with SMULX....
43172207 12/21/2009 10:52 pm Richard Henderson

tcg-sparc: Improve tcg_out_movi for sparc64.

Generate sign-extended 32-bit constants with SETHI+XOR.
Otherwise tidy the routine to avoid the need for
conditional compilation and code duplication with movi_imm32.

Signed-off-by: Richard Henderson <>...
4a09aa89 12/21/2009 10:49 pm Richard Henderson

tcg-sparc: Fix imm13 check in movi.

We were unnecessarily restricting imm13 constants to 12 bits.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
591d6f1d 12/15/2009 06:45 pm malc

tcg/ppc64: Fix loading of 32bit constants

Signed-off-by: malc <>
5d7ff5bb 12/06/2009 05:20 pm Andreas Faerber

TCG: Mac OS X support for ppc64 target

Darwin/ppc64 does not use function descriptors,
adapt prologue and tcg_out_call accordingly.
GPR2 is available for general use, so let's use it.

http://developer.apple.com/mac/library/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html...
2827822e 12/05/2009 06:36 pm Alexander Graf

S/390 fake TCG implementation

Qemu won't let us run a KVM target without having host TCG support. Well, for
now we don't have any so let's implement a fake target that only stubs out
everything.

I tried to keep the patch as close to Uli's source as possible, so whenever...
afa05235 12/01/2009 02:06 am Aurelien Jarno

tcg: initial mips support

Based on a patch from Arnaud Patard (Rtp) <>

A few words about design choices:
  • Two registers, at and t0, are reserved for TCG internal use. They are
    useful for bswap and 64-bit ops.
  • Most ops supports a constant argument with value 0, which is actually...
7d301752 11/24/2009 08:51 pm Aurelien Jarno

tcg: fix tcg_regset_{set,reset}_reg with more than 32 registers

Signed-off-by: Aurelien Jarno <>
016b2b28 11/24/2009 08:51 pm Aurelien Jarno

tcg/ppc64,x86_64: fix constraints of op_qemu_st64

This op only takes two arguments, not two.

Signed-off-by: Aurelien Jarno <>
b785e476 11/14/2009 02:17 am Magnus Damm

tcg/i386: remove duplicate sar opcode

Signed-off-by: Magnus Damm <>
Signed-off-by: Aurelien Jarno <>
6a957025 10/07/2009 08:53 am Aurelien Jarno

tcg: improve output log

Signed-off-by: Aurelien Jarno <>
94f4af02 10/04/2009 04:30 pm Aurelien Jarno

tcg: allocate s->op_dead_iargs dynamically

Similarly to what is already done in tcg_liveness_analysis() when
USE_LIVENESS_ANALYSIS is not set.

Signed-off-by: Aurelien Jarno <>
8389c67b 10/04/2009 04:16 pm Aurelien Jarno

tcg: remove dead code

Signed-off-by: Aurelien Jarno <>
cfc86988 10/04/2009 02:24 pm Aurelien Jarno

tcg: add ext{8,16,32}u_i{32,64} TCG ops

Currently zero extensions ops are implemented by a and op with a
constant. This is then catched in some backend, and replaced by
a zero extension instruction. While this works well on RISC
machines, this adds a useless register move on non-RISC machines....
64584218 10/04/2009 02:24 pm Aurelien Jarno

tcg/x86_64: add support for ext{8,16,32}u_i{32,64} TCG ops

Signed-off-by: Aurelien Jarno <>
5f0ce17f 10/04/2009 02:24 pm Aurelien Jarno

tcg/i386: add support for ext{8,16}u_i32 TCG ops

Signed-off-by: Aurelien Jarno <>
d6859202 09/30/2009 03:16 pm Aurelien Jarno

Revert part of 6692b043198d58a12317009edb98654c6839f043

Committed by accident.

Signed-off-by: Aurelien Jarno <>
6692b043 09/30/2009 03:10 pm Aurelien Jarno

TCG: fix DEF2 macro

Signed-off-by: Aurelien Jarno <>
17cf428f 09/27/2009 09:00 pm Aurelien Jarno

tcg/i386: generates dec/inc instead of sub/add when possible

We must take care that dec/inc do not compute CF, which is needed by
add2/sub2.

Signed-off-by: Aurelien Jarno <>
b70650cb 09/27/2009 09:00 pm Aurelien Jarno

tcg/i386: optimize and $0xff(ff), reg

Signed-off-by: Aurelien Jarno <>
a4b18c6d 09/27/2009 07:08 pm Aurelien Jarno

tcg/x86_64: generated dec/inc instead of sub/add when possible

Signed-off-by: Aurelien Jarno <>
d9370327 09/27/2009 01:41 pm malc

tcg/ppc: always use tcg_out_call

Signed-off-by: malc <>
7990496d 09/26/2009 10:29 pm Laurent Desnogues

ARM back-end: Use sxt[bh] instructions for ext{8, 6}s

This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end.

Signed-off-by: Laurent Desnogues <>
Signed-off-by: Aurelien Jarno <>
d89c682f 09/25/2009 05:31 pm Stefan Weil

Suppress some variants of English in comments

Replace surpress, supress by suppress.

Signed-off-by: Stefan Weil <>
Signed-off-by: Aurelien Jarno <>
96e132e2 09/20/2009 10:06 pm Blue Swirl

Compile TCG runtime library only once

Signed-off-by: Blue Swirl <>
b348113d 09/16/2009 10:26 pm Stefan Weil

tcg: fix size of local variables in tcg_gen_bswap64_i64

t0, t1 must be 64 bit values, not 32 bit.

Signed-off-by: Stefan Weil <>
Signed-off-by: Aurelien Jarno <>
abb6ae2c 09/11/2009 12:38 am malc

X86_64: Use proper jumps/calls when displacement exceeds +-2G

Signed-off-by: malc <>
c45851c4 09/06/2009 06:24 am malc

When targeting PPU use rlwinm instead of andi. if possible

andi. is microcoded and slow there.

Signed-off-by: malc <>
4e6f6d4c 08/25/2009 02:14 am Laurent Desnogues

ARM back-end: Fix encode_imm

the encode_imm function in tcg/arm/tcg-target.c lacks shift declaration.

Laurent

Signed-off-by: Laurent Desnogues <>
Signed-off-by: Andrzej Zaborowski <>
94953e6d 08/22/2009 03:29 pm Laurent Desnogues

ARM back-end: Handle all possible immediates for ALU ops

this patch handles all possible constants for immediate operand of ALU ops.
I'm not very satisfied by the implementation.

Laurent

Signed-off-by: Laurent Desnogues <>
Signed-off-by: Andrzej Zaborowski <>
f878d2d2 08/22/2009 02:55 pm Laurent Desnogues

ARM back-end: Add TCG not

this patch:

- implements TCG not.

Laurent

Signed-off-by: Laurent Desnogues <>
Signed-off-by: Andrzej Zaborowski <>
092c73ee 07/27/2009 10:09 pm Juan Quintela

rename DEBUG_TCG to CONFIG_DEBUG_TCG

Signed-off-by: Juan Quintela <>
Signed-off-by: Anthony Liguori <>
e2542fe2 07/27/2009 10:09 pm Juan Quintela

rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN

Signed-off-by: Juan Quintela <>
Signed-off-by: Anthony Liguori <>
dfe5fff3 07/27/2009 10:09 pm Juan Quintela

change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}

Signed-off-by: Juan Quintela <>
Signed-off-by: Anthony Liguori <>
871e6c35 07/21/2009 03:18 pm Blue Swirl

Fix CONFIG_PROFILER

Signed-off-by: Blue Swirl <>
a71836de 07/20/2009 12:15 am malc

Fix rbase initialization

Signed-off-by: malc <>
cb4e581f 07/18/2009 03:20 pm Laurent Desnogues

this patch improves the ARM back-end in the following way:

- use movw/movt to load immediate values for ARMv7-A
- implement add/sub/and/or/xor with immediate (only 8-bit)

Laurent

Signed-off-by: Laurent Desnogues <>
Signed-off-by: Andrzej Zaborowski <>
d9885a0b 07/18/2009 12:32 pm Aurelien Jarno

tcg: Fix tcg_gen_rotr_i64

Reported-by: Laurent Desnogues <>
Signed-off-by: Aurelien Jarno <>
f6548c0a 07/18/2009 12:16 pm malc

PPC 32/64 GUEST_BASE support

Signed-off-by: malc <>
4f4a67ae 07/18/2009 12:16 pm malc

Fix LHZX opcode value

Signed-off-by: malc <>
adea8197 07/17/2009 09:50 pm Juan Quintela

Userspace guest address offsetting

Fix type in i386 tcg.

Signed-off-by: Juan Quintela <>
379f6698 07/17/2009 03:12 pm Paul Brook

Userspace guest address offsetting

Re-implement GUEST_BASE support.
Offset guest ddress space by default if the guest binary contains
regions below the host mmap_min_addr.
Implement support for i386, x86-64 and arm hosts.

Signed-off-by: Riku Voipio <>...
2d69f359 07/17/2009 01:21 pm Paul Brook

ARM host fixes

Minor TCG cleanups and warning fixes for ARM hosts.

Signed-off-by: Paul Brook <>
55616505 05/13/2009 10:54 pm Paul Brook

Include assert.h from qemu-common.h

Include assert.h from qemu-common.h and remove other direct uses.
cpu-all.h still need to include it because of the dyngen-exec.h hacks

Signed-off-by: Paul Brook <>
cca82982 04/16/2009 12:58 pm aurel32

tcg: make sure NDEBUG is defined before including <assert.h>

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7122 c046a42c-6fe2-441c-8c8c-71466251a162
f8393946 04/13/2009 09:45 pm aurel32

Add a --enable-debug-tcg option to configure

This patch allows DEBUG_TCGV to be defined (and also prevents NDEBUG
from being defined) when passing an option to the configure script.
This should help to prevent any accidental changes that enable
DEBUG_TCGV in tcg/tcg.h from being committed in future, and may...
2ffebe2d 04/11/2009 11:19 am malc

Remove reserved registers from tcg_target_reg_alloc_order

Noticed by Andreas Faerber

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7082 c046a42c-6fe2-441c-8c8c-71466251a162
9de187a0 04/11/2009 10:39 am malc

Whack [LS]MW

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
e23f2f36 04/11/2009 10:38 am malc

Remove reserved registers from tcg_target_reg_alloc_order

Noticed by Andreas Faerber

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
3e00b3f5 04/07/2009 10:57 pm aurel32

tcg/tcg.h: fix a few typos

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7024 c046a42c-6fe2-441c-8c8c-71466251a162
b9c18f56 04/06/2009 03:33 pm aurel32

tcg: add a CONST flag to TCG helpers

A const function only reads its arguments and does not use TCG
globals variables. Hence a call to such a function does not
save TCG globals variabes back to their canonical location.

Signed-off-by: Aurelien Jarno <>...
34d5a9ff 04/06/2009 03:33 pm aurel32

tcg: improve comment about pure functions

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7007 c046a42c-6fe2-441c-8c8c-71466251a162
79d342dc 04/05/2009 11:08 pm aurel32

tcg/x86_64: optimize register allocation order

The beginning of the register allocation order list on the TCG x86_64
target matches the list of clobbered registers. This means that when an
helper is called, there is almost always clobbered registers that have...
1da92db2 04/04/2009 10:10 pm blueswir1

Fix branches and TLB matches for 64 bit targets

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6974 c046a42c-6fe2-441c-8c8c-71466251a162
f843e528 04/04/2009 06:33 pm blueswir1

Allocate space for static call args, increase stack frame size on Sparc64

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6973 c046a42c-6fe2-441c-8c8c-71466251a162
864951af 03/29/2009 05:08 pm aurel32

tcg: fix _tl aliases for divu/remu

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6948 c046a42c-6fe2-441c-8c8c-71466251a162
ab36421e 03/29/2009 04:19 am aurel32

tcg: add _tl aliases for div/divu/rem/remu

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6939 c046a42c-6fe2-441c-8c8c-71466251a162
604457d7 03/29/2009 01:27 am aurel32

tcg/README: fix description of bswap32_i32/i64

Thanks to Stuart Brady for the notice.

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6920 c046a42c-6fe2-441c-8c8c-71466251a162
86dbdd40 03/13/2009 11:35 am aurel32

tcg/x86_64: add bswap16_i{32,64} and bswap32_i64 ops

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6838 c046a42c-6fe2-441c-8c8c-71466251a162
5d40cd63 03/13/2009 11:35 am aurel32

tcg/x86: add bswap16_i32 ops

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6837 c046a42c-6fe2-441c-8c8c-71466251a162
4ad4ce16 03/13/2009 11:35 am aurel32

tcg: update README wrt recent bswap changes

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6834 c046a42c-6fe2-441c-8c8c-71466251a162
911d79ba 03/13/2009 11:35 am aurel32

tcg: add _tl aliases to bswap16/32/64 TCG ops

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6833 c046a42c-6fe2-441c-8c8c-71466251a162
9a5c57fd 03/13/2009 11:35 am aurel32

tcg: add bswap16_i64 and bswap32_i64 TCG ops

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6832 c046a42c-6fe2-441c-8c8c-71466251a162
dfa1a3f1 03/13/2009 11:35 am aurel32

tcg: optimize tcg_gen_bswap16_i32

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6831 c046a42c-6fe2-441c-8c8c-71466251a162
84aafb06 03/13/2009 11:34 am aurel32

tcg: allow bswap16_i32 to be implemented by TCG backends

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6830 c046a42c-6fe2-441c-8c8c-71466251a162
66896cb8 03/13/2009 11:34 am aurel32

tcg: rename bswap_i32/i64 functions

Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
0dd0dd55 03/11/2009 01:00 pm aurel32

tcg: move {not,neg}_i{32,64} definitions at the right place

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6811 c046a42c-6fe2-441c-8c8c-71466251a162
e5105083 03/11/2009 04:57 am aurel32

tcg: fix commit r6805

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6810 c046a42c-6fe2-441c-8c8c-71466251a162
419bafa5 03/10/2009 11:43 pm aurel32

tcg-arm: fix qemu_ld64

Emulating fldl on arm doesn't seem to work too well. It's the way
qemu_ld64 is translated to arm instructions.

tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
        tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);...
506bfcbb 03/10/2009 09:37 pm aurel32

tcg: update TODO

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6807 c046a42c-6fe2-441c-8c8c-71466251a162
9619376c 03/10/2009 09:37 pm aurel32

tcg/x86: add not/neg/extu/bswap/rot i32 ops

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6806 c046a42c-6fe2-441c-8c8c-71466251a162
7fc81051 03/10/2009 09:37 pm aurel32

tcg: optimize logical operations

Simplify nand/nor/eqv and move their optimizations to and/or/xor

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6805 c046a42c-6fe2-441c-8c8c-71466251a162
43e860ef 03/10/2009 12:29 pm aurel32

Fix tcg after commit 6800

The introduction of TCGV_EQUAL and not op is slightly broken.
The definition of DEBUG_TCGV shows that.

Signed-off-by: Laurent Desnogues <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6802 c046a42c-6fe2-441c-8c8c-71466251a162
fe75bcf7 03/10/2009 10:57 am aurel32

tcg: use TCGV_EQUAL_I{32,64}

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6800 c046a42c-6fe2-441c-8c8c-71466251a162
44e6acb0 03/10/2009 10:56 am aurel32

tcg: define TCGV_EQUAL_I{32,64}

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6799 c046a42c-6fe2-441c-8c8c-71466251a162
c29d0de4 03/10/2009 12:35 am aurel32

tcg: optimize nor(X, Y, Y), used on PPC for not(X, Y)

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6798 c046a42c-6fe2-441c-8c8c-71466251a162
d2604285 03/10/2009 12:35 am aurel32

Implement TCG not ops for x86-64

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6797 c046a42c-6fe2-441c-8c8c-71466251a162
f31e9370 03/09/2009 11:58 pm aurel32

tcg: don't define TCG rotation ops if they are not supported

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6796 c046a42c-6fe2-441c-8c8c-71466251a162
d42f183c 03/09/2009 08:50 pm aurel32

Implement TCG rotation ops for x86-64

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6795 c046a42c-6fe2-441c-8c8c-71466251a162
e63d7abd 03/08/2009 04:45 pm blueswir1

Prune unused TCG_AREGs

Remove definitions for TCG_AREGs corresponding to AREG definitions
removed in r6778.

Signed-off-by: Stuart Brady <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
9e622b15 03/07/2009 05:46 pm blueswir1

Sparse fixes: truncation by cast

Fix Sparse warnings about constant truncation caused by cast

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6737 c046a42c-6fe2-441c-8c8c-71466251a162