root / tcg / tcg-op.h @ add1e7ea
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "tcg.h" |
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int gen_new_label(void); |
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static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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} |
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static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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} |
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static inline void tcg_gen_op1i(int opc, TCGArg arg1) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = arg1; |
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} |
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static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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} |
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static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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} |
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static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = arg2; |
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} |
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static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = arg2; |
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} |
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static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = arg1; |
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*gen_opparam_ptr++ = arg2; |
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} |
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static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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} |
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static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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} |
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static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGArg arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = arg3; |
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} |
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static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGArg arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = arg3; |
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} |
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static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base, |
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TCGArg offset) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(val); |
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*gen_opparam_ptr++ = GET_TCGV_PTR(base); |
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*gen_opparam_ptr++ = offset; |
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} |
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static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base, |
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TCGArg offset) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(val); |
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*gen_opparam_ptr++ = GET_TCGV_PTR(base); |
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*gen_opparam_ptr++ = offset; |
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} |
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static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr, |
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TCGArg mem_index) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(val); |
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*gen_opparam_ptr++ = GET_TCGV_I32(addr); |
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*gen_opparam_ptr++ = mem_index; |
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} |
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static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr, |
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TCGArg mem_index) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(val); |
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*gen_opparam_ptr++ = GET_TCGV_I64(addr); |
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*gen_opparam_ptr++ = mem_index; |
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} |
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static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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} |
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static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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} |
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static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGArg arg3, TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = arg3; |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGArg arg3, TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = arg3; |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
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} |
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static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
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} |
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static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = arg5; |
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} |
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static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = arg5; |
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} |
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static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, |
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TCGv_i32 arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg6); |
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} |
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static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, |
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TCGv_i64 arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg6); |
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} |
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static inline void tcg_gen_op6i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, |
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TCGv_i32 arg5, TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
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*gen_opparam_ptr++ = arg6; |
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} |
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static inline void tcg_gen_op6i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, |
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TCGv_i64 arg5, TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
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*gen_opparam_ptr++ = arg6; |
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} |
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static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5, |
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TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = arg5; |
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*gen_opparam_ptr++ = arg6; |
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} |
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static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5, |
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TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = arg5; |
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*gen_opparam_ptr++ = arg6; |
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} |
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static inline void gen_set_label(int n) |
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{ |
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tcg_gen_op1i(INDEX_op_set_label, n); |
338 |
} |
339 |
|
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static inline void tcg_gen_br(int label) |
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{ |
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tcg_gen_op1i(INDEX_op_br, label); |
343 |
} |
344 |
|
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static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
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{ |
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if (!TCGV_EQUAL_I32(ret, arg))
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tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
349 |
} |
350 |
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static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
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{ |
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tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
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} |
355 |
|
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/* helper calls */
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static inline void tcg_gen_helperN(void *func, int flags, int sizemask, |
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TCGArg ret, int nargs, TCGArg *args)
|
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{ |
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TCGv_ptr fn; |
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fn = tcg_const_ptr((tcg_target_long)func); |
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tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret, |
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nargs, args); |
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tcg_temp_free_ptr(fn); |
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} |
366 |
|
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/* FIXME: Should this be pure? */
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static inline void tcg_gen_helper64(void *func, TCGv_i64 ret, |
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TCGv_i64 a, TCGv_i64 b) |
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{ |
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TCGv_ptr fn; |
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TCGArg args[2];
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fn = tcg_const_ptr((tcg_target_long)func); |
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args[0] = GET_TCGV_I64(a);
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args[1] = GET_TCGV_I64(b);
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tcg_gen_callN(&tcg_ctx, fn, 0, 7, GET_TCGV_I64(ret), 2, args); |
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tcg_temp_free_ptr(fn); |
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} |
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|
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/* 32 bit ops */
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static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
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{ |
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tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
385 |
} |
386 |
|
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static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
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{ |
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tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
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} |
391 |
|
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static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
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{ |
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tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
395 |
} |
396 |
|
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static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
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{ |
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tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
400 |
} |
401 |
|
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static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
403 |
{ |
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tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
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} |
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|
407 |
static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
408 |
{ |
409 |
tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
410 |
} |
411 |
|
412 |
static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
413 |
{ |
414 |
tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
415 |
} |
416 |
|
417 |
static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
418 |
{ |
419 |
tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
420 |
} |
421 |
|
422 |
static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
423 |
{ |
424 |
tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
425 |
} |
426 |
|
427 |
static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
428 |
{ |
429 |
/* some cases can be optimized here */
|
430 |
if (arg2 == 0) { |
431 |
tcg_gen_mov_i32(ret, arg1); |
432 |
} else {
|
433 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
434 |
tcg_gen_add_i32(ret, arg1, t0); |
435 |
tcg_temp_free_i32(t0); |
436 |
} |
437 |
} |
438 |
|
439 |
static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
440 |
{ |
441 |
tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
442 |
} |
443 |
|
444 |
static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) |
445 |
{ |
446 |
TCGv_i32 t0 = tcg_const_i32(arg1); |
447 |
tcg_gen_sub_i32(ret, t0, arg2); |
448 |
tcg_temp_free_i32(t0); |
449 |
} |
450 |
|
451 |
static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
452 |
{ |
453 |
/* some cases can be optimized here */
|
454 |
if (arg2 == 0) { |
455 |
tcg_gen_mov_i32(ret, arg1); |
456 |
} else {
|
457 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
458 |
tcg_gen_sub_i32(ret, arg1, t0); |
459 |
tcg_temp_free_i32(t0); |
460 |
} |
461 |
} |
462 |
|
463 |
static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
464 |
{ |
465 |
if (TCGV_EQUAL_I32(arg1, arg2)) {
|
466 |
tcg_gen_mov_i32(ret, arg1); |
467 |
} else {
|
468 |
tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); |
469 |
} |
470 |
} |
471 |
|
472 |
static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
473 |
{ |
474 |
/* some cases can be optimized here */
|
475 |
if (arg2 == 0) { |
476 |
tcg_gen_movi_i32(ret, 0);
|
477 |
} else if (arg2 == 0xffffffff) { |
478 |
tcg_gen_mov_i32(ret, arg1); |
479 |
} else {
|
480 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
481 |
tcg_gen_and_i32(ret, arg1, t0); |
482 |
tcg_temp_free_i32(t0); |
483 |
} |
484 |
} |
485 |
|
486 |
static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
487 |
{ |
488 |
if (TCGV_EQUAL_I32(arg1, arg2)) {
|
489 |
tcg_gen_mov_i32(ret, arg1); |
490 |
} else {
|
491 |
tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); |
492 |
} |
493 |
} |
494 |
|
495 |
static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
496 |
{ |
497 |
/* some cases can be optimized here */
|
498 |
if (arg2 == 0xffffffff) { |
499 |
tcg_gen_movi_i32(ret, 0xffffffff);
|
500 |
} else if (arg2 == 0) { |
501 |
tcg_gen_mov_i32(ret, arg1); |
502 |
} else {
|
503 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
504 |
tcg_gen_or_i32(ret, arg1, t0); |
505 |
tcg_temp_free_i32(t0); |
506 |
} |
507 |
} |
508 |
|
509 |
static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
510 |
{ |
511 |
if (TCGV_EQUAL_I32(arg1, arg2)) {
|
512 |
tcg_gen_movi_i32(ret, 0);
|
513 |
} else {
|
514 |
tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); |
515 |
} |
516 |
} |
517 |
|
518 |
static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
519 |
{ |
520 |
/* some cases can be optimized here */
|
521 |
if (arg2 == 0) { |
522 |
tcg_gen_mov_i32(ret, arg1); |
523 |
} else {
|
524 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
525 |
tcg_gen_xor_i32(ret, arg1, t0); |
526 |
tcg_temp_free_i32(t0); |
527 |
} |
528 |
} |
529 |
|
530 |
static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
531 |
{ |
532 |
tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
533 |
} |
534 |
|
535 |
static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
536 |
{ |
537 |
if (arg2 == 0) { |
538 |
tcg_gen_mov_i32(ret, arg1); |
539 |
} else {
|
540 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
541 |
tcg_gen_shl_i32(ret, arg1, t0); |
542 |
tcg_temp_free_i32(t0); |
543 |
} |
544 |
} |
545 |
|
546 |
static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
547 |
{ |
548 |
tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
549 |
} |
550 |
|
551 |
static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
552 |
{ |
553 |
if (arg2 == 0) { |
554 |
tcg_gen_mov_i32(ret, arg1); |
555 |
} else {
|
556 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
557 |
tcg_gen_shr_i32(ret, arg1, t0); |
558 |
tcg_temp_free_i32(t0); |
559 |
} |
560 |
} |
561 |
|
562 |
static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
563 |
{ |
564 |
tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
565 |
} |
566 |
|
567 |
static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
568 |
{ |
569 |
if (arg2 == 0) { |
570 |
tcg_gen_mov_i32(ret, arg1); |
571 |
} else {
|
572 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
573 |
tcg_gen_sar_i32(ret, arg1, t0); |
574 |
tcg_temp_free_i32(t0); |
575 |
} |
576 |
} |
577 |
|
578 |
static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2, |
579 |
int label_index)
|
580 |
{ |
581 |
tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
582 |
} |
583 |
|
584 |
static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2, |
585 |
int label_index)
|
586 |
{ |
587 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
588 |
tcg_gen_brcond_i32(cond, arg1, t0, label_index); |
589 |
tcg_temp_free_i32(t0); |
590 |
} |
591 |
|
592 |
static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
593 |
{ |
594 |
tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
595 |
} |
596 |
|
597 |
static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
598 |
{ |
599 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
600 |
tcg_gen_mul_i32(ret, arg1, t0); |
601 |
tcg_temp_free_i32(t0); |
602 |
} |
603 |
|
604 |
#ifdef TCG_TARGET_HAS_div_i32
|
605 |
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
606 |
{ |
607 |
tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); |
608 |
} |
609 |
|
610 |
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
611 |
{ |
612 |
tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); |
613 |
} |
614 |
|
615 |
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
616 |
{ |
617 |
tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); |
618 |
} |
619 |
|
620 |
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
621 |
{ |
622 |
tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); |
623 |
} |
624 |
#else
|
625 |
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
626 |
{ |
627 |
TCGv_i32 t0; |
628 |
t0 = tcg_temp_new_i32(); |
629 |
tcg_gen_sari_i32(t0, arg1, 31);
|
630 |
tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
631 |
tcg_temp_free_i32(t0); |
632 |
} |
633 |
|
634 |
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
635 |
{ |
636 |
TCGv_i32 t0; |
637 |
t0 = tcg_temp_new_i32(); |
638 |
tcg_gen_sari_i32(t0, arg1, 31);
|
639 |
tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
640 |
tcg_temp_free_i32(t0); |
641 |
} |
642 |
|
643 |
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
644 |
{ |
645 |
TCGv_i32 t0; |
646 |
t0 = tcg_temp_new_i32(); |
647 |
tcg_gen_movi_i32(t0, 0);
|
648 |
tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
649 |
tcg_temp_free_i32(t0); |
650 |
} |
651 |
|
652 |
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
653 |
{ |
654 |
TCGv_i32 t0; |
655 |
t0 = tcg_temp_new_i32(); |
656 |
tcg_gen_movi_i32(t0, 0);
|
657 |
tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
658 |
tcg_temp_free_i32(t0); |
659 |
} |
660 |
#endif
|
661 |
|
662 |
#if TCG_TARGET_REG_BITS == 32 |
663 |
|
664 |
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
665 |
{ |
666 |
if (!TCGV_EQUAL_I64(ret, arg)) {
|
667 |
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
668 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
669 |
} |
670 |
} |
671 |
|
672 |
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
673 |
{ |
674 |
tcg_gen_movi_i32(TCGV_LOW(ret), arg); |
675 |
tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
|
676 |
} |
677 |
|
678 |
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
679 |
tcg_target_long offset) |
680 |
{ |
681 |
tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); |
682 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
683 |
} |
684 |
|
685 |
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
686 |
tcg_target_long offset) |
687 |
{ |
688 |
tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); |
689 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
|
690 |
} |
691 |
|
692 |
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
693 |
tcg_target_long offset) |
694 |
{ |
695 |
tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); |
696 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
697 |
} |
698 |
|
699 |
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
700 |
tcg_target_long offset) |
701 |
{ |
702 |
tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); |
703 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
704 |
} |
705 |
|
706 |
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
707 |
tcg_target_long offset) |
708 |
{ |
709 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
710 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
711 |
} |
712 |
|
713 |
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
714 |
tcg_target_long offset) |
715 |
{ |
716 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
717 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
718 |
} |
719 |
|
720 |
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
721 |
tcg_target_long offset) |
722 |
{ |
723 |
/* since arg2 and ret have different types, they cannot be the
|
724 |
same temporary */
|
725 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
726 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
727 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
|
728 |
#else
|
729 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
730 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
|
731 |
#endif
|
732 |
} |
733 |
|
734 |
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
735 |
tcg_target_long offset) |
736 |
{ |
737 |
tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
738 |
} |
739 |
|
740 |
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
741 |
tcg_target_long offset) |
742 |
{ |
743 |
tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
744 |
} |
745 |
|
746 |
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
747 |
tcg_target_long offset) |
748 |
{ |
749 |
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
750 |
} |
751 |
|
752 |
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
753 |
tcg_target_long offset) |
754 |
{ |
755 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
756 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
757 |
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
|
758 |
#else
|
759 |
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
760 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
|
761 |
#endif
|
762 |
} |
763 |
|
764 |
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
765 |
{ |
766 |
tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
767 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
768 |
TCGV_HIGH(arg2)); |
769 |
} |
770 |
|
771 |
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
772 |
{ |
773 |
tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
774 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
775 |
TCGV_HIGH(arg2)); |
776 |
} |
777 |
|
778 |
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
779 |
{ |
780 |
tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
781 |
tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
782 |
} |
783 |
|
784 |
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
785 |
{ |
786 |
tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
787 |
tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
788 |
} |
789 |
|
790 |
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
791 |
{ |
792 |
tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
793 |
tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
794 |
} |
795 |
|
796 |
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
797 |
{ |
798 |
tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
799 |
tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
800 |
} |
801 |
|
802 |
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
803 |
{ |
804 |
tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
805 |
tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
806 |
} |
807 |
|
808 |
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
809 |
{ |
810 |
tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
811 |
tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
812 |
} |
813 |
|
814 |
/* XXX: use generic code when basic block handling is OK or CPU
|
815 |
specific code (x86) */
|
816 |
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
817 |
{ |
818 |
tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2); |
819 |
} |
820 |
|
821 |
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
822 |
{ |
823 |
tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); |
824 |
} |
825 |
|
826 |
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
827 |
{ |
828 |
tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2); |
829 |
} |
830 |
|
831 |
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
832 |
{ |
833 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); |
834 |
} |
835 |
|
836 |
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
837 |
{ |
838 |
tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2); |
839 |
} |
840 |
|
841 |
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
842 |
{ |
843 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); |
844 |
} |
845 |
|
846 |
static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2, |
847 |
int label_index)
|
848 |
{ |
849 |
tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, |
850 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
851 |
TCGV_HIGH(arg2), cond, label_index); |
852 |
} |
853 |
|
854 |
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
855 |
{ |
856 |
TCGv_i64 t0; |
857 |
TCGv_i32 t1; |
858 |
|
859 |
t0 = tcg_temp_new_i64(); |
860 |
t1 = tcg_temp_new_i32(); |
861 |
|
862 |
tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), |
863 |
TCGV_LOW(arg1), TCGV_LOW(arg2)); |
864 |
|
865 |
tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); |
866 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
867 |
tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); |
868 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
869 |
|
870 |
tcg_gen_mov_i64(ret, t0); |
871 |
tcg_temp_free_i64(t0); |
872 |
tcg_temp_free_i32(t1); |
873 |
} |
874 |
|
875 |
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
876 |
{ |
877 |
tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2); |
878 |
} |
879 |
|
880 |
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
881 |
{ |
882 |
tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2); |
883 |
} |
884 |
|
885 |
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
886 |
{ |
887 |
tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2); |
888 |
} |
889 |
|
890 |
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
891 |
{ |
892 |
tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2); |
893 |
} |
894 |
|
895 |
#else
|
896 |
|
897 |
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
898 |
{ |
899 |
if (!TCGV_EQUAL_I64(ret, arg))
|
900 |
tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
901 |
} |
902 |
|
903 |
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
904 |
{ |
905 |
tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
906 |
} |
907 |
|
908 |
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
909 |
tcg_target_long offset) |
910 |
{ |
911 |
tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
912 |
} |
913 |
|
914 |
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
915 |
tcg_target_long offset) |
916 |
{ |
917 |
tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
918 |
} |
919 |
|
920 |
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
921 |
tcg_target_long offset) |
922 |
{ |
923 |
tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
924 |
} |
925 |
|
926 |
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
927 |
tcg_target_long offset) |
928 |
{ |
929 |
tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
930 |
} |
931 |
|
932 |
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
933 |
tcg_target_long offset) |
934 |
{ |
935 |
tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
936 |
} |
937 |
|
938 |
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
939 |
tcg_target_long offset) |
940 |
{ |
941 |
tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
942 |
} |
943 |
|
944 |
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset) |
945 |
{ |
946 |
tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
947 |
} |
948 |
|
949 |
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
950 |
tcg_target_long offset) |
951 |
{ |
952 |
tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
953 |
} |
954 |
|
955 |
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
956 |
tcg_target_long offset) |
957 |
{ |
958 |
tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
959 |
} |
960 |
|
961 |
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
962 |
tcg_target_long offset) |
963 |
{ |
964 |
tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
965 |
} |
966 |
|
967 |
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset) |
968 |
{ |
969 |
tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
970 |
} |
971 |
|
972 |
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
973 |
{ |
974 |
tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
975 |
} |
976 |
|
977 |
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
978 |
{ |
979 |
tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
980 |
} |
981 |
|
982 |
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
983 |
{ |
984 |
if (TCGV_EQUAL_I64(arg1, arg2)) {
|
985 |
tcg_gen_mov_i64(ret, arg1); |
986 |
} else {
|
987 |
tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); |
988 |
} |
989 |
} |
990 |
|
991 |
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
992 |
{ |
993 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
994 |
tcg_gen_and_i64(ret, arg1, t0); |
995 |
tcg_temp_free_i64(t0); |
996 |
} |
997 |
|
998 |
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
999 |
{ |
1000 |
if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1001 |
tcg_gen_mov_i64(ret, arg1); |
1002 |
} else {
|
1003 |
tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); |
1004 |
} |
1005 |
} |
1006 |
|
1007 |
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1008 |
{ |
1009 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1010 |
tcg_gen_or_i64(ret, arg1, t0); |
1011 |
tcg_temp_free_i64(t0); |
1012 |
} |
1013 |
|
1014 |
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1015 |
{ |
1016 |
if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1017 |
tcg_gen_movi_i64(ret, 0);
|
1018 |
} else {
|
1019 |
tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); |
1020 |
} |
1021 |
} |
1022 |
|
1023 |
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1024 |
{ |
1025 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1026 |
tcg_gen_xor_i64(ret, arg1, t0); |
1027 |
tcg_temp_free_i64(t0); |
1028 |
} |
1029 |
|
1030 |
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1031 |
{ |
1032 |
tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
1033 |
} |
1034 |
|
1035 |
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1036 |
{ |
1037 |
if (arg2 == 0) { |
1038 |
tcg_gen_mov_i64(ret, arg1); |
1039 |
} else {
|
1040 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1041 |
tcg_gen_shl_i64(ret, arg1, t0); |
1042 |
tcg_temp_free_i64(t0); |
1043 |
} |
1044 |
} |
1045 |
|
1046 |
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1047 |
{ |
1048 |
tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
1049 |
} |
1050 |
|
1051 |
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1052 |
{ |
1053 |
if (arg2 == 0) { |
1054 |
tcg_gen_mov_i64(ret, arg1); |
1055 |
} else {
|
1056 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1057 |
tcg_gen_shr_i64(ret, arg1, t0); |
1058 |
tcg_temp_free_i64(t0); |
1059 |
} |
1060 |
} |
1061 |
|
1062 |
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1063 |
{ |
1064 |
tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
1065 |
} |
1066 |
|
1067 |
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1068 |
{ |
1069 |
if (arg2 == 0) { |
1070 |
tcg_gen_mov_i64(ret, arg1); |
1071 |
} else {
|
1072 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1073 |
tcg_gen_sar_i64(ret, arg1, t0); |
1074 |
tcg_temp_free_i64(t0); |
1075 |
} |
1076 |
} |
1077 |
|
1078 |
static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2, |
1079 |
int label_index)
|
1080 |
{ |
1081 |
tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
1082 |
} |
1083 |
|
1084 |
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1085 |
{ |
1086 |
tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
1087 |
} |
1088 |
|
1089 |
#ifdef TCG_TARGET_HAS_div_i64
|
1090 |
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1091 |
{ |
1092 |
tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); |
1093 |
} |
1094 |
|
1095 |
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1096 |
{ |
1097 |
tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); |
1098 |
} |
1099 |
|
1100 |
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1101 |
{ |
1102 |
tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); |
1103 |
} |
1104 |
|
1105 |
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1106 |
{ |
1107 |
tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); |
1108 |
} |
1109 |
#else
|
1110 |
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1111 |
{ |
1112 |
TCGv_i64 t0; |
1113 |
t0 = tcg_temp_new_i64(); |
1114 |
tcg_gen_sari_i64(t0, arg1, 63);
|
1115 |
tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
1116 |
tcg_temp_free_i64(t0); |
1117 |
} |
1118 |
|
1119 |
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1120 |
{ |
1121 |
TCGv_i64 t0; |
1122 |
t0 = tcg_temp_new_i64(); |
1123 |
tcg_gen_sari_i64(t0, arg1, 63);
|
1124 |
tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
1125 |
tcg_temp_free_i64(t0); |
1126 |
} |
1127 |
|
1128 |
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1129 |
{ |
1130 |
TCGv_i64 t0; |
1131 |
t0 = tcg_temp_new_i64(); |
1132 |
tcg_gen_movi_i64(t0, 0);
|
1133 |
tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
1134 |
tcg_temp_free_i64(t0); |
1135 |
} |
1136 |
|
1137 |
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1138 |
{ |
1139 |
TCGv_i64 t0; |
1140 |
t0 = tcg_temp_new_i64(); |
1141 |
tcg_gen_movi_i64(t0, 0);
|
1142 |
tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
1143 |
tcg_temp_free_i64(t0); |
1144 |
} |
1145 |
#endif
|
1146 |
|
1147 |
#endif
|
1148 |
|
1149 |
static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1150 |
{ |
1151 |
/* some cases can be optimized here */
|
1152 |
if (arg2 == 0) { |
1153 |
tcg_gen_mov_i64(ret, arg1); |
1154 |
} else {
|
1155 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1156 |
tcg_gen_add_i64(ret, arg1, t0); |
1157 |
tcg_temp_free_i64(t0); |
1158 |
} |
1159 |
} |
1160 |
|
1161 |
static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) |
1162 |
{ |
1163 |
TCGv_i64 t0 = tcg_const_i64(arg1); |
1164 |
tcg_gen_sub_i64(ret, t0, arg2); |
1165 |
tcg_temp_free_i64(t0); |
1166 |
} |
1167 |
|
1168 |
static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1169 |
{ |
1170 |
/* some cases can be optimized here */
|
1171 |
if (arg2 == 0) { |
1172 |
tcg_gen_mov_i64(ret, arg1); |
1173 |
} else {
|
1174 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1175 |
tcg_gen_sub_i64(ret, arg1, t0); |
1176 |
tcg_temp_free_i64(t0); |
1177 |
} |
1178 |
} |
1179 |
static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2, |
1180 |
int label_index)
|
1181 |
{ |
1182 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1183 |
tcg_gen_brcond_i64(cond, arg1, t0, label_index); |
1184 |
tcg_temp_free_i64(t0); |
1185 |
} |
1186 |
|
1187 |
static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1188 |
{ |
1189 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1190 |
tcg_gen_mul_i64(ret, arg1, t0); |
1191 |
tcg_temp_free_i64(t0); |
1192 |
} |
1193 |
|
1194 |
|
1195 |
/***************************************/
|
1196 |
/* optional operations */
|
1197 |
|
1198 |
static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) |
1199 |
{ |
1200 |
#ifdef TCG_TARGET_HAS_ext8s_i32
|
1201 |
tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); |
1202 |
#else
|
1203 |
tcg_gen_shli_i32(ret, arg, 24);
|
1204 |
tcg_gen_sari_i32(ret, ret, 24);
|
1205 |
#endif
|
1206 |
} |
1207 |
|
1208 |
static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) |
1209 |
{ |
1210 |
#ifdef TCG_TARGET_HAS_ext16s_i32
|
1211 |
tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); |
1212 |
#else
|
1213 |
tcg_gen_shli_i32(ret, arg, 16);
|
1214 |
tcg_gen_sari_i32(ret, ret, 16);
|
1215 |
#endif
|
1216 |
} |
1217 |
|
1218 |
static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) |
1219 |
{ |
1220 |
#ifdef TCG_TARGET_HAS_ext8u_i32
|
1221 |
tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); |
1222 |
#else
|
1223 |
tcg_gen_andi_i32(ret, arg, 0xffu);
|
1224 |
#endif
|
1225 |
} |
1226 |
|
1227 |
static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) |
1228 |
{ |
1229 |
#ifdef TCG_TARGET_HAS_ext16u_i32
|
1230 |
tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); |
1231 |
#else
|
1232 |
tcg_gen_andi_i32(ret, arg, 0xffffu);
|
1233 |
#endif
|
1234 |
} |
1235 |
|
1236 |
/* Note: we assume the two high bytes are set to zero */
|
1237 |
static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) |
1238 |
{ |
1239 |
#ifdef TCG_TARGET_HAS_bswap16_i32
|
1240 |
tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); |
1241 |
#else
|
1242 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
1243 |
|
1244 |
tcg_gen_ext8u_i32(t0, arg); |
1245 |
tcg_gen_shli_i32(t0, t0, 8);
|
1246 |
tcg_gen_shri_i32(ret, arg, 8);
|
1247 |
tcg_gen_or_i32(ret, ret, t0); |
1248 |
tcg_temp_free_i32(t0); |
1249 |
#endif
|
1250 |
} |
1251 |
|
1252 |
static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) |
1253 |
{ |
1254 |
#ifdef TCG_TARGET_HAS_bswap32_i32
|
1255 |
tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); |
1256 |
#else
|
1257 |
TCGv_i32 t0, t1; |
1258 |
t0 = tcg_temp_new_i32(); |
1259 |
t1 = tcg_temp_new_i32(); |
1260 |
|
1261 |
tcg_gen_shli_i32(t0, arg, 24);
|
1262 |
|
1263 |
tcg_gen_andi_i32(t1, arg, 0x0000ff00);
|
1264 |
tcg_gen_shli_i32(t1, t1, 8);
|
1265 |
tcg_gen_or_i32(t0, t0, t1); |
1266 |
|
1267 |
tcg_gen_shri_i32(t1, arg, 8);
|
1268 |
tcg_gen_andi_i32(t1, t1, 0x0000ff00);
|
1269 |
tcg_gen_or_i32(t0, t0, t1); |
1270 |
|
1271 |
tcg_gen_shri_i32(t1, arg, 24);
|
1272 |
tcg_gen_or_i32(ret, t0, t1); |
1273 |
tcg_temp_free_i32(t0); |
1274 |
tcg_temp_free_i32(t1); |
1275 |
#endif
|
1276 |
} |
1277 |
|
1278 |
#if TCG_TARGET_REG_BITS == 32 |
1279 |
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1280 |
{ |
1281 |
tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1282 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1283 |
} |
1284 |
|
1285 |
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1286 |
{ |
1287 |
tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1288 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1289 |
} |
1290 |
|
1291 |
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1292 |
{ |
1293 |
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1294 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1295 |
} |
1296 |
|
1297 |
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1298 |
{ |
1299 |
tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1300 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1301 |
} |
1302 |
|
1303 |
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1304 |
{ |
1305 |
tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1306 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1307 |
} |
1308 |
|
1309 |
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1310 |
{ |
1311 |
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1312 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1313 |
} |
1314 |
|
1315 |
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
1316 |
{ |
1317 |
tcg_gen_mov_i32(ret, TCGV_LOW(arg)); |
1318 |
} |
1319 |
|
1320 |
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1321 |
{ |
1322 |
tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1323 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1324 |
} |
1325 |
|
1326 |
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1327 |
{ |
1328 |
tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1329 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1330 |
} |
1331 |
|
1332 |
/* Note: we assume the six high bytes are set to zero */
|
1333 |
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
1334 |
{ |
1335 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
1336 |
tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1337 |
} |
1338 |
|
1339 |
/* Note: we assume the four high bytes are set to zero */
|
1340 |
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
1341 |
{ |
1342 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
1343 |
tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1344 |
} |
1345 |
|
1346 |
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
1347 |
{ |
1348 |
TCGv_i32 t0, t1; |
1349 |
t0 = tcg_temp_new_i32(); |
1350 |
t1 = tcg_temp_new_i32(); |
1351 |
|
1352 |
tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); |
1353 |
tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); |
1354 |
tcg_gen_mov_i32(TCGV_LOW(ret), t1); |
1355 |
tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
1356 |
tcg_temp_free_i32(t0); |
1357 |
tcg_temp_free_i32(t1); |
1358 |
} |
1359 |
#else
|
1360 |
|
1361 |
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1362 |
{ |
1363 |
#ifdef TCG_TARGET_HAS_ext8s_i64
|
1364 |
tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg); |
1365 |
#else
|
1366 |
tcg_gen_shli_i64(ret, arg, 56);
|
1367 |
tcg_gen_sari_i64(ret, ret, 56);
|
1368 |
#endif
|
1369 |
} |
1370 |
|
1371 |
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1372 |
{ |
1373 |
#ifdef TCG_TARGET_HAS_ext16s_i64
|
1374 |
tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg); |
1375 |
#else
|
1376 |
tcg_gen_shli_i64(ret, arg, 48);
|
1377 |
tcg_gen_sari_i64(ret, ret, 48);
|
1378 |
#endif
|
1379 |
} |
1380 |
|
1381 |
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1382 |
{ |
1383 |
#ifdef TCG_TARGET_HAS_ext32s_i64
|
1384 |
tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg); |
1385 |
#else
|
1386 |
tcg_gen_shli_i64(ret, arg, 32);
|
1387 |
tcg_gen_sari_i64(ret, ret, 32);
|
1388 |
#endif
|
1389 |
} |
1390 |
|
1391 |
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1392 |
{ |
1393 |
#ifdef TCG_TARGET_HAS_ext8u_i64
|
1394 |
tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg); |
1395 |
#else
|
1396 |
tcg_gen_andi_i64(ret, arg, 0xffu);
|
1397 |
#endif
|
1398 |
} |
1399 |
|
1400 |
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1401 |
{ |
1402 |
#ifdef TCG_TARGET_HAS_ext16u_i64
|
1403 |
tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg); |
1404 |
#else
|
1405 |
tcg_gen_andi_i64(ret, arg, 0xffffu);
|
1406 |
#endif
|
1407 |
} |
1408 |
|
1409 |
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1410 |
{ |
1411 |
#ifdef TCG_TARGET_HAS_ext32u_i64
|
1412 |
tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg); |
1413 |
#else
|
1414 |
tcg_gen_andi_i64(ret, arg, 0xffffffffu);
|
1415 |
#endif
|
1416 |
} |
1417 |
|
1418 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1419 |
registers. This will probably break MIPS64 targets. */
|
1420 |
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
1421 |
{ |
1422 |
tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); |
1423 |
} |
1424 |
|
1425 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1426 |
registers */
|
1427 |
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1428 |
{ |
1429 |
tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
1430 |
} |
1431 |
|
1432 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1433 |
registers */
|
1434 |
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1435 |
{ |
1436 |
tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
1437 |
} |
1438 |
|
1439 |
/* Note: we assume the six high bytes are set to zero */
|
1440 |
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
1441 |
{ |
1442 |
#ifdef TCG_TARGET_HAS_bswap16_i64
|
1443 |
tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg); |
1444 |
#else
|
1445 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1446 |
|
1447 |
tcg_gen_ext8u_i64(t0, arg); |
1448 |
tcg_gen_shli_i64(t0, t0, 8);
|
1449 |
tcg_gen_shri_i64(ret, arg, 8);
|
1450 |
tcg_gen_or_i64(ret, ret, t0); |
1451 |
tcg_temp_free_i64(t0); |
1452 |
#endif
|
1453 |
} |
1454 |
|
1455 |
/* Note: we assume the four high bytes are set to zero */
|
1456 |
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
1457 |
{ |
1458 |
#ifdef TCG_TARGET_HAS_bswap32_i64
|
1459 |
tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); |
1460 |
#else
|
1461 |
TCGv_i64 t0, t1; |
1462 |
t0 = tcg_temp_new_i64(); |
1463 |
t1 = tcg_temp_new_i64(); |
1464 |
|
1465 |
tcg_gen_shli_i64(t0, arg, 24);
|
1466 |
tcg_gen_ext32u_i64(t0, t0); |
1467 |
|
1468 |
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
1469 |
tcg_gen_shli_i64(t1, t1, 8);
|
1470 |
tcg_gen_or_i64(t0, t0, t1); |
1471 |
|
1472 |
tcg_gen_shri_i64(t1, arg, 8);
|
1473 |
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
1474 |
tcg_gen_or_i64(t0, t0, t1); |
1475 |
|
1476 |
tcg_gen_shri_i64(t1, arg, 24);
|
1477 |
tcg_gen_or_i64(ret, t0, t1); |
1478 |
tcg_temp_free_i64(t0); |
1479 |
tcg_temp_free_i64(t1); |
1480 |
#endif
|
1481 |
} |
1482 |
|
1483 |
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
1484 |
{ |
1485 |
#ifdef TCG_TARGET_HAS_bswap64_i64
|
1486 |
tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); |
1487 |
#else
|
1488 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1489 |
TCGv_i64 t1 = tcg_temp_new_i64(); |
1490 |
|
1491 |
tcg_gen_shli_i64(t0, arg, 56);
|
1492 |
|
1493 |
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
1494 |
tcg_gen_shli_i64(t1, t1, 40);
|
1495 |
tcg_gen_or_i64(t0, t0, t1); |
1496 |
|
1497 |
tcg_gen_andi_i64(t1, arg, 0x00ff0000);
|
1498 |
tcg_gen_shli_i64(t1, t1, 24);
|
1499 |
tcg_gen_or_i64(t0, t0, t1); |
1500 |
|
1501 |
tcg_gen_andi_i64(t1, arg, 0xff000000);
|
1502 |
tcg_gen_shli_i64(t1, t1, 8);
|
1503 |
tcg_gen_or_i64(t0, t0, t1); |
1504 |
|
1505 |
tcg_gen_shri_i64(t1, arg, 8);
|
1506 |
tcg_gen_andi_i64(t1, t1, 0xff000000);
|
1507 |
tcg_gen_or_i64(t0, t0, t1); |
1508 |
|
1509 |
tcg_gen_shri_i64(t1, arg, 24);
|
1510 |
tcg_gen_andi_i64(t1, t1, 0x00ff0000);
|
1511 |
tcg_gen_or_i64(t0, t0, t1); |
1512 |
|
1513 |
tcg_gen_shri_i64(t1, arg, 40);
|
1514 |
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
1515 |
tcg_gen_or_i64(t0, t0, t1); |
1516 |
|
1517 |
tcg_gen_shri_i64(t1, arg, 56);
|
1518 |
tcg_gen_or_i64(ret, t0, t1); |
1519 |
tcg_temp_free_i64(t0); |
1520 |
tcg_temp_free_i64(t1); |
1521 |
#endif
|
1522 |
} |
1523 |
|
1524 |
#endif
|
1525 |
|
1526 |
static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
1527 |
{ |
1528 |
#ifdef TCG_TARGET_HAS_neg_i32
|
1529 |
tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
1530 |
#else
|
1531 |
TCGv_i32 t0 = tcg_const_i32(0);
|
1532 |
tcg_gen_sub_i32(ret, t0, arg); |
1533 |
tcg_temp_free_i32(t0); |
1534 |
#endif
|
1535 |
} |
1536 |
|
1537 |
static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
1538 |
{ |
1539 |
#ifdef TCG_TARGET_HAS_neg_i64
|
1540 |
tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
1541 |
#else
|
1542 |
TCGv_i64 t0 = tcg_const_i64(0);
|
1543 |
tcg_gen_sub_i64(ret, t0, arg); |
1544 |
tcg_temp_free_i64(t0); |
1545 |
#endif
|
1546 |
} |
1547 |
|
1548 |
static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
1549 |
{ |
1550 |
#ifdef TCG_TARGET_HAS_not_i32
|
1551 |
tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); |
1552 |
#else
|
1553 |
tcg_gen_xori_i32(ret, arg, -1);
|
1554 |
#endif
|
1555 |
} |
1556 |
|
1557 |
static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) |
1558 |
{ |
1559 |
#ifdef TCG_TARGET_HAS_not_i64
|
1560 |
tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); |
1561 |
#else
|
1562 |
tcg_gen_xori_i64(ret, arg, -1);
|
1563 |
#endif
|
1564 |
} |
1565 |
|
1566 |
static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
1567 |
{ |
1568 |
tcg_gen_op1_i32(INDEX_op_discard, arg); |
1569 |
} |
1570 |
|
1571 |
#if TCG_TARGET_REG_BITS == 32 |
1572 |
static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
1573 |
{ |
1574 |
tcg_gen_discard_i32(TCGV_LOW(arg)); |
1575 |
tcg_gen_discard_i32(TCGV_HIGH(arg)); |
1576 |
} |
1577 |
#else
|
1578 |
static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
1579 |
{ |
1580 |
tcg_gen_op1_i64(INDEX_op_discard, arg); |
1581 |
} |
1582 |
#endif
|
1583 |
|
1584 |
static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) |
1585 |
{ |
1586 |
#if TCG_TARGET_REG_BITS == 32 |
1587 |
tcg_gen_mov_i32(TCGV_LOW(dest), low); |
1588 |
tcg_gen_mov_i32(TCGV_HIGH(dest), high); |
1589 |
#else
|
1590 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
1591 |
/* This extension is only needed for type correctness.
|
1592 |
We may be able to do better given target specific information. */
|
1593 |
tcg_gen_extu_i32_i64(tmp, high); |
1594 |
tcg_gen_shli_i64(tmp, tmp, 32);
|
1595 |
tcg_gen_extu_i32_i64(dest, low); |
1596 |
tcg_gen_or_i64(dest, dest, tmp); |
1597 |
tcg_temp_free_i64(tmp); |
1598 |
#endif
|
1599 |
} |
1600 |
|
1601 |
static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high) |
1602 |
{ |
1603 |
#if TCG_TARGET_REG_BITS == 32 |
1604 |
tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high)); |
1605 |
#else
|
1606 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
1607 |
tcg_gen_ext32u_i64(dest, low); |
1608 |
tcg_gen_shli_i64(tmp, high, 32);
|
1609 |
tcg_gen_or_i64(dest, dest, tmp); |
1610 |
tcg_temp_free_i64(tmp); |
1611 |
#endif
|
1612 |
} |
1613 |
|
1614 |
static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1615 |
{ |
1616 |
TCGv_i32 t0; |
1617 |
t0 = tcg_temp_new_i32(); |
1618 |
tcg_gen_not_i32(t0, arg2); |
1619 |
tcg_gen_and_i32(ret, arg1, t0); |
1620 |
tcg_temp_free_i32(t0); |
1621 |
} |
1622 |
|
1623 |
static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1624 |
{ |
1625 |
TCGv_i64 t0; |
1626 |
t0 = tcg_temp_new_i64(); |
1627 |
tcg_gen_not_i64(t0, arg2); |
1628 |
tcg_gen_and_i64(ret, arg1, t0); |
1629 |
tcg_temp_free_i64(t0); |
1630 |
} |
1631 |
|
1632 |
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1633 |
{ |
1634 |
tcg_gen_xor_i32(ret, arg1, arg2); |
1635 |
tcg_gen_not_i32(ret, ret); |
1636 |
} |
1637 |
|
1638 |
static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1639 |
{ |
1640 |
tcg_gen_xor_i64(ret, arg1, arg2); |
1641 |
tcg_gen_not_i64(ret, ret); |
1642 |
} |
1643 |
|
1644 |
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1645 |
{ |
1646 |
tcg_gen_and_i32(ret, arg1, arg2); |
1647 |
tcg_gen_not_i32(ret, ret); |
1648 |
} |
1649 |
|
1650 |
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1651 |
{ |
1652 |
tcg_gen_and_i64(ret, arg1, arg2); |
1653 |
tcg_gen_not_i64(ret, ret); |
1654 |
} |
1655 |
|
1656 |
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1657 |
{ |
1658 |
tcg_gen_or_i32(ret, arg1, arg2); |
1659 |
tcg_gen_not_i32(ret, ret); |
1660 |
} |
1661 |
|
1662 |
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1663 |
{ |
1664 |
tcg_gen_or_i64(ret, arg1, arg2); |
1665 |
tcg_gen_not_i64(ret, ret); |
1666 |
} |
1667 |
|
1668 |
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1669 |
{ |
1670 |
TCGv_i32 t0; |
1671 |
t0 = tcg_temp_new_i32(); |
1672 |
tcg_gen_not_i32(t0, arg2); |
1673 |
tcg_gen_or_i32(ret, arg1, t0); |
1674 |
tcg_temp_free_i32(t0); |
1675 |
} |
1676 |
|
1677 |
static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1678 |
{ |
1679 |
TCGv_i64 t0; |
1680 |
t0 = tcg_temp_new_i64(); |
1681 |
tcg_gen_not_i64(t0, arg2); |
1682 |
tcg_gen_or_i64(ret, arg1, t0); |
1683 |
tcg_temp_free_i64(t0); |
1684 |
} |
1685 |
|
1686 |
static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1687 |
{ |
1688 |
#ifdef TCG_TARGET_HAS_rot_i32
|
1689 |
tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); |
1690 |
#else
|
1691 |
TCGv_i32 t0, t1; |
1692 |
|
1693 |
t0 = tcg_temp_new_i32(); |
1694 |
t1 = tcg_temp_new_i32(); |
1695 |
tcg_gen_shl_i32(t0, arg1, arg2); |
1696 |
tcg_gen_subfi_i32(t1, 32, arg2);
|
1697 |
tcg_gen_shr_i32(t1, arg1, t1); |
1698 |
tcg_gen_or_i32(ret, t0, t1); |
1699 |
tcg_temp_free_i32(t0); |
1700 |
tcg_temp_free_i32(t1); |
1701 |
#endif
|
1702 |
} |
1703 |
|
1704 |
static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1705 |
{ |
1706 |
#ifdef TCG_TARGET_HAS_rot_i64
|
1707 |
tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); |
1708 |
#else
|
1709 |
TCGv_i64 t0, t1; |
1710 |
|
1711 |
t0 = tcg_temp_new_i64(); |
1712 |
t1 = tcg_temp_new_i64(); |
1713 |
tcg_gen_shl_i64(t0, arg1, arg2); |
1714 |
tcg_gen_subfi_i64(t1, 64, arg2);
|
1715 |
tcg_gen_shr_i64(t1, arg1, t1); |
1716 |
tcg_gen_or_i64(ret, t0, t1); |
1717 |
tcg_temp_free_i64(t0); |
1718 |
tcg_temp_free_i64(t1); |
1719 |
#endif
|
1720 |
} |
1721 |
|
1722 |
static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
1723 |
{ |
1724 |
/* some cases can be optimized here */
|
1725 |
if (arg2 == 0) { |
1726 |
tcg_gen_mov_i32(ret, arg1); |
1727 |
} else {
|
1728 |
#ifdef TCG_TARGET_HAS_rot_i32
|
1729 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
1730 |
tcg_gen_rotl_i32(ret, arg1, t0); |
1731 |
tcg_temp_free_i32(t0); |
1732 |
#else
|
1733 |
TCGv_i32 t0, t1; |
1734 |
t0 = tcg_temp_new_i32(); |
1735 |
t1 = tcg_temp_new_i32(); |
1736 |
tcg_gen_shli_i32(t0, arg1, arg2); |
1737 |
tcg_gen_shri_i32(t1, arg1, 32 - arg2);
|
1738 |
tcg_gen_or_i32(ret, t0, t1); |
1739 |
tcg_temp_free_i32(t0); |
1740 |
tcg_temp_free_i32(t1); |
1741 |
#endif
|
1742 |
} |
1743 |
} |
1744 |
|
1745 |
static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1746 |
{ |
1747 |
/* some cases can be optimized here */
|
1748 |
if (arg2 == 0) { |
1749 |
tcg_gen_mov_i64(ret, arg1); |
1750 |
} else {
|
1751 |
#ifdef TCG_TARGET_HAS_rot_i64
|
1752 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1753 |
tcg_gen_rotl_i64(ret, arg1, t0); |
1754 |
tcg_temp_free_i64(t0); |
1755 |
#else
|
1756 |
TCGv_i64 t0, t1; |
1757 |
t0 = tcg_temp_new_i64(); |
1758 |
t1 = tcg_temp_new_i64(); |
1759 |
tcg_gen_shli_i64(t0, arg1, arg2); |
1760 |
tcg_gen_shri_i64(t1, arg1, 64 - arg2);
|
1761 |
tcg_gen_or_i64(ret, t0, t1); |
1762 |
tcg_temp_free_i64(t0); |
1763 |
tcg_temp_free_i64(t1); |
1764 |
#endif
|
1765 |
} |
1766 |
} |
1767 |
|
1768 |
static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1769 |
{ |
1770 |
#ifdef TCG_TARGET_HAS_rot_i32
|
1771 |
tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); |
1772 |
#else
|
1773 |
TCGv_i32 t0, t1; |
1774 |
|
1775 |
t0 = tcg_temp_new_i32(); |
1776 |
t1 = tcg_temp_new_i32(); |
1777 |
tcg_gen_shr_i32(t0, arg1, arg2); |
1778 |
tcg_gen_subfi_i32(t1, 32, arg2);
|
1779 |
tcg_gen_shl_i32(t1, arg1, t1); |
1780 |
tcg_gen_or_i32(ret, t0, t1); |
1781 |
tcg_temp_free_i32(t0); |
1782 |
tcg_temp_free_i32(t1); |
1783 |
#endif
|
1784 |
} |
1785 |
|
1786 |
static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1787 |
{ |
1788 |
#ifdef TCG_TARGET_HAS_rot_i64
|
1789 |
tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); |
1790 |
#else
|
1791 |
TCGv_i64 t0, t1; |
1792 |
|
1793 |
t0 = tcg_temp_new_i64(); |
1794 |
t1 = tcg_temp_new_i64(); |
1795 |
tcg_gen_shr_i64(t0, arg1, arg2); |
1796 |
tcg_gen_subfi_i64(t1, 64, arg2);
|
1797 |
tcg_gen_shl_i64(t1, arg1, t1); |
1798 |
tcg_gen_or_i64(ret, t0, t1); |
1799 |
tcg_temp_free_i64(t0); |
1800 |
tcg_temp_free_i64(t1); |
1801 |
#endif
|
1802 |
} |
1803 |
|
1804 |
static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
1805 |
{ |
1806 |
/* some cases can be optimized here */
|
1807 |
if (arg2 == 0) { |
1808 |
tcg_gen_mov_i32(ret, arg1); |
1809 |
} else {
|
1810 |
tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
|
1811 |
} |
1812 |
} |
1813 |
|
1814 |
static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1815 |
{ |
1816 |
/* some cases can be optimized here */
|
1817 |
if (arg2 == 0) { |
1818 |
tcg_gen_mov_i64(ret, arg1); |
1819 |
} else {
|
1820 |
tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
|
1821 |
} |
1822 |
} |
1823 |
|
1824 |
static inline void tcg_gen_setcond_i32(int cond, TCGv_i32 ret, |
1825 |
TCGv_i32 arg1, TCGv_i32 arg2) |
1826 |
{ |
1827 |
tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); |
1828 |
} |
1829 |
|
1830 |
static inline void tcg_gen_setcondi_i32(int cond, TCGv_i32 ret, TCGv_i32 arg1, |
1831 |
int32_t arg2) |
1832 |
{ |
1833 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
1834 |
tcg_gen_setcond_i32(cond, ret, arg1, t0); |
1835 |
tcg_temp_free_i32(t0); |
1836 |
} |
1837 |
|
1838 |
static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret, |
1839 |
TCGv_i64 arg1, TCGv_i64 arg2) |
1840 |
{ |
1841 |
#if TCG_TARGET_REG_BITS == 64 |
1842 |
tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); |
1843 |
#else
|
1844 |
tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), |
1845 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), |
1846 |
TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); |
1847 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1848 |
#endif
|
1849 |
} |
1850 |
|
1851 |
static inline void tcg_gen_setcondi_i64(int cond, TCGv_i64 ret, TCGv_i64 arg1, |
1852 |
int64_t arg2) |
1853 |
{ |
1854 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1855 |
tcg_gen_setcond_i64(cond, ret, arg1, t0); |
1856 |
tcg_temp_free_i64(t0); |
1857 |
} |
1858 |
|
1859 |
/***************************************/
|
1860 |
/* QEMU specific operations. Their type depend on the QEMU CPU
|
1861 |
type. */
|
1862 |
#ifndef TARGET_LONG_BITS
|
1863 |
#error must include QEMU headers
|
1864 |
#endif
|
1865 |
|
1866 |
#if TARGET_LONG_BITS == 32 |
1867 |
#define TCGv TCGv_i32
|
1868 |
#define tcg_temp_new() tcg_temp_new_i32()
|
1869 |
#define tcg_global_reg_new tcg_global_reg_new_i32
|
1870 |
#define tcg_global_mem_new tcg_global_mem_new_i32
|
1871 |
#define tcg_temp_local_new() tcg_temp_local_new_i32()
|
1872 |
#define tcg_temp_free tcg_temp_free_i32
|
1873 |
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
|
1874 |
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
|
1875 |
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
|
1876 |
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
|
1877 |
#else
|
1878 |
#define TCGv TCGv_i64
|
1879 |
#define tcg_temp_new() tcg_temp_new_i64()
|
1880 |
#define tcg_global_reg_new tcg_global_reg_new_i64
|
1881 |
#define tcg_global_mem_new tcg_global_mem_new_i64
|
1882 |
#define tcg_temp_local_new() tcg_temp_local_new_i64()
|
1883 |
#define tcg_temp_free tcg_temp_free_i64
|
1884 |
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
|
1885 |
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
|
1886 |
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
|
1887 |
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
|
1888 |
#endif
|
1889 |
|
1890 |
/* debug info: write the PC of the corresponding QEMU CPU instruction */
|
1891 |
static inline void tcg_gen_debug_insn_start(uint64_t pc) |
1892 |
{ |
1893 |
/* XXX: must really use a 32 bit size for TCGArg in all cases */
|
1894 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
1895 |
tcg_gen_op2ii(INDEX_op_debug_insn_start, |
1896 |
(uint32_t)(pc), (uint32_t)(pc >> 32));
|
1897 |
#else
|
1898 |
tcg_gen_op1i(INDEX_op_debug_insn_start, pc); |
1899 |
#endif
|
1900 |
} |
1901 |
|
1902 |
static inline void tcg_gen_exit_tb(tcg_target_long val) |
1903 |
{ |
1904 |
tcg_gen_op1i(INDEX_op_exit_tb, val); |
1905 |
} |
1906 |
|
1907 |
static inline void tcg_gen_goto_tb(int idx) |
1908 |
{ |
1909 |
tcg_gen_op1i(INDEX_op_goto_tb, idx); |
1910 |
} |
1911 |
|
1912 |
#if TCG_TARGET_REG_BITS == 32 |
1913 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
1914 |
{ |
1915 |
#if TARGET_LONG_BITS == 32 |
1916 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
1917 |
#else
|
1918 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr), |
1919 |
TCGV_HIGH(addr), mem_index); |
1920 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1921 |
#endif
|
1922 |
} |
1923 |
|
1924 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
1925 |
{ |
1926 |
#if TARGET_LONG_BITS == 32 |
1927 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
1928 |
#else
|
1929 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr), |
1930 |
TCGV_HIGH(addr), mem_index); |
1931 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1932 |
#endif
|
1933 |
} |
1934 |
|
1935 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
1936 |
{ |
1937 |
#if TARGET_LONG_BITS == 32 |
1938 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
1939 |
#else
|
1940 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr), |
1941 |
TCGV_HIGH(addr), mem_index); |
1942 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1943 |
#endif
|
1944 |
} |
1945 |
|
1946 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
1947 |
{ |
1948 |
#if TARGET_LONG_BITS == 32 |
1949 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
1950 |
#else
|
1951 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr), |
1952 |
TCGV_HIGH(addr), mem_index); |
1953 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1954 |
#endif
|
1955 |
} |
1956 |
|
1957 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
1958 |
{ |
1959 |
#if TARGET_LONG_BITS == 32 |
1960 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
1961 |
#else
|
1962 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
1963 |
TCGV_HIGH(addr), mem_index); |
1964 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1965 |
#endif
|
1966 |
} |
1967 |
|
1968 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
1969 |
{ |
1970 |
#if TARGET_LONG_BITS == 32 |
1971 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
1972 |
#else
|
1973 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
1974 |
TCGV_HIGH(addr), mem_index); |
1975 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1976 |
#endif
|
1977 |
} |
1978 |
|
1979 |
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
1980 |
{ |
1981 |
#if TARGET_LONG_BITS == 32 |
1982 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index); |
1983 |
#else
|
1984 |
tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), |
1985 |
TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
1986 |
#endif
|
1987 |
} |
1988 |
|
1989 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
1990 |
{ |
1991 |
#if TARGET_LONG_BITS == 32 |
1992 |
tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index); |
1993 |
#else
|
1994 |
tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr), |
1995 |
TCGV_HIGH(addr), mem_index); |
1996 |
#endif
|
1997 |
} |
1998 |
|
1999 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
2000 |
{ |
2001 |
#if TARGET_LONG_BITS == 32 |
2002 |
tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index); |
2003 |
#else
|
2004 |
tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr), |
2005 |
TCGV_HIGH(addr), mem_index); |
2006 |
#endif
|
2007 |
} |
2008 |
|
2009 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
2010 |
{ |
2011 |
#if TARGET_LONG_BITS == 32 |
2012 |
tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index); |
2013 |
#else
|
2014 |
tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr), |
2015 |
TCGV_HIGH(addr), mem_index); |
2016 |
#endif
|
2017 |
} |
2018 |
|
2019 |
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
2020 |
{ |
2021 |
#if TARGET_LONG_BITS == 32 |
2022 |
tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr, |
2023 |
mem_index); |
2024 |
#else
|
2025 |
tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), |
2026 |
TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
2027 |
#endif
|
2028 |
} |
2029 |
|
2030 |
#define tcg_gen_ld_ptr tcg_gen_ld_i32
|
2031 |
#define tcg_gen_discard_ptr tcg_gen_discard_i32
|
2032 |
|
2033 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
2034 |
|
2035 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
2036 |
{ |
2037 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
2038 |
} |
2039 |
|
2040 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
2041 |
{ |
2042 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
2043 |
} |
2044 |
|
2045 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
2046 |
{ |
2047 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
2048 |
} |
2049 |
|
2050 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
2051 |
{ |
2052 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
2053 |
} |
2054 |
|
2055 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
2056 |
{ |
2057 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
2058 |
} |
2059 |
|
2060 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
2061 |
{ |
2062 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
2063 |
} |
2064 |
|
2065 |
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
2066 |
{ |
2067 |
tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index); |
2068 |
} |
2069 |
|
2070 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
2071 |
{ |
2072 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index); |
2073 |
} |
2074 |
|
2075 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
2076 |
{ |
2077 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index); |
2078 |
} |
2079 |
|
2080 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
2081 |
{ |
2082 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index); |
2083 |
} |
2084 |
|
2085 |
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
2086 |
{ |
2087 |
tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index); |
2088 |
} |
2089 |
|
2090 |
#define tcg_gen_ld_ptr tcg_gen_ld_i64
|
2091 |
#define tcg_gen_discard_ptr tcg_gen_discard_i64
|
2092 |
|
2093 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |
2094 |
|
2095 |
#if TARGET_LONG_BITS == 64 |
2096 |
#define TCG_TYPE_TL TCG_TYPE_I64
|
2097 |
#define tcg_gen_movi_tl tcg_gen_movi_i64
|
2098 |
#define tcg_gen_mov_tl tcg_gen_mov_i64
|
2099 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
|
2100 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
|
2101 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
|
2102 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
|
2103 |
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
|
2104 |
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
|
2105 |
#define tcg_gen_ld_tl tcg_gen_ld_i64
|
2106 |
#define tcg_gen_st8_tl tcg_gen_st8_i64
|
2107 |
#define tcg_gen_st16_tl tcg_gen_st16_i64
|
2108 |
#define tcg_gen_st32_tl tcg_gen_st32_i64
|
2109 |
#define tcg_gen_st_tl tcg_gen_st_i64
|
2110 |
#define tcg_gen_add_tl tcg_gen_add_i64
|
2111 |
#define tcg_gen_addi_tl tcg_gen_addi_i64
|
2112 |
#define tcg_gen_sub_tl tcg_gen_sub_i64
|
2113 |
#define tcg_gen_neg_tl tcg_gen_neg_i64
|
2114 |
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
|
2115 |
#define tcg_gen_subi_tl tcg_gen_subi_i64
|
2116 |
#define tcg_gen_and_tl tcg_gen_and_i64
|
2117 |
#define tcg_gen_andi_tl tcg_gen_andi_i64
|
2118 |
#define tcg_gen_or_tl tcg_gen_or_i64
|
2119 |
#define tcg_gen_ori_tl tcg_gen_ori_i64
|
2120 |
#define tcg_gen_xor_tl tcg_gen_xor_i64
|
2121 |
#define tcg_gen_xori_tl tcg_gen_xori_i64
|
2122 |
#define tcg_gen_not_tl tcg_gen_not_i64
|
2123 |
#define tcg_gen_shl_tl tcg_gen_shl_i64
|
2124 |
#define tcg_gen_shli_tl tcg_gen_shli_i64
|
2125 |
#define tcg_gen_shr_tl tcg_gen_shr_i64
|
2126 |
#define tcg_gen_shri_tl tcg_gen_shri_i64
|
2127 |
#define tcg_gen_sar_tl tcg_gen_sar_i64
|
2128 |
#define tcg_gen_sari_tl tcg_gen_sari_i64
|
2129 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
|
2130 |
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
|
2131 |
#define tcg_gen_setcond_tl tcg_gen_setcond_i64
|
2132 |
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
|
2133 |
#define tcg_gen_mul_tl tcg_gen_mul_i64
|
2134 |
#define tcg_gen_muli_tl tcg_gen_muli_i64
|
2135 |
#define tcg_gen_div_tl tcg_gen_div_i64
|
2136 |
#define tcg_gen_rem_tl tcg_gen_rem_i64
|
2137 |
#define tcg_gen_divu_tl tcg_gen_divu_i64
|
2138 |
#define tcg_gen_remu_tl tcg_gen_remu_i64
|
2139 |
#define tcg_gen_discard_tl tcg_gen_discard_i64
|
2140 |
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
|
2141 |
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
|
2142 |
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
|
2143 |
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
|
2144 |
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
|
2145 |
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
|
2146 |
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
|
2147 |
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
|
2148 |
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
|
2149 |
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
|
2150 |
#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
|
2151 |
#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
|
2152 |
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
|
2153 |
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
|
2154 |
#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
|
2155 |
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
|
2156 |
#define tcg_gen_andc_tl tcg_gen_andc_i64
|
2157 |
#define tcg_gen_eqv_tl tcg_gen_eqv_i64
|
2158 |
#define tcg_gen_nand_tl tcg_gen_nand_i64
|
2159 |
#define tcg_gen_nor_tl tcg_gen_nor_i64
|
2160 |
#define tcg_gen_orc_tl tcg_gen_orc_i64
|
2161 |
#define tcg_gen_rotl_tl tcg_gen_rotl_i64
|
2162 |
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
|
2163 |
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
|
2164 |
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
|
2165 |
#define tcg_const_tl tcg_const_i64
|
2166 |
#define tcg_const_local_tl tcg_const_local_i64
|
2167 |
#else
|
2168 |
#define TCG_TYPE_TL TCG_TYPE_I32
|
2169 |
#define tcg_gen_movi_tl tcg_gen_movi_i32
|
2170 |
#define tcg_gen_mov_tl tcg_gen_mov_i32
|
2171 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
|
2172 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
|
2173 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
|
2174 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
|
2175 |
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
|
2176 |
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
|
2177 |
#define tcg_gen_ld_tl tcg_gen_ld_i32
|
2178 |
#define tcg_gen_st8_tl tcg_gen_st8_i32
|
2179 |
#define tcg_gen_st16_tl tcg_gen_st16_i32
|
2180 |
#define tcg_gen_st32_tl tcg_gen_st_i32
|
2181 |
#define tcg_gen_st_tl tcg_gen_st_i32
|
2182 |
#define tcg_gen_add_tl tcg_gen_add_i32
|
2183 |
#define tcg_gen_addi_tl tcg_gen_addi_i32
|
2184 |
#define tcg_gen_sub_tl tcg_gen_sub_i32
|
2185 |
#define tcg_gen_neg_tl tcg_gen_neg_i32
|
2186 |
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
|
2187 |
#define tcg_gen_subi_tl tcg_gen_subi_i32
|
2188 |
#define tcg_gen_and_tl tcg_gen_and_i32
|
2189 |
#define tcg_gen_andi_tl tcg_gen_andi_i32
|
2190 |
#define tcg_gen_or_tl tcg_gen_or_i32
|
2191 |
#define tcg_gen_ori_tl tcg_gen_ori_i32
|
2192 |
#define tcg_gen_xor_tl tcg_gen_xor_i32
|
2193 |
#define tcg_gen_xori_tl tcg_gen_xori_i32
|
2194 |
#define tcg_gen_not_tl tcg_gen_not_i32
|
2195 |
#define tcg_gen_shl_tl tcg_gen_shl_i32
|
2196 |
#define tcg_gen_shli_tl tcg_gen_shli_i32
|
2197 |
#define tcg_gen_shr_tl tcg_gen_shr_i32
|
2198 |
#define tcg_gen_shri_tl tcg_gen_shri_i32
|
2199 |
#define tcg_gen_sar_tl tcg_gen_sar_i32
|
2200 |
#define tcg_gen_sari_tl tcg_gen_sari_i32
|
2201 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
|
2202 |
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
|
2203 |
#define tcg_gen_setcond_tl tcg_gen_setcond_i32
|
2204 |
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
|
2205 |
#define tcg_gen_mul_tl tcg_gen_mul_i32
|
2206 |
#define tcg_gen_muli_tl tcg_gen_muli_i32
|
2207 |
#define tcg_gen_div_tl tcg_gen_div_i32
|
2208 |
#define tcg_gen_rem_tl tcg_gen_rem_i32
|
2209 |
#define tcg_gen_divu_tl tcg_gen_divu_i32
|
2210 |
#define tcg_gen_remu_tl tcg_gen_remu_i32
|
2211 |
#define tcg_gen_discard_tl tcg_gen_discard_i32
|
2212 |
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
|
2213 |
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
|
2214 |
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
|
2215 |
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
|
2216 |
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
|
2217 |
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
|
2218 |
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
|
2219 |
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
|
2220 |
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
|
2221 |
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
|
2222 |
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
|
2223 |
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
|
2224 |
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
|
2225 |
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
|
2226 |
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
|
2227 |
#define tcg_gen_andc_tl tcg_gen_andc_i32
|
2228 |
#define tcg_gen_eqv_tl tcg_gen_eqv_i32
|
2229 |
#define tcg_gen_nand_tl tcg_gen_nand_i32
|
2230 |
#define tcg_gen_nor_tl tcg_gen_nor_i32
|
2231 |
#define tcg_gen_orc_tl tcg_gen_orc_i32
|
2232 |
#define tcg_gen_rotl_tl tcg_gen_rotl_i32
|
2233 |
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
|
2234 |
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
|
2235 |
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
|
2236 |
#define tcg_const_tl tcg_const_i32
|
2237 |
#define tcg_const_local_tl tcg_const_local_i32
|
2238 |
#endif
|
2239 |
|
2240 |
#if TCG_TARGET_REG_BITS == 32 |
2241 |
#define tcg_gen_add_ptr tcg_gen_add_i32
|
2242 |
#define tcg_gen_addi_ptr tcg_gen_addi_i32
|
2243 |
#define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
|
2244 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
2245 |
#define tcg_gen_add_ptr tcg_gen_add_i64
|
2246 |
#define tcg_gen_addi_ptr tcg_gen_addi_i64
|
2247 |
#define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
|
2248 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |