root / target-alpha / translate.c @ ae8ecd42
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/*
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* Alpha emulation cpu translation for qemu.
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdint.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "disas.h" |
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#include "host-utils.h" |
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#include "helper.h" |
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#include "tcg-op.h" |
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#include "qemu-common.h" |
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#define DO_SINGLE_STEP
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#define GENERATE_NOP
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#define ALPHA_DEBUG_DISAS
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#define DO_TB_FLUSH
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typedef struct DisasContext DisasContext; |
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struct DisasContext {
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uint64_t pc; |
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int mem_idx;
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#if !defined (CONFIG_USER_ONLY)
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int pal_mode;
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#endif
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uint32_t amask; |
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}; |
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/* global register indexes */
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static TCGv cpu_env;
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static TCGv cpu_ir[31]; |
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static TCGv cpu_pc;
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/* dyngen register indexes */
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static TCGv cpu_T[3]; |
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/* register names */
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static char cpu_reg_names[5*31]; |
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#include "gen-icount.h" |
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static void alpha_translate_init(void) |
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{ |
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int i;
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char *p;
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static int done_init = 0; |
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if (done_init)
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return;
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cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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cpu_T[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, t0), "T0");
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cpu_T[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, t1), "T1");
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cpu_T[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, t2), "T2");
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#else
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cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG1, "T0"); |
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cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG2, "T1"); |
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cpu_T[2] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG3, "T2"); |
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#endif
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p = cpu_reg_names; |
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for (i = 0; i < 31; i++) { |
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sprintf(p, "ir%d", i);
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cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
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offsetof(CPUState, ir[i]), p); |
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p += 4;
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} |
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cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
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offsetof(CPUState, pc), "pc");
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/* register helpers */
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#undef DEF_HELPER
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#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); |
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#include "helper.h" |
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done_init = 1;
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} |
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static always_inline void gen_op_nop (void) |
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{ |
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#if defined(GENERATE_NOP)
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gen_op_no_op(); |
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#endif
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} |
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#define GEN32(func, NAME) \
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static GenOpFunc *NAME ## _table [32] = { \ |
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ |
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NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ |
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NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ |
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NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ |
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}; \ |
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static always_inline void func (int n) \ |
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{ \ |
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NAME ## _table[n](); \ |
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} |
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/* IR moves */
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/* Special hacks for ir31 */
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#define gen_op_cmov_ir31 gen_op_nop
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GEN32(gen_op_cmov_ir, gen_op_cmov_ir); |
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/* FIR moves */
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/* Special hacks for fir31 */
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#define gen_op_load_FT0_fir31 gen_op_reset_FT0
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#define gen_op_load_FT1_fir31 gen_op_reset_FT1
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#define gen_op_load_FT2_fir31 gen_op_reset_FT2
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#define gen_op_store_FT0_fir31 gen_op_nop
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#define gen_op_store_FT1_fir31 gen_op_nop
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#define gen_op_store_FT2_fir31 gen_op_nop
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#define gen_op_cmov_fir31 gen_op_nop
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GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir); |
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GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir); |
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GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir); |
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GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir); |
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GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir); |
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GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir); |
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GEN32(gen_op_cmov_fir, gen_op_cmov_fir); |
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static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn) |
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{ |
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switch (Tn) {
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case 0: |
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gen_op_load_FT0_fir(firn); |
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break;
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case 1: |
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gen_op_load_FT1_fir(firn); |
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break;
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case 2: |
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gen_op_load_FT2_fir(firn); |
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break;
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} |
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} |
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static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn) |
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{ |
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switch (Tn) {
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case 0: |
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gen_op_store_FT0_fir(firn); |
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break;
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case 1: |
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gen_op_store_FT1_fir(firn); |
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break;
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case 2: |
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gen_op_store_FT2_fir(firn); |
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break;
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} |
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} |
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/* Memory moves */
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#if defined(CONFIG_USER_ONLY)
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#define OP_LD_TABLE(width) \
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static GenOpFunc *gen_op_ld##width[] = { \ |
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&gen_op_ld##width##_raw, \ |
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} |
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#define OP_ST_TABLE(width) \
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static GenOpFunc *gen_op_st##width[] = { \ |
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&gen_op_st##width##_raw, \ |
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} |
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#else
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#define OP_LD_TABLE(width) \
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static GenOpFunc *gen_op_ld##width[] = { \ |
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&gen_op_ld##width##_kernel, \ |
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&gen_op_ld##width##_executive, \ |
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&gen_op_ld##width##_supervisor, \ |
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&gen_op_ld##width##_user, \ |
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} |
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#define OP_ST_TABLE(width) \
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static GenOpFunc *gen_op_st##width[] = { \ |
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&gen_op_st##width##_kernel, \ |
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&gen_op_st##width##_executive, \ |
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&gen_op_st##width##_supervisor, \ |
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&gen_op_st##width##_user, \ |
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} |
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#endif
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#define GEN_LD(width) \
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OP_LD_TABLE(width); \ |
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static always_inline void gen_ld##width (DisasContext *ctx) \ |
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{ \ |
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(*gen_op_ld##width[ctx->mem_idx])(); \ |
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} |
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#define GEN_ST(width) \
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OP_ST_TABLE(width); \ |
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static always_inline void gen_st##width (DisasContext *ctx) \ |
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{ \ |
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(*gen_op_st##width[ctx->mem_idx])(); \ |
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} |
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GEN_LD(bu); |
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GEN_ST(b); |
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GEN_LD(wu); |
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GEN_ST(w); |
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GEN_LD(l); |
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GEN_ST(l); |
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GEN_LD(q); |
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GEN_ST(q); |
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GEN_LD(q_u); |
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GEN_ST(q_u); |
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GEN_LD(l_l); |
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GEN_ST(l_c); |
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GEN_LD(q_l); |
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GEN_ST(q_c); |
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#if 0 /* currently unused */
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GEN_LD(f);
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GEN_ST(f);
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GEN_LD(g);
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GEN_ST(g);
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#endif /* 0 */
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GEN_LD(s); |
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GEN_ST(s); |
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GEN_LD(t); |
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GEN_ST(t); |
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static always_inline void _gen_op_bcond (DisasContext *ctx) |
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{ |
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#if 0 // Qemu does not know how to do this...
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gen_op_bcond(ctx->pc);
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#else
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gen_op_bcond(ctx->pc >> 32, ctx->pc);
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#endif
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} |
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static always_inline void gen_excp (DisasContext *ctx, |
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int exception, int error_code) |
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{ |
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tcg_gen_movi_i64(cpu_pc, ctx->pc); |
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gen_op_excp(exception, error_code); |
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} |
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static always_inline void gen_invalid (DisasContext *ctx) |
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{ |
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gen_excp(ctx, EXCP_OPCDEC, 0);
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} |
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static always_inline void gen_load_mem (DisasContext *ctx, |
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void (*gen_load_op)(DisasContext *ctx),
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int ra, int rb, int32_t disp16, |
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int clear)
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{ |
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if (ra == 31 && disp16 == 0) { |
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/* UNOP */
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gen_op_nop(); |
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} else {
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if (rb != 31) |
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tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
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else
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tcg_gen_movi_i64(cpu_T[0], disp16);
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if (clear)
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tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7); |
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(*gen_load_op)(ctx); |
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if (ra != 31) |
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tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
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} |
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} |
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static always_inline void gen_store_mem (DisasContext *ctx, |
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void (*gen_store_op)(DisasContext *ctx),
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int ra, int rb, int32_t disp16, |
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int clear)
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{ |
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if (rb != 31) |
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tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
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else
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tcg_gen_movi_i64(cpu_T[0], disp16);
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if (clear)
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tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7); |
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if (ra != 31) |
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tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
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else
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tcg_gen_movi_i64(cpu_T[1], 0); |
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(*gen_store_op)(ctx); |
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} |
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static always_inline void gen_load_fmem (DisasContext *ctx, |
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void (*gen_load_fop)(DisasContext *ctx),
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int ra, int rb, int32_t disp16) |
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{ |
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if (rb != 31) |
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tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
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else
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tcg_gen_movi_i64(cpu_T[0], disp16);
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(*gen_load_fop)(ctx); |
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gen_store_fir(ctx, ra, 1);
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} |
317 |
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static always_inline void gen_store_fmem (DisasContext *ctx, |
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void (*gen_store_fop)(DisasContext *ctx),
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int ra, int rb, int32_t disp16) |
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{ |
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if (rb != 31) |
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tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
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else
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tcg_gen_movi_i64(cpu_T[0], disp16);
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gen_load_fir(ctx, ra, 1);
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(*gen_store_fop)(ctx); |
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} |
329 |
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static always_inline void gen_bcond (DisasContext *ctx, |
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void (*gen_test_op)(void), |
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int ra, int32_t disp16)
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{ |
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tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2)); |
335 |
if (ra != 31) |
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tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
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else
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tcg_gen_movi_i64(cpu_T[0], 0); |
339 |
(*gen_test_op)(); |
340 |
_gen_op_bcond(ctx); |
341 |
} |
342 |
|
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static always_inline void gen_fbcond (DisasContext *ctx, |
344 |
void (*gen_test_op)(void), |
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int ra, int32_t disp16)
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{ |
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tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2)); |
348 |
gen_load_fir(ctx, ra, 0);
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(*gen_test_op)(); |
350 |
_gen_op_bcond(ctx); |
351 |
} |
352 |
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static always_inline void gen_arith3 (DisasContext *ctx, |
354 |
void (*gen_arith_op)(void), |
355 |
int ra, int rb, int rc, |
356 |
int islit, uint8_t lit)
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{ |
358 |
if (ra != 31) |
359 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
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360 |
else
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tcg_gen_movi_i64(cpu_T[0], 0); |
362 |
if (islit)
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tcg_gen_movi_i64(cpu_T[1], lit);
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else if (rb != 31) |
365 |
tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]);
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else
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tcg_gen_movi_i64(cpu_T[1], 0); |
368 |
(*gen_arith_op)(); |
369 |
if (rc != 31) |
370 |
tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);
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} |
372 |
|
373 |
static always_inline void gen_cmov (DisasContext *ctx, |
374 |
void (*gen_test_op)(void), |
375 |
int ra, int rb, int rc, |
376 |
int islit, uint8_t lit)
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{ |
378 |
if (ra != 31) |
379 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
|
380 |
else
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381 |
tcg_gen_movi_i64(cpu_T[0], 0); |
382 |
if (islit)
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383 |
tcg_gen_movi_i64(cpu_T[1], lit);
|
384 |
else if (rb != 31) |
385 |
tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]);
|
386 |
else
|
387 |
tcg_gen_movi_i64(cpu_T[1], 0); |
388 |
(*gen_test_op)(); |
389 |
gen_op_cmov_ir(rc); |
390 |
} |
391 |
|
392 |
static always_inline void gen_farith2 (DisasContext *ctx, |
393 |
void (*gen_arith_fop)(void), |
394 |
int rb, int rc) |
395 |
{ |
396 |
gen_load_fir(ctx, rb, 0);
|
397 |
(*gen_arith_fop)(); |
398 |
gen_store_fir(ctx, rc, 0);
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399 |
} |
400 |
|
401 |
static always_inline void gen_farith3 (DisasContext *ctx, |
402 |
void (*gen_arith_fop)(void), |
403 |
int ra, int rb, int rc) |
404 |
{ |
405 |
gen_load_fir(ctx, ra, 0);
|
406 |
gen_load_fir(ctx, rb, 1);
|
407 |
(*gen_arith_fop)(); |
408 |
gen_store_fir(ctx, rc, 0);
|
409 |
} |
410 |
|
411 |
static always_inline void gen_fcmov (DisasContext *ctx, |
412 |
void (*gen_test_fop)(void), |
413 |
int ra, int rb, int rc) |
414 |
{ |
415 |
gen_load_fir(ctx, ra, 0);
|
416 |
gen_load_fir(ctx, rb, 1);
|
417 |
(*gen_test_fop)(); |
418 |
gen_op_cmov_fir(rc); |
419 |
} |
420 |
|
421 |
static always_inline void gen_fti (DisasContext *ctx, |
422 |
void (*gen_move_fop)(void), |
423 |
int ra, int rc) |
424 |
{ |
425 |
gen_load_fir(ctx, rc, 0);
|
426 |
(*gen_move_fop)(); |
427 |
if (ra != 31) |
428 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
|
429 |
} |
430 |
|
431 |
static always_inline void gen_itf (DisasContext *ctx, |
432 |
void (*gen_move_fop)(void), |
433 |
int ra, int rc) |
434 |
{ |
435 |
if (ra != 31) |
436 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
|
437 |
else
|
438 |
tcg_gen_movi_i64(cpu_T[0], 0); |
439 |
(*gen_move_fop)(); |
440 |
gen_store_fir(ctx, rc, 0);
|
441 |
} |
442 |
|
443 |
static always_inline void gen_s4addl (void) |
444 |
{ |
445 |
tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2); |
446 |
gen_op_addl(); |
447 |
} |
448 |
|
449 |
static always_inline void gen_s4subl (void) |
450 |
{ |
451 |
tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2); |
452 |
gen_op_subl(); |
453 |
} |
454 |
|
455 |
static always_inline void gen_s8addl (void) |
456 |
{ |
457 |
tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 3); |
458 |
gen_op_addl(); |
459 |
} |
460 |
|
461 |
static always_inline void gen_s8subl (void) |
462 |
{ |
463 |
tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 3); |
464 |
gen_op_subl(); |
465 |
} |
466 |
|
467 |
static always_inline void gen_s4addq (void) |
468 |
{ |
469 |
tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2); |
470 |
tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
471 |
} |
472 |
|
473 |
static always_inline void gen_s4subq (void) |
474 |
{ |
475 |
tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2); |
476 |
tcg_gen_sub_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
477 |
} |
478 |
|
479 |
static always_inline void gen_s8addq (void) |
480 |
{ |
481 |
tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 3); |
482 |
tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
483 |
} |
484 |
|
485 |
static always_inline void gen_s8subq (void) |
486 |
{ |
487 |
tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 3); |
488 |
tcg_gen_sub_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
489 |
} |
490 |
|
491 |
static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
492 |
{ |
493 |
uint32_t palcode; |
494 |
int32_t disp21, disp16, disp12; |
495 |
uint16_t fn11, fn16; |
496 |
uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit; |
497 |
int8_t lit; |
498 |
int ret;
|
499 |
|
500 |
/* Decode all instruction fields */
|
501 |
opc = insn >> 26;
|
502 |
ra = (insn >> 21) & 0x1F; |
503 |
rb = (insn >> 16) & 0x1F; |
504 |
rc = insn & 0x1F;
|
505 |
sbz = (insn >> 13) & 0x07; |
506 |
islit = (insn >> 12) & 1; |
507 |
lit = (insn >> 13) & 0xFF; |
508 |
palcode = insn & 0x03FFFFFF;
|
509 |
disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11; |
510 |
disp16 = (int16_t)(insn & 0x0000FFFF);
|
511 |
disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20; |
512 |
fn16 = insn & 0x0000FFFF;
|
513 |
fn11 = (insn >> 5) & 0x000007FF; |
514 |
fpfn = fn11 & 0x3F;
|
515 |
fn7 = (insn >> 5) & 0x0000007F; |
516 |
fn2 = (insn >> 5) & 0x00000003; |
517 |
ret = 0;
|
518 |
#if defined ALPHA_DEBUG_DISAS
|
519 |
if (logfile != NULL) { |
520 |
fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
|
521 |
opc, ra, rb, rc, disp16); |
522 |
} |
523 |
#endif
|
524 |
switch (opc) {
|
525 |
case 0x00: |
526 |
/* CALL_PAL */
|
527 |
if (palcode >= 0x80 && palcode < 0xC0) { |
528 |
/* Unprivileged PAL call */
|
529 |
gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0); |
530 |
#if !defined (CONFIG_USER_ONLY)
|
531 |
} else if (palcode < 0x40) { |
532 |
/* Privileged PAL code */
|
533 |
if (ctx->mem_idx & 1) |
534 |
goto invalid_opc;
|
535 |
else
|
536 |
gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x1F) << 6), 0); |
537 |
#endif
|
538 |
} else {
|
539 |
/* Invalid PAL call */
|
540 |
goto invalid_opc;
|
541 |
} |
542 |
ret = 3;
|
543 |
break;
|
544 |
case 0x01: |
545 |
/* OPC01 */
|
546 |
goto invalid_opc;
|
547 |
case 0x02: |
548 |
/* OPC02 */
|
549 |
goto invalid_opc;
|
550 |
case 0x03: |
551 |
/* OPC03 */
|
552 |
goto invalid_opc;
|
553 |
case 0x04: |
554 |
/* OPC04 */
|
555 |
goto invalid_opc;
|
556 |
case 0x05: |
557 |
/* OPC05 */
|
558 |
goto invalid_opc;
|
559 |
case 0x06: |
560 |
/* OPC06 */
|
561 |
goto invalid_opc;
|
562 |
case 0x07: |
563 |
/* OPC07 */
|
564 |
goto invalid_opc;
|
565 |
case 0x08: |
566 |
/* LDA */
|
567 |
if (ra != 31) { |
568 |
if (rb != 31) |
569 |
tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16); |
570 |
else
|
571 |
tcg_gen_movi_i64(cpu_ir[ra], disp16); |
572 |
} |
573 |
break;
|
574 |
case 0x09: |
575 |
/* LDAH */
|
576 |
if (ra != 31) { |
577 |
if (rb != 31) |
578 |
tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
|
579 |
else
|
580 |
tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
|
581 |
} |
582 |
break;
|
583 |
case 0x0A: |
584 |
/* LDBU */
|
585 |
if (!(ctx->amask & AMASK_BWX))
|
586 |
goto invalid_opc;
|
587 |
gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0);
|
588 |
break;
|
589 |
case 0x0B: |
590 |
/* LDQ_U */
|
591 |
gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1);
|
592 |
break;
|
593 |
case 0x0C: |
594 |
/* LDWU */
|
595 |
if (!(ctx->amask & AMASK_BWX))
|
596 |
goto invalid_opc;
|
597 |
gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0);
|
598 |
break;
|
599 |
case 0x0D: |
600 |
/* STW */
|
601 |
if (!(ctx->amask & AMASK_BWX))
|
602 |
goto invalid_opc;
|
603 |
gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0);
|
604 |
break;
|
605 |
case 0x0E: |
606 |
/* STB */
|
607 |
if (!(ctx->amask & AMASK_BWX))
|
608 |
goto invalid_opc;
|
609 |
gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0);
|
610 |
break;
|
611 |
case 0x0F: |
612 |
/* STQ_U */
|
613 |
gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1);
|
614 |
break;
|
615 |
case 0x10: |
616 |
switch (fn7) {
|
617 |
case 0x00: |
618 |
/* ADDL */
|
619 |
gen_arith3(ctx, &gen_op_addl, ra, rb, rc, islit, lit); |
620 |
break;
|
621 |
case 0x02: |
622 |
/* S4ADDL */
|
623 |
gen_arith3(ctx, &gen_s4addl, ra, rb, rc, islit, lit); |
624 |
break;
|
625 |
case 0x09: |
626 |
/* SUBL */
|
627 |
gen_arith3(ctx, &gen_op_subl, ra, rb, rc, islit, lit); |
628 |
break;
|
629 |
case 0x0B: |
630 |
/* S4SUBL */
|
631 |
gen_arith3(ctx, &gen_s4subl, ra, rb, rc, islit, lit); |
632 |
break;
|
633 |
case 0x0F: |
634 |
/* CMPBGE */
|
635 |
gen_arith3(ctx, &gen_op_cmpbge, ra, rb, rc, islit, lit); |
636 |
break;
|
637 |
case 0x12: |
638 |
/* S8ADDL */
|
639 |
gen_arith3(ctx, &gen_s8addl, ra, rb, rc, islit, lit); |
640 |
break;
|
641 |
case 0x1B: |
642 |
/* S8SUBL */
|
643 |
gen_arith3(ctx, &gen_s8subl, ra, rb, rc, islit, lit); |
644 |
break;
|
645 |
case 0x1D: |
646 |
/* CMPULT */
|
647 |
gen_arith3(ctx, &gen_op_cmpult, ra, rb, rc, islit, lit); |
648 |
break;
|
649 |
case 0x20: |
650 |
/* ADDQ */
|
651 |
gen_arith3(ctx, &gen_op_addq, ra, rb, rc, islit, lit); |
652 |
break;
|
653 |
case 0x22: |
654 |
/* S4ADDQ */
|
655 |
gen_arith3(ctx, &gen_s4addq, ra, rb, rc, islit, lit); |
656 |
break;
|
657 |
case 0x29: |
658 |
/* SUBQ */
|
659 |
gen_arith3(ctx, &gen_op_subq, ra, rb, rc, islit, lit); |
660 |
break;
|
661 |
case 0x2B: |
662 |
/* S4SUBQ */
|
663 |
gen_arith3(ctx, &gen_s4subq, ra, rb, rc, islit, lit); |
664 |
break;
|
665 |
case 0x2D: |
666 |
/* CMPEQ */
|
667 |
gen_arith3(ctx, &gen_op_cmpeq, ra, rb, rc, islit, lit); |
668 |
break;
|
669 |
case 0x32: |
670 |
/* S8ADDQ */
|
671 |
gen_arith3(ctx, &gen_s8addq, ra, rb, rc, islit, lit); |
672 |
break;
|
673 |
case 0x3B: |
674 |
/* S8SUBQ */
|
675 |
gen_arith3(ctx, &gen_s8subq, ra, rb, rc, islit, lit); |
676 |
break;
|
677 |
case 0x3D: |
678 |
/* CMPULE */
|
679 |
gen_arith3(ctx, &gen_op_cmpule, ra, rb, rc, islit, lit); |
680 |
break;
|
681 |
case 0x40: |
682 |
/* ADDL/V */
|
683 |
gen_arith3(ctx, &gen_op_addlv, ra, rb, rc, islit, lit); |
684 |
break;
|
685 |
case 0x49: |
686 |
/* SUBL/V */
|
687 |
gen_arith3(ctx, &gen_op_sublv, ra, rb, rc, islit, lit); |
688 |
break;
|
689 |
case 0x4D: |
690 |
/* CMPLT */
|
691 |
gen_arith3(ctx, &gen_op_cmplt, ra, rb, rc, islit, lit); |
692 |
break;
|
693 |
case 0x60: |
694 |
/* ADDQ/V */
|
695 |
gen_arith3(ctx, &gen_op_addqv, ra, rb, rc, islit, lit); |
696 |
break;
|
697 |
case 0x69: |
698 |
/* SUBQ/V */
|
699 |
gen_arith3(ctx, &gen_op_subqv, ra, rb, rc, islit, lit); |
700 |
break;
|
701 |
case 0x6D: |
702 |
/* CMPLE */
|
703 |
gen_arith3(ctx, &gen_op_cmple, ra, rb, rc, islit, lit); |
704 |
break;
|
705 |
default:
|
706 |
goto invalid_opc;
|
707 |
} |
708 |
break;
|
709 |
case 0x11: |
710 |
switch (fn7) {
|
711 |
case 0x00: |
712 |
/* AND */
|
713 |
gen_arith3(ctx, &gen_op_and, ra, rb, rc, islit, lit); |
714 |
break;
|
715 |
case 0x08: |
716 |
/* BIC */
|
717 |
gen_arith3(ctx, &gen_op_bic, ra, rb, rc, islit, lit); |
718 |
break;
|
719 |
case 0x14: |
720 |
/* CMOVLBS */
|
721 |
gen_cmov(ctx, &gen_op_cmplbs, ra, rb, rc, islit, lit); |
722 |
break;
|
723 |
case 0x16: |
724 |
/* CMOVLBC */
|
725 |
gen_cmov(ctx, &gen_op_cmplbc, ra, rb, rc, islit, lit); |
726 |
break;
|
727 |
case 0x20: |
728 |
/* BIS */
|
729 |
if (ra == rb || ra == 31 || rb == 31) { |
730 |
if (ra == 31 && rc == 31) { |
731 |
/* NOP */
|
732 |
gen_op_nop(); |
733 |
} else {
|
734 |
/* MOV */
|
735 |
if (rc != 31) { |
736 |
if (rb != 31) |
737 |
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
738 |
else
|
739 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
740 |
} |
741 |
} |
742 |
} else {
|
743 |
gen_arith3(ctx, &gen_op_bis, ra, rb, rc, islit, lit); |
744 |
} |
745 |
break;
|
746 |
case 0x24: |
747 |
/* CMOVEQ */
|
748 |
gen_cmov(ctx, &gen_op_cmpeqz, ra, rb, rc, islit, lit); |
749 |
break;
|
750 |
case 0x26: |
751 |
/* CMOVNE */
|
752 |
gen_cmov(ctx, &gen_op_cmpnez, ra, rb, rc, islit, lit); |
753 |
break;
|
754 |
case 0x28: |
755 |
/* ORNOT */
|
756 |
gen_arith3(ctx, &gen_op_ornot, ra, rb, rc, islit, lit); |
757 |
break;
|
758 |
case 0x40: |
759 |
/* XOR */
|
760 |
gen_arith3(ctx, &gen_op_xor, ra, rb, rc, islit, lit); |
761 |
break;
|
762 |
case 0x44: |
763 |
/* CMOVLT */
|
764 |
gen_cmov(ctx, &gen_op_cmpltz, ra, rb, rc, islit, lit); |
765 |
break;
|
766 |
case 0x46: |
767 |
/* CMOVGE */
|
768 |
gen_cmov(ctx, &gen_op_cmpgez, ra, rb, rc, islit, lit); |
769 |
break;
|
770 |
case 0x48: |
771 |
/* EQV */
|
772 |
gen_arith3(ctx, &gen_op_eqv, ra, rb, rc, islit, lit); |
773 |
break;
|
774 |
case 0x61: |
775 |
/* AMASK */
|
776 |
if (likely(rc != 31)) { |
777 |
if (islit)
|
778 |
tcg_gen_movi_i64(cpu_ir[rc], helper_amask(lit)); |
779 |
else if (rb != 31) |
780 |
tcg_gen_helper_1_1(helper_amask, cpu_ir[rc], cpu_ir[rb]); |
781 |
else
|
782 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
783 |
} |
784 |
break;
|
785 |
case 0x64: |
786 |
/* CMOVLE */
|
787 |
gen_cmov(ctx, &gen_op_cmplez, ra, rb, rc, islit, lit); |
788 |
break;
|
789 |
case 0x66: |
790 |
/* CMOVGT */
|
791 |
gen_cmov(ctx, &gen_op_cmpgtz, ra, rb, rc, islit, lit); |
792 |
break;
|
793 |
case 0x6C: |
794 |
/* IMPLVER */
|
795 |
gen_op_load_implver(); |
796 |
if (rc != 31) |
797 |
tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);
|
798 |
break;
|
799 |
default:
|
800 |
goto invalid_opc;
|
801 |
} |
802 |
break;
|
803 |
case 0x12: |
804 |
switch (fn7) {
|
805 |
case 0x02: |
806 |
/* MSKBL */
|
807 |
gen_arith3(ctx, &gen_op_mskbl, ra, rb, rc, islit, lit); |
808 |
break;
|
809 |
case 0x06: |
810 |
/* EXTBL */
|
811 |
gen_arith3(ctx, &gen_op_extbl, ra, rb, rc, islit, lit); |
812 |
break;
|
813 |
case 0x0B: |
814 |
/* INSBL */
|
815 |
gen_arith3(ctx, &gen_op_insbl, ra, rb, rc, islit, lit); |
816 |
break;
|
817 |
case 0x12: |
818 |
/* MSKWL */
|
819 |
gen_arith3(ctx, &gen_op_mskwl, ra, rb, rc, islit, lit); |
820 |
break;
|
821 |
case 0x16: |
822 |
/* EXTWL */
|
823 |
gen_arith3(ctx, &gen_op_extwl, ra, rb, rc, islit, lit); |
824 |
break;
|
825 |
case 0x1B: |
826 |
/* INSWL */
|
827 |
gen_arith3(ctx, &gen_op_inswl, ra, rb, rc, islit, lit); |
828 |
break;
|
829 |
case 0x22: |
830 |
/* MSKLL */
|
831 |
gen_arith3(ctx, &gen_op_mskll, ra, rb, rc, islit, lit); |
832 |
break;
|
833 |
case 0x26: |
834 |
/* EXTLL */
|
835 |
gen_arith3(ctx, &gen_op_extll, ra, rb, rc, islit, lit); |
836 |
break;
|
837 |
case 0x2B: |
838 |
/* INSLL */
|
839 |
gen_arith3(ctx, &gen_op_insll, ra, rb, rc, islit, lit); |
840 |
break;
|
841 |
case 0x30: |
842 |
/* ZAP */
|
843 |
gen_arith3(ctx, &gen_op_zap, ra, rb, rc, islit, lit); |
844 |
break;
|
845 |
case 0x31: |
846 |
/* ZAPNOT */
|
847 |
gen_arith3(ctx, &gen_op_zapnot, ra, rb, rc, islit, lit); |
848 |
break;
|
849 |
case 0x32: |
850 |
/* MSKQL */
|
851 |
gen_arith3(ctx, &gen_op_mskql, ra, rb, rc, islit, lit); |
852 |
break;
|
853 |
case 0x34: |
854 |
/* SRL */
|
855 |
gen_arith3(ctx, &gen_op_srl, ra, rb, rc, islit, lit); |
856 |
break;
|
857 |
case 0x36: |
858 |
/* EXTQL */
|
859 |
gen_arith3(ctx, &gen_op_extql, ra, rb, rc, islit, lit); |
860 |
break;
|
861 |
case 0x39: |
862 |
/* SLL */
|
863 |
gen_arith3(ctx, &gen_op_sll, ra, rb, rc, islit, lit); |
864 |
break;
|
865 |
case 0x3B: |
866 |
/* INSQL */
|
867 |
gen_arith3(ctx, &gen_op_insql, ra, rb, rc, islit, lit); |
868 |
break;
|
869 |
case 0x3C: |
870 |
/* SRA */
|
871 |
gen_arith3(ctx, &gen_op_sra, ra, rb, rc, islit, lit); |
872 |
break;
|
873 |
case 0x52: |
874 |
/* MSKWH */
|
875 |
gen_arith3(ctx, &gen_op_mskwh, ra, rb, rc, islit, lit); |
876 |
break;
|
877 |
case 0x57: |
878 |
/* INSWH */
|
879 |
gen_arith3(ctx, &gen_op_inswh, ra, rb, rc, islit, lit); |
880 |
break;
|
881 |
case 0x5A: |
882 |
/* EXTWH */
|
883 |
gen_arith3(ctx, &gen_op_extwh, ra, rb, rc, islit, lit); |
884 |
break;
|
885 |
case 0x62: |
886 |
/* MSKLH */
|
887 |
gen_arith3(ctx, &gen_op_msklh, ra, rb, rc, islit, lit); |
888 |
break;
|
889 |
case 0x67: |
890 |
/* INSLH */
|
891 |
gen_arith3(ctx, &gen_op_inslh, ra, rb, rc, islit, lit); |
892 |
break;
|
893 |
case 0x6A: |
894 |
/* EXTLH */
|
895 |
gen_arith3(ctx, &gen_op_extlh, ra, rb, rc, islit, lit); |
896 |
break;
|
897 |
case 0x72: |
898 |
/* MSKQH */
|
899 |
gen_arith3(ctx, &gen_op_mskqh, ra, rb, rc, islit, lit); |
900 |
break;
|
901 |
case 0x77: |
902 |
/* INSQH */
|
903 |
gen_arith3(ctx, &gen_op_insqh, ra, rb, rc, islit, lit); |
904 |
break;
|
905 |
case 0x7A: |
906 |
/* EXTQH */
|
907 |
gen_arith3(ctx, &gen_op_extqh, ra, rb, rc, islit, lit); |
908 |
break;
|
909 |
default:
|
910 |
goto invalid_opc;
|
911 |
} |
912 |
break;
|
913 |
case 0x13: |
914 |
switch (fn7) {
|
915 |
case 0x00: |
916 |
/* MULL */
|
917 |
gen_arith3(ctx, &gen_op_mull, ra, rb, rc, islit, lit); |
918 |
break;
|
919 |
case 0x20: |
920 |
/* MULQ */
|
921 |
gen_arith3(ctx, &gen_op_mulq, ra, rb, rc, islit, lit); |
922 |
break;
|
923 |
case 0x30: |
924 |
/* UMULH */
|
925 |
gen_arith3(ctx, &gen_op_umulh, ra, rb, rc, islit, lit); |
926 |
break;
|
927 |
case 0x40: |
928 |
/* MULL/V */
|
929 |
gen_arith3(ctx, &gen_op_mullv, ra, rb, rc, islit, lit); |
930 |
break;
|
931 |
case 0x60: |
932 |
/* MULQ/V */
|
933 |
gen_arith3(ctx, &gen_op_mulqv, ra, rb, rc, islit, lit); |
934 |
break;
|
935 |
default:
|
936 |
goto invalid_opc;
|
937 |
} |
938 |
break;
|
939 |
case 0x14: |
940 |
switch (fpfn) { /* f11 & 0x3F */ |
941 |
case 0x04: |
942 |
/* ITOFS */
|
943 |
if (!(ctx->amask & AMASK_FIX))
|
944 |
goto invalid_opc;
|
945 |
gen_itf(ctx, &gen_op_itofs, ra, rc); |
946 |
break;
|
947 |
case 0x0A: |
948 |
/* SQRTF */
|
949 |
if (!(ctx->amask & AMASK_FIX))
|
950 |
goto invalid_opc;
|
951 |
gen_farith2(ctx, &gen_op_sqrtf, rb, rc); |
952 |
break;
|
953 |
case 0x0B: |
954 |
/* SQRTS */
|
955 |
if (!(ctx->amask & AMASK_FIX))
|
956 |
goto invalid_opc;
|
957 |
gen_farith2(ctx, &gen_op_sqrts, rb, rc); |
958 |
break;
|
959 |
case 0x14: |
960 |
/* ITOFF */
|
961 |
if (!(ctx->amask & AMASK_FIX))
|
962 |
goto invalid_opc;
|
963 |
#if 0 // TODO
|
964 |
gen_itf(ctx, &gen_op_itoff, ra, rc);
|
965 |
#else
|
966 |
goto invalid_opc;
|
967 |
#endif
|
968 |
break;
|
969 |
case 0x24: |
970 |
/* ITOFT */
|
971 |
if (!(ctx->amask & AMASK_FIX))
|
972 |
goto invalid_opc;
|
973 |
gen_itf(ctx, &gen_op_itoft, ra, rc); |
974 |
break;
|
975 |
case 0x2A: |
976 |
/* SQRTG */
|
977 |
if (!(ctx->amask & AMASK_FIX))
|
978 |
goto invalid_opc;
|
979 |
gen_farith2(ctx, &gen_op_sqrtg, rb, rc); |
980 |
break;
|
981 |
case 0x02B: |
982 |
/* SQRTT */
|
983 |
if (!(ctx->amask & AMASK_FIX))
|
984 |
goto invalid_opc;
|
985 |
gen_farith2(ctx, &gen_op_sqrtt, rb, rc); |
986 |
break;
|
987 |
default:
|
988 |
goto invalid_opc;
|
989 |
} |
990 |
break;
|
991 |
case 0x15: |
992 |
/* VAX floating point */
|
993 |
/* XXX: rounding mode and trap are ignored (!) */
|
994 |
switch (fpfn) { /* f11 & 0x3F */ |
995 |
case 0x00: |
996 |
/* ADDF */
|
997 |
gen_farith3(ctx, &gen_op_addf, ra, rb, rc); |
998 |
break;
|
999 |
case 0x01: |
1000 |
/* SUBF */
|
1001 |
gen_farith3(ctx, &gen_op_subf, ra, rb, rc); |
1002 |
break;
|
1003 |
case 0x02: |
1004 |
/* MULF */
|
1005 |
gen_farith3(ctx, &gen_op_mulf, ra, rb, rc); |
1006 |
break;
|
1007 |
case 0x03: |
1008 |
/* DIVF */
|
1009 |
gen_farith3(ctx, &gen_op_divf, ra, rb, rc); |
1010 |
break;
|
1011 |
case 0x1E: |
1012 |
/* CVTDG */
|
1013 |
#if 0 // TODO
|
1014 |
gen_farith2(ctx, &gen_op_cvtdg, rb, rc);
|
1015 |
#else
|
1016 |
goto invalid_opc;
|
1017 |
#endif
|
1018 |
break;
|
1019 |
case 0x20: |
1020 |
/* ADDG */
|
1021 |
gen_farith3(ctx, &gen_op_addg, ra, rb, rc); |
1022 |
break;
|
1023 |
case 0x21: |
1024 |
/* SUBG */
|
1025 |
gen_farith3(ctx, &gen_op_subg, ra, rb, rc); |
1026 |
break;
|
1027 |
case 0x22: |
1028 |
/* MULG */
|
1029 |
gen_farith3(ctx, &gen_op_mulg, ra, rb, rc); |
1030 |
break;
|
1031 |
case 0x23: |
1032 |
/* DIVG */
|
1033 |
gen_farith3(ctx, &gen_op_divg, ra, rb, rc); |
1034 |
break;
|
1035 |
case 0x25: |
1036 |
/* CMPGEQ */
|
1037 |
gen_farith3(ctx, &gen_op_cmpgeq, ra, rb, rc); |
1038 |
break;
|
1039 |
case 0x26: |
1040 |
/* CMPGLT */
|
1041 |
gen_farith3(ctx, &gen_op_cmpglt, ra, rb, rc); |
1042 |
break;
|
1043 |
case 0x27: |
1044 |
/* CMPGLE */
|
1045 |
gen_farith3(ctx, &gen_op_cmpgle, ra, rb, rc); |
1046 |
break;
|
1047 |
case 0x2C: |
1048 |
/* CVTGF */
|
1049 |
gen_farith2(ctx, &gen_op_cvtgf, rb, rc); |
1050 |
break;
|
1051 |
case 0x2D: |
1052 |
/* CVTGD */
|
1053 |
#if 0 // TODO
|
1054 |
gen_farith2(ctx, &gen_op_cvtgd, rb, rc);
|
1055 |
#else
|
1056 |
goto invalid_opc;
|
1057 |
#endif
|
1058 |
break;
|
1059 |
case 0x2F: |
1060 |
/* CVTGQ */
|
1061 |
gen_farith2(ctx, &gen_op_cvtgq, rb, rc); |
1062 |
break;
|
1063 |
case 0x3C: |
1064 |
/* CVTQF */
|
1065 |
gen_farith2(ctx, &gen_op_cvtqf, rb, rc); |
1066 |
break;
|
1067 |
case 0x3E: |
1068 |
/* CVTQG */
|
1069 |
gen_farith2(ctx, &gen_op_cvtqg, rb, rc); |
1070 |
break;
|
1071 |
default:
|
1072 |
goto invalid_opc;
|
1073 |
} |
1074 |
break;
|
1075 |
case 0x16: |
1076 |
/* IEEE floating-point */
|
1077 |
/* XXX: rounding mode and traps are ignored (!) */
|
1078 |
switch (fpfn) { /* f11 & 0x3F */ |
1079 |
case 0x00: |
1080 |
/* ADDS */
|
1081 |
gen_farith3(ctx, &gen_op_adds, ra, rb, rc); |
1082 |
break;
|
1083 |
case 0x01: |
1084 |
/* SUBS */
|
1085 |
gen_farith3(ctx, &gen_op_subs, ra, rb, rc); |
1086 |
break;
|
1087 |
case 0x02: |
1088 |
/* MULS */
|
1089 |
gen_farith3(ctx, &gen_op_muls, ra, rb, rc); |
1090 |
break;
|
1091 |
case 0x03: |
1092 |
/* DIVS */
|
1093 |
gen_farith3(ctx, &gen_op_divs, ra, rb, rc); |
1094 |
break;
|
1095 |
case 0x20: |
1096 |
/* ADDT */
|
1097 |
gen_farith3(ctx, &gen_op_addt, ra, rb, rc); |
1098 |
break;
|
1099 |
case 0x21: |
1100 |
/* SUBT */
|
1101 |
gen_farith3(ctx, &gen_op_subt, ra, rb, rc); |
1102 |
break;
|
1103 |
case 0x22: |
1104 |
/* MULT */
|
1105 |
gen_farith3(ctx, &gen_op_mult, ra, rb, rc); |
1106 |
break;
|
1107 |
case 0x23: |
1108 |
/* DIVT */
|
1109 |
gen_farith3(ctx, &gen_op_divt, ra, rb, rc); |
1110 |
break;
|
1111 |
case 0x24: |
1112 |
/* CMPTUN */
|
1113 |
gen_farith3(ctx, &gen_op_cmptun, ra, rb, rc); |
1114 |
break;
|
1115 |
case 0x25: |
1116 |
/* CMPTEQ */
|
1117 |
gen_farith3(ctx, &gen_op_cmpteq, ra, rb, rc); |
1118 |
break;
|
1119 |
case 0x26: |
1120 |
/* CMPTLT */
|
1121 |
gen_farith3(ctx, &gen_op_cmptlt, ra, rb, rc); |
1122 |
break;
|
1123 |
case 0x27: |
1124 |
/* CMPTLE */
|
1125 |
gen_farith3(ctx, &gen_op_cmptle, ra, rb, rc); |
1126 |
break;
|
1127 |
case 0x2C: |
1128 |
/* XXX: incorrect */
|
1129 |
if (fn11 == 0x2AC) { |
1130 |
/* CVTST */
|
1131 |
gen_farith2(ctx, &gen_op_cvtst, rb, rc); |
1132 |
} else {
|
1133 |
/* CVTTS */
|
1134 |
gen_farith2(ctx, &gen_op_cvtts, rb, rc); |
1135 |
} |
1136 |
break;
|
1137 |
case 0x2F: |
1138 |
/* CVTTQ */
|
1139 |
gen_farith2(ctx, &gen_op_cvttq, rb, rc); |
1140 |
break;
|
1141 |
case 0x3C: |
1142 |
/* CVTQS */
|
1143 |
gen_farith2(ctx, &gen_op_cvtqs, rb, rc); |
1144 |
break;
|
1145 |
case 0x3E: |
1146 |
/* CVTQT */
|
1147 |
gen_farith2(ctx, &gen_op_cvtqt, rb, rc); |
1148 |
break;
|
1149 |
default:
|
1150 |
goto invalid_opc;
|
1151 |
} |
1152 |
break;
|
1153 |
case 0x17: |
1154 |
switch (fn11) {
|
1155 |
case 0x010: |
1156 |
/* CVTLQ */
|
1157 |
gen_farith2(ctx, &gen_op_cvtlq, rb, rc); |
1158 |
break;
|
1159 |
case 0x020: |
1160 |
/* CPYS */
|
1161 |
if (ra == rb) {
|
1162 |
if (ra == 31 && rc == 31) { |
1163 |
/* FNOP */
|
1164 |
gen_op_nop(); |
1165 |
} else {
|
1166 |
/* FMOV */
|
1167 |
gen_load_fir(ctx, rb, 0);
|
1168 |
gen_store_fir(ctx, rc, 0);
|
1169 |
} |
1170 |
} else {
|
1171 |
gen_farith3(ctx, &gen_op_cpys, ra, rb, rc); |
1172 |
} |
1173 |
break;
|
1174 |
case 0x021: |
1175 |
/* CPYSN */
|
1176 |
gen_farith2(ctx, &gen_op_cpysn, rb, rc); |
1177 |
break;
|
1178 |
case 0x022: |
1179 |
/* CPYSE */
|
1180 |
gen_farith2(ctx, &gen_op_cpyse, rb, rc); |
1181 |
break;
|
1182 |
case 0x024: |
1183 |
/* MT_FPCR */
|
1184 |
gen_load_fir(ctx, ra, 0);
|
1185 |
gen_op_store_fpcr(); |
1186 |
break;
|
1187 |
case 0x025: |
1188 |
/* MF_FPCR */
|
1189 |
gen_op_load_fpcr(); |
1190 |
gen_store_fir(ctx, ra, 0);
|
1191 |
break;
|
1192 |
case 0x02A: |
1193 |
/* FCMOVEQ */
|
1194 |
gen_fcmov(ctx, &gen_op_cmpfeq, ra, rb, rc); |
1195 |
break;
|
1196 |
case 0x02B: |
1197 |
/* FCMOVNE */
|
1198 |
gen_fcmov(ctx, &gen_op_cmpfne, ra, rb, rc); |
1199 |
break;
|
1200 |
case 0x02C: |
1201 |
/* FCMOVLT */
|
1202 |
gen_fcmov(ctx, &gen_op_cmpflt, ra, rb, rc); |
1203 |
break;
|
1204 |
case 0x02D: |
1205 |
/* FCMOVGE */
|
1206 |
gen_fcmov(ctx, &gen_op_cmpfge, ra, rb, rc); |
1207 |
break;
|
1208 |
case 0x02E: |
1209 |
/* FCMOVLE */
|
1210 |
gen_fcmov(ctx, &gen_op_cmpfle, ra, rb, rc); |
1211 |
break;
|
1212 |
case 0x02F: |
1213 |
/* FCMOVGT */
|
1214 |
gen_fcmov(ctx, &gen_op_cmpfgt, ra, rb, rc); |
1215 |
break;
|
1216 |
case 0x030: |
1217 |
/* CVTQL */
|
1218 |
gen_farith2(ctx, &gen_op_cvtql, rb, rc); |
1219 |
break;
|
1220 |
case 0x130: |
1221 |
/* CVTQL/V */
|
1222 |
gen_farith2(ctx, &gen_op_cvtqlv, rb, rc); |
1223 |
break;
|
1224 |
case 0x530: |
1225 |
/* CVTQL/SV */
|
1226 |
gen_farith2(ctx, &gen_op_cvtqlsv, rb, rc); |
1227 |
break;
|
1228 |
default:
|
1229 |
goto invalid_opc;
|
1230 |
} |
1231 |
break;
|
1232 |
case 0x18: |
1233 |
switch ((uint16_t)disp16) {
|
1234 |
case 0x0000: |
1235 |
/* TRAPB */
|
1236 |
/* No-op. Just exit from the current tb */
|
1237 |
ret = 2;
|
1238 |
break;
|
1239 |
case 0x0400: |
1240 |
/* EXCB */
|
1241 |
/* No-op. Just exit from the current tb */
|
1242 |
ret = 2;
|
1243 |
break;
|
1244 |
case 0x4000: |
1245 |
/* MB */
|
1246 |
/* No-op */
|
1247 |
break;
|
1248 |
case 0x4400: |
1249 |
/* WMB */
|
1250 |
/* No-op */
|
1251 |
break;
|
1252 |
case 0x8000: |
1253 |
/* FETCH */
|
1254 |
/* No-op */
|
1255 |
break;
|
1256 |
case 0xA000: |
1257 |
/* FETCH_M */
|
1258 |
/* No-op */
|
1259 |
break;
|
1260 |
case 0xC000: |
1261 |
/* RPCC */
|
1262 |
gen_op_load_pcc(); |
1263 |
if (ra != 31) |
1264 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
|
1265 |
break;
|
1266 |
case 0xE000: |
1267 |
/* RC */
|
1268 |
gen_op_load_irf(); |
1269 |
if (ra != 31) |
1270 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
|
1271 |
gen_op_clear_irf(); |
1272 |
break;
|
1273 |
case 0xE800: |
1274 |
/* ECB */
|
1275 |
/* XXX: TODO: evict tb cache at address rb */
|
1276 |
#if 0
|
1277 |
ret = 2;
|
1278 |
#else
|
1279 |
goto invalid_opc;
|
1280 |
#endif
|
1281 |
break;
|
1282 |
case 0xF000: |
1283 |
/* RS */
|
1284 |
gen_op_load_irf(); |
1285 |
if (ra != 31) |
1286 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
|
1287 |
gen_op_set_irf(); |
1288 |
break;
|
1289 |
case 0xF800: |
1290 |
/* WH64 */
|
1291 |
/* No-op */
|
1292 |
break;
|
1293 |
default:
|
1294 |
goto invalid_opc;
|
1295 |
} |
1296 |
break;
|
1297 |
case 0x19: |
1298 |
/* HW_MFPR (PALcode) */
|
1299 |
#if defined (CONFIG_USER_ONLY)
|
1300 |
goto invalid_opc;
|
1301 |
#else
|
1302 |
if (!ctx->pal_mode)
|
1303 |
goto invalid_opc;
|
1304 |
gen_op_mfpr(insn & 0xFF);
|
1305 |
if (ra != 31) |
1306 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
|
1307 |
break;
|
1308 |
#endif
|
1309 |
case 0x1A: |
1310 |
if (ra != 31) |
1311 |
tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
1312 |
if (rb != 31) |
1313 |
tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
|
1314 |
else
|
1315 |
tcg_gen_movi_i64(cpu_pc, 0);
|
1316 |
/* Those four jumps only differ by the branch prediction hint */
|
1317 |
switch (fn2) {
|
1318 |
case 0x0: |
1319 |
/* JMP */
|
1320 |
break;
|
1321 |
case 0x1: |
1322 |
/* JSR */
|
1323 |
break;
|
1324 |
case 0x2: |
1325 |
/* RET */
|
1326 |
break;
|
1327 |
case 0x3: |
1328 |
/* JSR_COROUTINE */
|
1329 |
break;
|
1330 |
} |
1331 |
ret = 1;
|
1332 |
break;
|
1333 |
case 0x1B: |
1334 |
/* HW_LD (PALcode) */
|
1335 |
#if defined (CONFIG_USER_ONLY)
|
1336 |
goto invalid_opc;
|
1337 |
#else
|
1338 |
if (!ctx->pal_mode)
|
1339 |
goto invalid_opc;
|
1340 |
if (rb != 31) |
1341 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
|
1342 |
else
|
1343 |
tcg_gen_movi_i64(cpu_T[0], 0); |
1344 |
tcg_gen_movi_i64(cpu_T[1], disp12);
|
1345 |
tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
1346 |
switch ((insn >> 12) & 0xF) { |
1347 |
case 0x0: |
1348 |
/* Longword physical access */
|
1349 |
gen_op_ldl_raw(); |
1350 |
break;
|
1351 |
case 0x1: |
1352 |
/* Quadword physical access */
|
1353 |
gen_op_ldq_raw(); |
1354 |
break;
|
1355 |
case 0x2: |
1356 |
/* Longword physical access with lock */
|
1357 |
gen_op_ldl_l_raw(); |
1358 |
break;
|
1359 |
case 0x3: |
1360 |
/* Quadword physical access with lock */
|
1361 |
gen_op_ldq_l_raw(); |
1362 |
break;
|
1363 |
case 0x4: |
1364 |
/* Longword virtual PTE fetch */
|
1365 |
gen_op_ldl_kernel(); |
1366 |
break;
|
1367 |
case 0x5: |
1368 |
/* Quadword virtual PTE fetch */
|
1369 |
gen_op_ldq_kernel(); |
1370 |
break;
|
1371 |
case 0x6: |
1372 |
/* Invalid */
|
1373 |
goto invalid_opc;
|
1374 |
case 0x7: |
1375 |
/* Invalid */
|
1376 |
goto invalid_opc;
|
1377 |
case 0x8: |
1378 |
/* Longword virtual access */
|
1379 |
gen_op_ld_phys_to_virt(); |
1380 |
gen_op_ldl_raw(); |
1381 |
break;
|
1382 |
case 0x9: |
1383 |
/* Quadword virtual access */
|
1384 |
gen_op_ld_phys_to_virt(); |
1385 |
gen_op_ldq_raw(); |
1386 |
break;
|
1387 |
case 0xA: |
1388 |
/* Longword virtual access with protection check */
|
1389 |
gen_ldl(ctx); |
1390 |
break;
|
1391 |
case 0xB: |
1392 |
/* Quadword virtual access with protection check */
|
1393 |
gen_ldq(ctx); |
1394 |
break;
|
1395 |
case 0xC: |
1396 |
/* Longword virtual access with altenate access mode */
|
1397 |
gen_op_set_alt_mode(); |
1398 |
gen_op_ld_phys_to_virt(); |
1399 |
gen_op_ldl_raw(); |
1400 |
gen_op_restore_mode(); |
1401 |
break;
|
1402 |
case 0xD: |
1403 |
/* Quadword virtual access with altenate access mode */
|
1404 |
gen_op_set_alt_mode(); |
1405 |
gen_op_ld_phys_to_virt(); |
1406 |
gen_op_ldq_raw(); |
1407 |
gen_op_restore_mode(); |
1408 |
break;
|
1409 |
case 0xE: |
1410 |
/* Longword virtual access with alternate access mode and
|
1411 |
* protection checks
|
1412 |
*/
|
1413 |
gen_op_set_alt_mode(); |
1414 |
gen_op_ldl_data(); |
1415 |
gen_op_restore_mode(); |
1416 |
break;
|
1417 |
case 0xF: |
1418 |
/* Quadword virtual access with alternate access mode and
|
1419 |
* protection checks
|
1420 |
*/
|
1421 |
gen_op_set_alt_mode(); |
1422 |
gen_op_ldq_data(); |
1423 |
gen_op_restore_mode(); |
1424 |
break;
|
1425 |
} |
1426 |
if (ra != 31) |
1427 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
|
1428 |
break;
|
1429 |
#endif
|
1430 |
case 0x1C: |
1431 |
switch (fn7) {
|
1432 |
case 0x00: |
1433 |
/* SEXTB */
|
1434 |
if (!(ctx->amask & AMASK_BWX))
|
1435 |
goto invalid_opc;
|
1436 |
if (likely(rc != 31)) { |
1437 |
if (islit)
|
1438 |
tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit)); |
1439 |
else if (rb != 31) |
1440 |
tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]); |
1441 |
else
|
1442 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1443 |
} |
1444 |
break;
|
1445 |
case 0x01: |
1446 |
/* SEXTW */
|
1447 |
if (!(ctx->amask & AMASK_BWX))
|
1448 |
goto invalid_opc;
|
1449 |
if (likely(rc != 31)) { |
1450 |
if (islit)
|
1451 |
tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit)); |
1452 |
else if (rb != 31) |
1453 |
tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]); |
1454 |
else
|
1455 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1456 |
} |
1457 |
break;
|
1458 |
case 0x30: |
1459 |
/* CTPOP */
|
1460 |
if (!(ctx->amask & AMASK_CIX))
|
1461 |
goto invalid_opc;
|
1462 |
if (likely(rc != 31)) { |
1463 |
if (islit)
|
1464 |
tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit)); |
1465 |
else if (rb != 31) |
1466 |
tcg_gen_helper_1_1(helper_ctpop, cpu_ir[rc], cpu_ir[rb]); |
1467 |
else
|
1468 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1469 |
} |
1470 |
break;
|
1471 |
case 0x31: |
1472 |
/* PERR */
|
1473 |
if (!(ctx->amask & AMASK_MVI))
|
1474 |
goto invalid_opc;
|
1475 |
/* XXX: TODO */
|
1476 |
goto invalid_opc;
|
1477 |
break;
|
1478 |
case 0x32: |
1479 |
/* CTLZ */
|
1480 |
if (!(ctx->amask & AMASK_CIX))
|
1481 |
goto invalid_opc;
|
1482 |
if (likely(rc != 31)) { |
1483 |
if (islit)
|
1484 |
tcg_gen_movi_i64(cpu_ir[rc], clz64(lit)); |
1485 |
else if (rb != 31) |
1486 |
tcg_gen_helper_1_1(helper_ctlz, cpu_ir[rc], cpu_ir[rb]); |
1487 |
else
|
1488 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1489 |
} |
1490 |
break;
|
1491 |
case 0x33: |
1492 |
/* CTTZ */
|
1493 |
if (!(ctx->amask & AMASK_CIX))
|
1494 |
goto invalid_opc;
|
1495 |
if (likely(rc != 31)) { |
1496 |
if (islit)
|
1497 |
tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit)); |
1498 |
else if (rb != 31) |
1499 |
tcg_gen_helper_1_1(helper_cttz, cpu_ir[rc], cpu_ir[rb]); |
1500 |
else
|
1501 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1502 |
} |
1503 |
break;
|
1504 |
case 0x34: |
1505 |
/* UNPKBW */
|
1506 |
if (!(ctx->amask & AMASK_MVI))
|
1507 |
goto invalid_opc;
|
1508 |
/* XXX: TODO */
|
1509 |
goto invalid_opc;
|
1510 |
break;
|
1511 |
case 0x35: |
1512 |
/* UNPKWL */
|
1513 |
if (!(ctx->amask & AMASK_MVI))
|
1514 |
goto invalid_opc;
|
1515 |
/* XXX: TODO */
|
1516 |
goto invalid_opc;
|
1517 |
break;
|
1518 |
case 0x36: |
1519 |
/* PKWB */
|
1520 |
if (!(ctx->amask & AMASK_MVI))
|
1521 |
goto invalid_opc;
|
1522 |
/* XXX: TODO */
|
1523 |
goto invalid_opc;
|
1524 |
break;
|
1525 |
case 0x37: |
1526 |
/* PKLB */
|
1527 |
if (!(ctx->amask & AMASK_MVI))
|
1528 |
goto invalid_opc;
|
1529 |
/* XXX: TODO */
|
1530 |
goto invalid_opc;
|
1531 |
break;
|
1532 |
case 0x38: |
1533 |
/* MINSB8 */
|
1534 |
if (!(ctx->amask & AMASK_MVI))
|
1535 |
goto invalid_opc;
|
1536 |
/* XXX: TODO */
|
1537 |
goto invalid_opc;
|
1538 |
break;
|
1539 |
case 0x39: |
1540 |
/* MINSW4 */
|
1541 |
if (!(ctx->amask & AMASK_MVI))
|
1542 |
goto invalid_opc;
|
1543 |
/* XXX: TODO */
|
1544 |
goto invalid_opc;
|
1545 |
break;
|
1546 |
case 0x3A: |
1547 |
/* MINUB8 */
|
1548 |
if (!(ctx->amask & AMASK_MVI))
|
1549 |
goto invalid_opc;
|
1550 |
/* XXX: TODO */
|
1551 |
goto invalid_opc;
|
1552 |
break;
|
1553 |
case 0x3B: |
1554 |
/* MINUW4 */
|
1555 |
if (!(ctx->amask & AMASK_MVI))
|
1556 |
goto invalid_opc;
|
1557 |
/* XXX: TODO */
|
1558 |
goto invalid_opc;
|
1559 |
break;
|
1560 |
case 0x3C: |
1561 |
/* MAXUB8 */
|
1562 |
if (!(ctx->amask & AMASK_MVI))
|
1563 |
goto invalid_opc;
|
1564 |
/* XXX: TODO */
|
1565 |
goto invalid_opc;
|
1566 |
break;
|
1567 |
case 0x3D: |
1568 |
/* MAXUW4 */
|
1569 |
if (!(ctx->amask & AMASK_MVI))
|
1570 |
goto invalid_opc;
|
1571 |
/* XXX: TODO */
|
1572 |
goto invalid_opc;
|
1573 |
break;
|
1574 |
case 0x3E: |
1575 |
/* MAXSB8 */
|
1576 |
if (!(ctx->amask & AMASK_MVI))
|
1577 |
goto invalid_opc;
|
1578 |
/* XXX: TODO */
|
1579 |
goto invalid_opc;
|
1580 |
break;
|
1581 |
case 0x3F: |
1582 |
/* MAXSW4 */
|
1583 |
if (!(ctx->amask & AMASK_MVI))
|
1584 |
goto invalid_opc;
|
1585 |
/* XXX: TODO */
|
1586 |
goto invalid_opc;
|
1587 |
break;
|
1588 |
case 0x70: |
1589 |
/* FTOIT */
|
1590 |
if (!(ctx->amask & AMASK_FIX))
|
1591 |
goto invalid_opc;
|
1592 |
gen_fti(ctx, &gen_op_ftoit, ra, rb); |
1593 |
break;
|
1594 |
case 0x78: |
1595 |
/* FTOIS */
|
1596 |
if (!(ctx->amask & AMASK_FIX))
|
1597 |
goto invalid_opc;
|
1598 |
gen_fti(ctx, &gen_op_ftois, ra, rb); |
1599 |
break;
|
1600 |
default:
|
1601 |
goto invalid_opc;
|
1602 |
} |
1603 |
break;
|
1604 |
case 0x1D: |
1605 |
/* HW_MTPR (PALcode) */
|
1606 |
#if defined (CONFIG_USER_ONLY)
|
1607 |
goto invalid_opc;
|
1608 |
#else
|
1609 |
if (!ctx->pal_mode)
|
1610 |
goto invalid_opc;
|
1611 |
if (ra != 31) |
1612 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
|
1613 |
else
|
1614 |
tcg_gen_movi_i64(cpu_T[0], 0); |
1615 |
gen_op_mtpr(insn & 0xFF);
|
1616 |
ret = 2;
|
1617 |
break;
|
1618 |
#endif
|
1619 |
case 0x1E: |
1620 |
/* HW_REI (PALcode) */
|
1621 |
#if defined (CONFIG_USER_ONLY)
|
1622 |
goto invalid_opc;
|
1623 |
#else
|
1624 |
if (!ctx->pal_mode)
|
1625 |
goto invalid_opc;
|
1626 |
if (rb == 31) { |
1627 |
/* "Old" alpha */
|
1628 |
gen_op_hw_rei(); |
1629 |
} else {
|
1630 |
if (ra != 31) |
1631 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
|
1632 |
else
|
1633 |
tcg_gen_movi_i64(cpu_T[0], 0); |
1634 |
tcg_gen_movi_i64(cpu_T[1], (((int64_t)insn << 51) >> 51)); |
1635 |
tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
1636 |
gen_op_hw_ret(); |
1637 |
} |
1638 |
ret = 2;
|
1639 |
break;
|
1640 |
#endif
|
1641 |
case 0x1F: |
1642 |
/* HW_ST (PALcode) */
|
1643 |
#if defined (CONFIG_USER_ONLY)
|
1644 |
goto invalid_opc;
|
1645 |
#else
|
1646 |
if (!ctx->pal_mode)
|
1647 |
goto invalid_opc;
|
1648 |
if (ra != 31) |
1649 |
tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp12);
|
1650 |
else
|
1651 |
tcg_gen_movi_i64(cpu_T[0], disp12);
|
1652 |
if (ra != 31) |
1653 |
tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
|
1654 |
else
|
1655 |
tcg_gen_movi_i64(cpu_T[1], 0); |
1656 |
switch ((insn >> 12) & 0xF) { |
1657 |
case 0x0: |
1658 |
/* Longword physical access */
|
1659 |
gen_op_stl_raw(); |
1660 |
break;
|
1661 |
case 0x1: |
1662 |
/* Quadword physical access */
|
1663 |
gen_op_stq_raw(); |
1664 |
break;
|
1665 |
case 0x2: |
1666 |
/* Longword physical access with lock */
|
1667 |
gen_op_stl_c_raw(); |
1668 |
break;
|
1669 |
case 0x3: |
1670 |
/* Quadword physical access with lock */
|
1671 |
gen_op_stq_c_raw(); |
1672 |
break;
|
1673 |
case 0x4: |
1674 |
/* Longword virtual access */
|
1675 |
gen_op_st_phys_to_virt(); |
1676 |
gen_op_stl_raw(); |
1677 |
break;
|
1678 |
case 0x5: |
1679 |
/* Quadword virtual access */
|
1680 |
gen_op_st_phys_to_virt(); |
1681 |
gen_op_stq_raw(); |
1682 |
break;
|
1683 |
case 0x6: |
1684 |
/* Invalid */
|
1685 |
goto invalid_opc;
|
1686 |
case 0x7: |
1687 |
/* Invalid */
|
1688 |
goto invalid_opc;
|
1689 |
case 0x8: |
1690 |
/* Invalid */
|
1691 |
goto invalid_opc;
|
1692 |
case 0x9: |
1693 |
/* Invalid */
|
1694 |
goto invalid_opc;
|
1695 |
case 0xA: |
1696 |
/* Invalid */
|
1697 |
goto invalid_opc;
|
1698 |
case 0xB: |
1699 |
/* Invalid */
|
1700 |
goto invalid_opc;
|
1701 |
case 0xC: |
1702 |
/* Longword virtual access with alternate access mode */
|
1703 |
gen_op_set_alt_mode(); |
1704 |
gen_op_st_phys_to_virt(); |
1705 |
gen_op_ldl_raw(); |
1706 |
gen_op_restore_mode(); |
1707 |
break;
|
1708 |
case 0xD: |
1709 |
/* Quadword virtual access with alternate access mode */
|
1710 |
gen_op_set_alt_mode(); |
1711 |
gen_op_st_phys_to_virt(); |
1712 |
gen_op_ldq_raw(); |
1713 |
gen_op_restore_mode(); |
1714 |
break;
|
1715 |
case 0xE: |
1716 |
/* Invalid */
|
1717 |
goto invalid_opc;
|
1718 |
case 0xF: |
1719 |
/* Invalid */
|
1720 |
goto invalid_opc;
|
1721 |
} |
1722 |
ret = 2;
|
1723 |
break;
|
1724 |
#endif
|
1725 |
case 0x20: |
1726 |
/* LDF */
|
1727 |
#if 0 // TODO
|
1728 |
gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16);
|
1729 |
#else
|
1730 |
goto invalid_opc;
|
1731 |
#endif
|
1732 |
break;
|
1733 |
case 0x21: |
1734 |
/* LDG */
|
1735 |
#if 0 // TODO
|
1736 |
gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16);
|
1737 |
#else
|
1738 |
goto invalid_opc;
|
1739 |
#endif
|
1740 |
break;
|
1741 |
case 0x22: |
1742 |
/* LDS */
|
1743 |
gen_load_fmem(ctx, &gen_lds, ra, rb, disp16); |
1744 |
break;
|
1745 |
case 0x23: |
1746 |
/* LDT */
|
1747 |
gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16); |
1748 |
break;
|
1749 |
case 0x24: |
1750 |
/* STF */
|
1751 |
#if 0 // TODO
|
1752 |
gen_store_fmem(ctx, &gen_stf, ra, rb, disp16);
|
1753 |
#else
|
1754 |
goto invalid_opc;
|
1755 |
#endif
|
1756 |
break;
|
1757 |
case 0x25: |
1758 |
/* STG */
|
1759 |
#if 0 // TODO
|
1760 |
gen_store_fmem(ctx, &gen_stg, ra, rb, disp16);
|
1761 |
#else
|
1762 |
goto invalid_opc;
|
1763 |
#endif
|
1764 |
break;
|
1765 |
case 0x26: |
1766 |
/* STS */
|
1767 |
gen_store_fmem(ctx, &gen_sts, ra, rb, disp16); |
1768 |
break;
|
1769 |
case 0x27: |
1770 |
/* STT */
|
1771 |
gen_store_fmem(ctx, &gen_stt, ra, rb, disp16); |
1772 |
break;
|
1773 |
case 0x28: |
1774 |
/* LDL */
|
1775 |
gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0);
|
1776 |
break;
|
1777 |
case 0x29: |
1778 |
/* LDQ */
|
1779 |
gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0);
|
1780 |
break;
|
1781 |
case 0x2A: |
1782 |
/* LDL_L */
|
1783 |
gen_load_mem(ctx, &gen_ldl_l, ra, rb, disp16, 0);
|
1784 |
break;
|
1785 |
case 0x2B: |
1786 |
/* LDQ_L */
|
1787 |
gen_load_mem(ctx, &gen_ldq_l, ra, rb, disp16, 0);
|
1788 |
break;
|
1789 |
case 0x2C: |
1790 |
/* STL */
|
1791 |
gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0);
|
1792 |
break;
|
1793 |
case 0x2D: |
1794 |
/* STQ */
|
1795 |
gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0);
|
1796 |
break;
|
1797 |
case 0x2E: |
1798 |
/* STL_C */
|
1799 |
gen_store_mem(ctx, &gen_stl_c, ra, rb, disp16, 0);
|
1800 |
break;
|
1801 |
case 0x2F: |
1802 |
/* STQ_C */
|
1803 |
gen_store_mem(ctx, &gen_stq_c, ra, rb, disp16, 0);
|
1804 |
break;
|
1805 |
case 0x30: |
1806 |
/* BR */
|
1807 |
if (ra != 31) |
1808 |
tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
1809 |
tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
|
1810 |
ret = 1;
|
1811 |
break;
|
1812 |
case 0x31: |
1813 |
/* FBEQ */
|
1814 |
gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16); |
1815 |
ret = 1;
|
1816 |
break;
|
1817 |
case 0x32: |
1818 |
/* FBLT */
|
1819 |
gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16); |
1820 |
ret = 1;
|
1821 |
break;
|
1822 |
case 0x33: |
1823 |
/* FBLE */
|
1824 |
gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16); |
1825 |
ret = 1;
|
1826 |
break;
|
1827 |
case 0x34: |
1828 |
/* BSR */
|
1829 |
if (ra != 31) |
1830 |
tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
1831 |
tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
|
1832 |
ret = 1;
|
1833 |
break;
|
1834 |
case 0x35: |
1835 |
/* FBNE */
|
1836 |
gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16); |
1837 |
ret = 1;
|
1838 |
break;
|
1839 |
case 0x36: |
1840 |
/* FBGE */
|
1841 |
gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16); |
1842 |
ret = 1;
|
1843 |
break;
|
1844 |
case 0x37: |
1845 |
/* FBGT */
|
1846 |
gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16); |
1847 |
ret = 1;
|
1848 |
break;
|
1849 |
case 0x38: |
1850 |
/* BLBC */
|
1851 |
gen_bcond(ctx, &gen_op_cmplbc, ra, disp16); |
1852 |
ret = 1;
|
1853 |
break;
|
1854 |
case 0x39: |
1855 |
/* BEQ */
|
1856 |
gen_bcond(ctx, &gen_op_cmpeqz, ra, disp16); |
1857 |
ret = 1;
|
1858 |
break;
|
1859 |
case 0x3A: |
1860 |
/* BLT */
|
1861 |
gen_bcond(ctx, &gen_op_cmpltz, ra, disp16); |
1862 |
ret = 1;
|
1863 |
break;
|
1864 |
case 0x3B: |
1865 |
/* BLE */
|
1866 |
gen_bcond(ctx, &gen_op_cmplez, ra, disp16); |
1867 |
ret = 1;
|
1868 |
break;
|
1869 |
case 0x3C: |
1870 |
/* BLBS */
|
1871 |
gen_bcond(ctx, &gen_op_cmplbs, ra, disp16); |
1872 |
ret = 1;
|
1873 |
break;
|
1874 |
case 0x3D: |
1875 |
/* BNE */
|
1876 |
gen_bcond(ctx, &gen_op_cmpnez, ra, disp16); |
1877 |
ret = 1;
|
1878 |
break;
|
1879 |
case 0x3E: |
1880 |
/* BGE */
|
1881 |
gen_bcond(ctx, &gen_op_cmpgez, ra, disp16); |
1882 |
ret = 1;
|
1883 |
break;
|
1884 |
case 0x3F: |
1885 |
/* BGT */
|
1886 |
gen_bcond(ctx, &gen_op_cmpgtz, ra, disp16); |
1887 |
ret = 1;
|
1888 |
break;
|
1889 |
invalid_opc:
|
1890 |
gen_invalid(ctx); |
1891 |
ret = 3;
|
1892 |
break;
|
1893 |
} |
1894 |
|
1895 |
return ret;
|
1896 |
} |
1897 |
|
1898 |
static always_inline void gen_intermediate_code_internal (CPUState *env, |
1899 |
TranslationBlock *tb, |
1900 |
int search_pc)
|
1901 |
{ |
1902 |
#if defined ALPHA_DEBUG_DISAS
|
1903 |
static int insn_count; |
1904 |
#endif
|
1905 |
DisasContext ctx, *ctxp = &ctx; |
1906 |
target_ulong pc_start; |
1907 |
uint32_t insn; |
1908 |
uint16_t *gen_opc_end; |
1909 |
int j, lj = -1; |
1910 |
int ret;
|
1911 |
int num_insns;
|
1912 |
int max_insns;
|
1913 |
|
1914 |
pc_start = tb->pc; |
1915 |
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
1916 |
ctx.pc = pc_start; |
1917 |
ctx.amask = env->amask; |
1918 |
#if defined (CONFIG_USER_ONLY)
|
1919 |
ctx.mem_idx = 0;
|
1920 |
#else
|
1921 |
ctx.mem_idx = ((env->ps >> 3) & 3); |
1922 |
ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
|
1923 |
#endif
|
1924 |
num_insns = 0;
|
1925 |
max_insns = tb->cflags & CF_COUNT_MASK; |
1926 |
if (max_insns == 0) |
1927 |
max_insns = CF_COUNT_MASK; |
1928 |
|
1929 |
gen_icount_start(); |
1930 |
for (ret = 0; ret == 0;) { |
1931 |
if (env->nb_breakpoints > 0) { |
1932 |
for(j = 0; j < env->nb_breakpoints; j++) { |
1933 |
if (env->breakpoints[j] == ctx.pc) {
|
1934 |
gen_excp(&ctx, EXCP_DEBUG, 0);
|
1935 |
break;
|
1936 |
} |
1937 |
} |
1938 |
} |
1939 |
if (search_pc) {
|
1940 |
j = gen_opc_ptr - gen_opc_buf; |
1941 |
if (lj < j) {
|
1942 |
lj++; |
1943 |
while (lj < j)
|
1944 |
gen_opc_instr_start[lj++] = 0;
|
1945 |
gen_opc_pc[lj] = ctx.pc; |
1946 |
gen_opc_instr_start[lj] = 1;
|
1947 |
gen_opc_icount[lj] = num_insns; |
1948 |
} |
1949 |
} |
1950 |
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
1951 |
gen_io_start(); |
1952 |
#if defined ALPHA_DEBUG_DISAS
|
1953 |
insn_count++; |
1954 |
if (logfile != NULL) { |
1955 |
fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n", |
1956 |
ctx.pc, ctx.mem_idx); |
1957 |
} |
1958 |
#endif
|
1959 |
insn = ldl_code(ctx.pc); |
1960 |
#if defined ALPHA_DEBUG_DISAS
|
1961 |
insn_count++; |
1962 |
if (logfile != NULL) { |
1963 |
fprintf(logfile, "opcode %08x %d\n", insn, insn_count);
|
1964 |
} |
1965 |
#endif
|
1966 |
num_insns++; |
1967 |
ctx.pc += 4;
|
1968 |
ret = translate_one(ctxp, insn); |
1969 |
if (ret != 0) |
1970 |
break;
|
1971 |
/* if we reach a page boundary or are single stepping, stop
|
1972 |
* generation
|
1973 |
*/
|
1974 |
if (((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) || |
1975 |
(env->singlestep_enabled) || |
1976 |
num_insns >= max_insns) { |
1977 |
break;
|
1978 |
} |
1979 |
#if defined (DO_SINGLE_STEP)
|
1980 |
break;
|
1981 |
#endif
|
1982 |
} |
1983 |
if (ret != 1 && ret != 3) { |
1984 |
tcg_gen_movi_i64(cpu_pc, ctx.pc); |
1985 |
} |
1986 |
#if defined (DO_TB_FLUSH)
|
1987 |
tcg_gen_helper_0_0(helper_tb_flush); |
1988 |
#endif
|
1989 |
if (tb->cflags & CF_LAST_IO)
|
1990 |
gen_io_end(); |
1991 |
/* Generate the return instruction */
|
1992 |
tcg_gen_exit_tb(0);
|
1993 |
gen_icount_end(tb, num_insns); |
1994 |
*gen_opc_ptr = INDEX_op_end; |
1995 |
if (search_pc) {
|
1996 |
j = gen_opc_ptr - gen_opc_buf; |
1997 |
lj++; |
1998 |
while (lj <= j)
|
1999 |
gen_opc_instr_start[lj++] = 0;
|
2000 |
} else {
|
2001 |
tb->size = ctx.pc - pc_start; |
2002 |
tb->icount = num_insns; |
2003 |
} |
2004 |
#if defined ALPHA_DEBUG_DISAS
|
2005 |
if (loglevel & CPU_LOG_TB_CPU) {
|
2006 |
cpu_dump_state(env, logfile, fprintf, 0);
|
2007 |
} |
2008 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
2009 |
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
2010 |
target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
|
2011 |
fprintf(logfile, "\n");
|
2012 |
} |
2013 |
#endif
|
2014 |
} |
2015 |
|
2016 |
void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
2017 |
{ |
2018 |
gen_intermediate_code_internal(env, tb, 0);
|
2019 |
} |
2020 |
|
2021 |
void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
2022 |
{ |
2023 |
gen_intermediate_code_internal(env, tb, 1);
|
2024 |
} |
2025 |
|
2026 |
CPUAlphaState * cpu_alpha_init (const char *cpu_model) |
2027 |
{ |
2028 |
CPUAlphaState *env; |
2029 |
uint64_t hwpcb; |
2030 |
|
2031 |
env = qemu_mallocz(sizeof(CPUAlphaState));
|
2032 |
if (!env)
|
2033 |
return NULL; |
2034 |
cpu_exec_init(env); |
2035 |
alpha_translate_init(); |
2036 |
tlb_flush(env, 1);
|
2037 |
/* XXX: should not be hardcoded */
|
2038 |
env->implver = IMPLVER_2106x; |
2039 |
env->ps = 0x1F00;
|
2040 |
#if defined (CONFIG_USER_ONLY)
|
2041 |
env->ps |= 1 << 3; |
2042 |
#endif
|
2043 |
pal_init(env); |
2044 |
/* Initialize IPR */
|
2045 |
hwpcb = env->ipr[IPR_PCBB]; |
2046 |
env->ipr[IPR_ASN] = 0;
|
2047 |
env->ipr[IPR_ASTEN] = 0;
|
2048 |
env->ipr[IPR_ASTSR] = 0;
|
2049 |
env->ipr[IPR_DATFX] = 0;
|
2050 |
/* XXX: fix this */
|
2051 |
// env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
|
2052 |
// env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
|
2053 |
// env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
|
2054 |
// env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
|
2055 |
env->ipr[IPR_FEN] = 0;
|
2056 |
env->ipr[IPR_IPL] = 31;
|
2057 |
env->ipr[IPR_MCES] = 0;
|
2058 |
env->ipr[IPR_PERFMON] = 0; /* Implementation specific */ |
2059 |
// env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
|
2060 |
env->ipr[IPR_SISR] = 0;
|
2061 |
env->ipr[IPR_VIRBND] = -1ULL;
|
2062 |
|
2063 |
return env;
|
2064 |
} |
2065 |
|
2066 |
void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
2067 |
unsigned long searched_pc, int pc_pos, void *puc) |
2068 |
{ |
2069 |
env->pc = gen_opc_pc[pc_pos]; |
2070 |
} |