Revision aef445bd
| b/Makefile.target | ||
|---|---|---|
| 289 | 289 |
endif |
| 290 | 290 |
|
| 291 | 291 |
# must use static linking to avoid leaving stuff in virtual address space |
| 292 |
VL_OBJS=vl.o osdep.o readline.o monitor.o pci.o console.o loader.o |
|
| 292 |
VL_OBJS=vl.o osdep.o readline.o monitor.o pci.o console.o loader.o isa_mmio.o
|
|
| 293 | 293 |
VL_OBJS+=block.o block-raw.o |
| 294 | 294 |
VL_OBJS+=block-cow.o block-qcow.o aes.o block-vmdk.o block-cloop.o block-dmg.o block-bochs.o block-vpc.o block-vvfat.o block-qcow2.o |
| 295 | 295 |
ifdef CONFIG_WIN32 |
| b/hw/isa_mmio.c | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
* Memory mapped access to ISA IO space. |
|
| 3 |
* |
|
| 4 |
* Copyright (c) 2006 Fabrice Bellard |
|
| 5 |
* |
|
| 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
|
| 7 |
* of this software and associated documentation files (the "Software"), to deal |
|
| 8 |
* in the Software without restriction, including without limitation the rights |
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| 9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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* copies of the Software, and to permit persons to whom the Software is |
|
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* furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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* THE SOFTWARE. |
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*/ |
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|
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#include "vl.h" |
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|
|
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static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr, |
|
| 28 |
uint32_t val) |
|
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{
|
|
| 30 |
cpu_outb(NULL, addr & 0xffff, val); |
|
| 31 |
} |
|
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|
|
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static void isa_mmio_writew (void *opaque, target_phys_addr_t addr, |
|
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uint32_t val) |
|
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{
|
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#ifdef TARGET_WORDS_BIGENDIAN |
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val = bswap16(val); |
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#endif |
|
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cpu_outw(NULL, addr & 0xffff, val); |
|
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} |
|
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|
|
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static void isa_mmio_writel (void *opaque, target_phys_addr_t addr, |
|
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uint32_t val) |
|
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{
|
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#ifdef TARGET_WORDS_BIGENDIAN |
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val = bswap32(val); |
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#endif |
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cpu_outl(NULL, addr & 0xffff, val); |
|
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} |
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|
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static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr) |
|
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{
|
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uint32_t val; |
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|
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val = cpu_inb(NULL, addr & 0xffff); |
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return val; |
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} |
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|
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static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr) |
|
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{
|
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uint32_t val; |
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|
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val = cpu_inw(NULL, addr & 0xffff); |
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#ifdef TARGET_WORDS_BIGENDIAN |
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val = bswap16(val); |
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#endif |
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return val; |
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} |
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|
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static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr) |
|
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{
|
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uint32_t val; |
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|
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val = cpu_inl(NULL, addr & 0xffff); |
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#ifdef TARGET_WORDS_BIGENDIAN |
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val = bswap32(val); |
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#endif |
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return val; |
|
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} |
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|
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static CPUWriteMemoryFunc *isa_mmio_write[] = {
|
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&isa_mmio_writeb, |
|
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&isa_mmio_writew, |
|
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&isa_mmio_writel, |
|
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}; |
|
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|
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static CPUReadMemoryFunc *isa_mmio_read[] = {
|
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&isa_mmio_readb, |
|
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&isa_mmio_readw, |
|
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&isa_mmio_readl, |
|
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}; |
|
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|
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static int isa_mmio_iomemtype = 0; |
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|
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void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size) |
|
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{
|
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if (!isa_mmio_iomemtype) {
|
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isa_mmio_iomemtype = cpu_register_io_memory(0, isa_mmio_read, |
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isa_mmio_write, NULL); |
|
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} |
|
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cpu_register_physical_memory(base, size, isa_mmio_iomemtype); |
|
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} |
|
| b/hw/mips_r4k.c | ||
|---|---|---|
| 107 | 107 |
} |
| 108 | 108 |
|
| 109 | 109 |
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static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
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{
|
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#if 0 |
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if (logfile) |
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); |
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#endif |
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cpu_outb(NULL, addr & 0xffff, value); |
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} |
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|
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static uint32_t io_readb (void *opaque, target_phys_addr_t addr) |
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{
|
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uint32_t ret = cpu_inb(NULL, addr & 0xffff); |
|
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#if 0 |
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if (logfile) |
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); |
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#endif |
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return ret; |
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} |
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|
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static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
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{
|
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#if 0 |
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if (logfile) |
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); |
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#endif |
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#ifdef TARGET_WORDS_BIGENDIAN |
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value = bswap16(value); |
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#endif |
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cpu_outw(NULL, addr & 0xffff, value); |
|
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} |
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|
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static uint32_t io_readw (void *opaque, target_phys_addr_t addr) |
|
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{
|
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uint32_t ret = cpu_inw(NULL, addr & 0xffff); |
|
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#ifdef TARGET_WORDS_BIGENDIAN |
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ret = bswap16(ret); |
|
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#endif |
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#if 0 |
|
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if (logfile) |
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); |
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#endif |
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return ret; |
|
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} |
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|
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static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
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{
|
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#if 0 |
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if (logfile) |
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); |
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#endif |
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#ifdef TARGET_WORDS_BIGENDIAN |
|
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value = bswap32(value); |
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#endif |
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cpu_outl(NULL, addr & 0xffff, value); |
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} |
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|
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static uint32_t io_readl (void *opaque, target_phys_addr_t addr) |
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{
|
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uint32_t ret = cpu_inl(NULL, addr & 0xffff); |
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|
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#ifdef TARGET_WORDS_BIGENDIAN |
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ret = bswap32(ret); |
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#endif |
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#if 0 |
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if (logfile) |
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); |
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#endif |
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return ret; |
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} |
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|
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CPUWriteMemoryFunc *io_write[] = {
|
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&io_writeb, |
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&io_writew, |
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&io_writel, |
|
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}; |
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|
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CPUReadMemoryFunc *io_read[] = {
|
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&io_readb, |
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&io_readw, |
|
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&io_readl, |
|
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}; |
|
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|
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| 192 | 110 |
void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, |
| 193 | 111 |
DisplayState *ds, const char **fd_filename, int snapshot, |
| 194 | 112 |
const char *kernel_filename, const char *kernel_cmdline, |
| ... | ... | |
| 197 | 115 |
char buf[1024]; |
| 198 | 116 |
int64_t entry = 0; |
| 199 | 117 |
unsigned long bios_offset; |
| 200 |
int io_memory; |
|
| 201 | 118 |
int ret; |
| 202 | 119 |
CPUState *env; |
| 203 | 120 |
long kernel_size; |
| ... | ... | |
| 263 | 180 |
cpu_mips_irqctrl_init(); |
| 264 | 181 |
|
| 265 | 182 |
/* Register 64 KB of ISA IO space at 0x14000000 */ |
| 266 |
io_memory = cpu_register_io_memory(0, io_read, io_write, NULL); |
|
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cpu_register_physical_memory(0x14000000, 0x00010000, io_memory); |
|
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isa_mmio_init(0x14000000, 0x00010000); |
|
| 268 | 184 |
isa_mem_base = 0x10000000; |
| 269 | 185 |
|
| 270 | 186 |
isa_pic = pic_init(pic_irq_request, env); |
| b/hw/ppc.c | ||
|---|---|---|
| 201 | 201 |
} |
| 202 | 202 |
#endif |
| 203 | 203 |
|
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static void PPC_io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
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{
|
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| 206 |
cpu_outb(NULL, addr & 0xffff, value); |
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} |
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|
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static uint32_t PPC_io_readb (void *opaque, target_phys_addr_t addr) |
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{
|
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uint32_t ret = cpu_inb(NULL, addr & 0xffff); |
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return ret; |
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} |
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|
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static void PPC_io_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
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{
|
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| 217 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
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value = bswap16(value); |
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#endif |
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cpu_outw(NULL, addr & 0xffff, value); |
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} |
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|
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static uint32_t PPC_io_readw (void *opaque, target_phys_addr_t addr) |
|
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{
|
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uint32_t ret = cpu_inw(NULL, addr & 0xffff); |
|
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#ifdef TARGET_WORDS_BIGENDIAN |
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ret = bswap16(ret); |
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#endif |
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return ret; |
|
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} |
|
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|
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| 232 |
static void PPC_io_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
| 233 |
{
|
|
| 234 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
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value = bswap32(value); |
|
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#endif |
|
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cpu_outl(NULL, addr & 0xffff, value); |
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} |
|
| 239 |
|
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| 240 |
static uint32_t PPC_io_readl (void *opaque, target_phys_addr_t addr) |
|
| 241 |
{
|
|
| 242 |
uint32_t ret = cpu_inl(NULL, addr & 0xffff); |
|
| 243 |
|
|
| 244 |
#ifdef TARGET_WORDS_BIGENDIAN |
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ret = bswap32(ret); |
|
| 246 |
#endif |
|
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return ret; |
|
| 248 |
} |
|
| 249 |
|
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| 250 |
CPUWriteMemoryFunc *PPC_io_write[] = {
|
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| 251 |
&PPC_io_writeb, |
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&PPC_io_writew, |
|
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&PPC_io_writel, |
|
| 254 |
}; |
|
| 255 |
|
|
| 256 |
CPUReadMemoryFunc *PPC_io_read[] = {
|
|
| 257 |
&PPC_io_readb, |
|
| 258 |
&PPC_io_readw, |
|
| 259 |
&PPC_io_readl, |
|
| 260 |
}; |
|
| 261 |
|
|
| 262 | 204 |
/*****************************************************************************/ |
| 263 | 205 |
/* Debug port */ |
| 264 | 206 |
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
| b/hw/ppc_chrp.c | ||
|---|---|---|
| 305 | 305 |
SetIRQFunc *set_irq; |
| 306 | 306 |
void *pic; |
| 307 | 307 |
m48t59_t *nvram; |
| 308 |
int PPC_io_memory, unin_memory;
|
|
| 308 |
int unin_memory; |
|
| 309 | 309 |
int linux_boot, i; |
| 310 | 310 |
unsigned long bios_offset, vga_bios_offset; |
| 311 | 311 |
uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
| ... | ... | |
| 417 | 417 |
isa_mem_base = 0x80000000; |
| 418 | 418 |
|
| 419 | 419 |
/* Register 2 MB of ISA IO space */ |
| 420 |
PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL); |
|
| 421 |
cpu_register_physical_memory(0xfe000000, 0x00200000, PPC_io_memory); |
|
| 422 |
|
|
| 420 |
isa_mmio_init(0xfe000000, 0x00200000); |
|
| 421 |
|
|
| 423 | 422 |
/* init basic PC hardware */ |
| 424 | 423 |
pic = heathrow_pic_init(&heathrow_pic_mem_index); |
| 425 | 424 |
set_irq = heathrow_pic_set_irq; |
| ... | ... | |
| 463 | 462 |
isa_mem_base = 0x80000000; |
| 464 | 463 |
|
| 465 | 464 |
/* Register 8 MB of ISA IO space */ |
| 466 |
PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL); |
|
| 467 |
cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory); |
|
| 465 |
isa_mmio_init(0xf2000000, 0x00800000); |
|
| 468 | 466 |
|
| 469 | 467 |
/* UniN init */ |
| 470 | 468 |
unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL); |
| b/vl.h | ||
|---|---|---|
| 675 | 675 |
IOPortWriteFunc *func, void *opaque); |
| 676 | 676 |
void isa_unassign_ioport(int start, int length); |
| 677 | 677 |
|
| 678 |
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size); |
|
| 679 |
|
|
| 678 | 680 |
/* PCI bus */ |
| 679 | 681 |
|
| 680 | 682 |
extern target_phys_addr_t pci_mem_base; |
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