Revision af12906f target-ppc/translate.c
b/target-ppc/translate.c | ||
---|---|---|
75 | 75 |
#else |
76 | 76 |
static TCGv_i64 cpu_T64[3]; |
77 | 77 |
#endif |
78 |
static TCGv_i64 cpu_FT[3];
|
|
78 |
static TCGv_i64 cpu_FT[2];
|
|
79 | 79 |
static TCGv_i64 cpu_AVRh[3], cpu_AVRl[3]; |
80 | 80 |
|
81 | 81 |
#include "gen-icount.h" |
... | ... | |
120 | 120 |
offsetof(CPUState, ft0), "FT0"); |
121 | 121 |
cpu_FT[1] = tcg_global_mem_new_i64(TCG_AREG0, |
122 | 122 |
offsetof(CPUState, ft1), "FT1"); |
123 |
cpu_FT[2] = tcg_global_mem_new_i64(TCG_AREG0, |
|
124 |
offsetof(CPUState, ft2), "FT2"); |
|
125 | 123 |
|
126 | 124 |
cpu_AVRh[0] = tcg_global_mem_new_i64(TCG_AREG0, |
127 | 125 |
offsetof(CPUState, avr0.u64[0]), "AVR0H"); |
... | ... | |
245 | 243 |
#endif |
246 | 244 |
} |
247 | 245 |
|
248 |
static always_inline void gen_compute_fprf (int set_fprf, int set_rc) |
|
246 |
static always_inline void gen_compute_fprf (TCGv arg, int set_fprf, int set_rc)
|
|
249 | 247 |
{ |
248 |
TCGv t0 = tcg_temp_new_i32(); |
|
249 |
|
|
250 | 250 |
if (set_fprf != 0) { |
251 | 251 |
/* This case might be optimized later */ |
252 | 252 |
#if defined(OPTIMIZE_FPRF_UPDATE) |
253 | 253 |
*gen_fprf_ptr++ = gen_opc_ptr; |
254 | 254 |
#endif |
255 |
gen_op_compute_fprf(1); |
|
255 |
tcg_gen_movi_tl(t0, 1); |
|
256 |
gen_helper_compute_fprf(t0, arg, t0); |
|
256 | 257 |
if (unlikely(set_rc)) { |
257 |
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_T[0]); |
|
258 |
tcg_gen_andi_i32(cpu_crf[1], cpu_crf[1], 0xf); |
|
258 |
tcg_gen_movi_i32(cpu_crf[1], t0); |
|
259 | 259 |
} |
260 |
gen_op_float_check_status();
|
|
260 |
gen_helper_float_check_status();
|
|
261 | 261 |
} else if (unlikely(set_rc)) { |
262 | 262 |
/* We always need to compute fpcc */ |
263 |
gen_op_compute_fprf(0);
|
|
264 |
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_T[0]);
|
|
265 |
tcg_gen_andi_i32(cpu_crf[1], cpu_crf[1], 0xf);
|
|
263 |
tcg_gen_movi_tl(t0, 0);
|
|
264 |
gen_helper_compute_fprf(t0, arg, t0);
|
|
265 |
tcg_gen_movi_i32(cpu_crf[1], t0);
|
|
266 | 266 |
if (set_fprf) |
267 |
gen_op_float_check_status();
|
|
267 |
gen_helper_float_check_status();
|
|
268 | 268 |
} |
269 |
|
|
270 |
tcg_temp_free(t0); |
|
269 | 271 |
} |
270 | 272 |
|
271 | 273 |
static always_inline void gen_optimize_fprf (void) |
... | ... | |
2096 | 2098 |
GEN_EXCP_NO_FP(ctx); \ |
2097 | 2099 |
return; \ |
2098 | 2100 |
} \ |
2099 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \ |
|
2100 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \ |
|
2101 |
tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \ |
|
2102 | 2101 |
gen_reset_fpstatus(); \ |
2103 |
gen_op_f##op(); \ |
|
2102 |
gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
|
2103 |
cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
|
2104 | 2104 |
if (isfloat) { \ |
2105 |
gen_op_frsp(); \
|
|
2105 |
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
|
|
2106 | 2106 |
} \ |
2107 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
2108 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
|
2107 |
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
|
|
2108 |
Rc(ctx->opcode) != 0); \
|
|
2109 | 2109 |
} |
2110 | 2110 |
|
2111 | 2111 |
#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
... | ... | |
2119 | 2119 |
GEN_EXCP_NO_FP(ctx); \ |
2120 | 2120 |
return; \ |
2121 | 2121 |
} \ |
2122 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \ |
|
2123 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \ |
|
2124 | 2122 |
gen_reset_fpstatus(); \ |
2125 |
gen_op_f##op(); \ |
|
2123 |
gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
|
2124 |
cpu_fpr[rB(ctx->opcode)]); \ |
|
2126 | 2125 |
if (isfloat) { \ |
2127 |
gen_op_frsp(); \
|
|
2126 |
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
|
|
2128 | 2127 |
} \ |
2129 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
2130 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
|
2128 |
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
|
|
2129 |
set_fprf, Rc(ctx->opcode) != 0); \
|
|
2131 | 2130 |
} |
2132 | 2131 |
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
2133 | 2132 |
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
... | ... | |
2140 | 2139 |
GEN_EXCP_NO_FP(ctx); \ |
2141 | 2140 |
return; \ |
2142 | 2141 |
} \ |
2143 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \ |
|
2144 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \ |
|
2145 | 2142 |
gen_reset_fpstatus(); \ |
2146 |
gen_op_f##op(); \ |
|
2143 |
gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
|
2144 |
cpu_fpr[rC(ctx->opcode)]); \ |
|
2147 | 2145 |
if (isfloat) { \ |
2148 |
gen_op_frsp(); \
|
|
2146 |
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
|
|
2149 | 2147 |
} \ |
2150 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
2151 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
|
2148 |
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
|
|
2149 |
set_fprf, Rc(ctx->opcode) != 0); \
|
|
2152 | 2150 |
} |
2153 | 2151 |
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
2154 | 2152 |
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
... | ... | |
2161 | 2159 |
GEN_EXCP_NO_FP(ctx); \ |
2162 | 2160 |
return; \ |
2163 | 2161 |
} \ |
2164 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \ |
|
2165 | 2162 |
gen_reset_fpstatus(); \ |
2166 |
gen_op_f##name(); \
|
|
2167 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
2168 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
|
2163 |
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
|
|
2164 |
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
|
|
2165 |
set_fprf, Rc(ctx->opcode) != 0); \
|
|
2169 | 2166 |
} |
2170 | 2167 |
|
2171 | 2168 |
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
... | ... | |
2175 | 2172 |
GEN_EXCP_NO_FP(ctx); \ |
2176 | 2173 |
return; \ |
2177 | 2174 |
} \ |
2178 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \ |
|
2179 | 2175 |
gen_reset_fpstatus(); \ |
2180 |
gen_op_f##name(); \
|
|
2181 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
2182 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
|
2176 |
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
|
|
2177 |
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
|
|
2178 |
set_fprf, Rc(ctx->opcode) != 0); \
|
|
2183 | 2179 |
} |
2184 | 2180 |
|
2185 | 2181 |
/* fadd - fadds */ |
... | ... | |
2199 | 2195 |
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2200 | 2196 |
|
2201 | 2197 |
/* frsqrtes */ |
2202 |
static always_inline void gen_op_frsqrtes (void)
|
|
2198 |
GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
|
|
2203 | 2199 |
{ |
2204 |
gen_op_frsqrte(); |
|
2205 |
gen_op_frsp(); |
|
2200 |
if (unlikely(!ctx->fpu_enabled)) { |
|
2201 |
GEN_EXCP_NO_FP(ctx); |
|
2202 |
return; |
|
2203 |
} |
|
2204 |
gen_reset_fpstatus(); |
|
2205 |
gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
|
2206 |
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); |
|
2207 |
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
|
2206 | 2208 |
} |
2207 |
GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES); |
|
2208 | 2209 |
|
2209 | 2210 |
/* fsel */ |
2210 | 2211 |
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
... | ... | |
2218 | 2219 |
GEN_EXCP_NO_FP(ctx); |
2219 | 2220 |
return; |
2220 | 2221 |
} |
2221 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); |
|
2222 | 2222 |
gen_reset_fpstatus(); |
2223 |
gen_op_fsqrt(); |
|
2224 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); |
|
2225 |
gen_compute_fprf(1, Rc(ctx->opcode) != 0); |
|
2223 |
gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
|
2224 |
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
|
2226 | 2225 |
} |
2227 | 2226 |
|
2228 | 2227 |
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) |
... | ... | |
2231 | 2230 |
GEN_EXCP_NO_FP(ctx); |
2232 | 2231 |
return; |
2233 | 2232 |
} |
2234 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); |
|
2235 | 2233 |
gen_reset_fpstatus(); |
2236 |
gen_op_fsqrt(); |
|
2237 |
gen_op_frsp(); |
|
2238 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); |
|
2239 |
gen_compute_fprf(1, Rc(ctx->opcode) != 0); |
|
2234 |
gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
|
2235 |
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); |
|
2236 |
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
|
2240 | 2237 |
} |
2241 | 2238 |
|
2242 | 2239 |
/*** Floating-Point multiply-and-add ***/ |
... | ... | |
2282 | 2279 |
GEN_EXCP_NO_FP(ctx); |
2283 | 2280 |
return; |
2284 | 2281 |
} |
2285 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); |
|
2286 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); |
|
2287 | 2282 |
gen_reset_fpstatus(); |
2288 |
gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)]); |
|
2289 |
gen_op_float_check_status(); |
|
2283 |
gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)], |
|
2284 |
cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
|
2285 |
gen_helper_float_check_status(); |
|
2290 | 2286 |
} |
2291 | 2287 |
|
2292 | 2288 |
/* fcmpu */ |
... | ... | |
2296 | 2292 |
GEN_EXCP_NO_FP(ctx); |
2297 | 2293 |
return; |
2298 | 2294 |
} |
2299 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); |
|
2300 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); |
|
2301 | 2295 |
gen_reset_fpstatus(); |
2302 |
gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)]); |
|
2303 |
gen_op_float_check_status(); |
|
2296 |
gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)], |
|
2297 |
cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
|
2298 |
gen_helper_float_check_status(); |
|
2304 | 2299 |
} |
2305 | 2300 |
|
2306 | 2301 |
/*** Floating-point move ***/ |
... | ... | |
2316 | 2311 |
GEN_EXCP_NO_FP(ctx); |
2317 | 2312 |
return; |
2318 | 2313 |
} |
2319 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); |
|
2320 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); |
|
2321 |
gen_compute_fprf(0, Rc(ctx->opcode) != 0); |
|
2314 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
|
2315 |
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
|
2322 | 2316 |
} |
2323 | 2317 |
|
2324 | 2318 |
/* fnabs */ |
... | ... | |
2342 | 2336 |
bfa = 4 * (7 - crfS(ctx->opcode)); |
2343 | 2337 |
tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa); |
2344 | 2338 |
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); |
2345 |
gen_op_fpscr_resetbit(~(0xF << bfa));
|
|
2339 |
tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
|
|
2346 | 2340 |
} |
2347 | 2341 |
|
2348 | 2342 |
/* mffs */ |
... | ... | |
2354 | 2348 |
} |
2355 | 2349 |
gen_optimize_fprf(); |
2356 | 2350 |
gen_reset_fpstatus(); |
2357 |
gen_op_load_fpscr_FT0(); |
|
2358 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); |
|
2359 |
gen_compute_fprf(0, Rc(ctx->opcode) != 0); |
|
2351 |
tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
|
2352 |
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
|
2360 | 2353 |
} |
2361 | 2354 |
|
2362 | 2355 |
/* mtfsb0 */ |
... | ... | |
2372 | 2365 |
gen_optimize_fprf(); |
2373 | 2366 |
gen_reset_fpstatus(); |
2374 | 2367 |
if (likely(crb != 30 && crb != 29)) |
2375 |
gen_op_fpscr_resetbit(~(1 << crb));
|
|
2368 |
tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
|
|
2376 | 2369 |
if (unlikely(Rc(ctx->opcode) != 0)) { |
2377 | 2370 |
tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
2378 | 2371 |
} |
... | ... | |
2391 | 2384 |
gen_optimize_fprf(); |
2392 | 2385 |
gen_reset_fpstatus(); |
2393 | 2386 |
/* XXX: we pretend we can only do IEEE floating-point computations */ |
2394 |
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) |
|
2395 |
gen_op_fpscr_setbit(crb); |
|
2387 |
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
|
2388 |
TCGv t0 = tcg_const_tl(crb); |
|
2389 |
gen_helper_fpscr_setbit(t0); |
|
2390 |
tcg_temp_free(t0); |
|
2391 |
} |
|
2396 | 2392 |
if (unlikely(Rc(ctx->opcode) != 0)) { |
2397 | 2393 |
tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
2398 | 2394 |
} |
2399 | 2395 |
/* We can raise a differed exception */ |
2400 |
gen_op_float_check_status();
|
|
2396 |
gen_helper_float_check_status();
|
|
2401 | 2397 |
} |
2402 | 2398 |
|
2403 | 2399 |
/* mtfsf */ |
2404 | 2400 |
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) |
2405 | 2401 |
{ |
2402 |
TCGv t0; |
|
2403 |
|
|
2406 | 2404 |
if (unlikely(!ctx->fpu_enabled)) { |
2407 | 2405 |
GEN_EXCP_NO_FP(ctx); |
2408 | 2406 |
return; |
2409 | 2407 |
} |
2410 | 2408 |
gen_optimize_fprf(); |
2411 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); |
|
2412 | 2409 |
gen_reset_fpstatus(); |
2413 |
gen_op_store_fpscr(FM(ctx->opcode)); |
|
2410 |
t0 = tcg_const_i32(FM(ctx->opcode)); |
|
2411 |
gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0); |
|
2412 |
tcg_temp_free(t0); |
|
2414 | 2413 |
if (unlikely(Rc(ctx->opcode) != 0)) { |
2415 | 2414 |
tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
2416 | 2415 |
} |
2417 | 2416 |
/* We can raise a differed exception */ |
2418 |
gen_op_float_check_status();
|
|
2417 |
gen_helper_float_check_status();
|
|
2419 | 2418 |
} |
2420 | 2419 |
|
2421 | 2420 |
/* mtfsfi */ |
2422 | 2421 |
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) |
2423 | 2422 |
{ |
2424 | 2423 |
int bf, sh; |
2424 |
TCGv t0, t1; |
|
2425 | 2425 |
|
2426 | 2426 |
if (unlikely(!ctx->fpu_enabled)) { |
2427 | 2427 |
GEN_EXCP_NO_FP(ctx); |
... | ... | |
2430 | 2430 |
bf = crbD(ctx->opcode) >> 2; |
2431 | 2431 |
sh = 7 - bf; |
2432 | 2432 |
gen_optimize_fprf(); |
2433 |
tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh)); |
|
2434 | 2433 |
gen_reset_fpstatus(); |
2435 |
gen_op_store_fpscr(1 << sh); |
|
2434 |
t0 = tcg_const_tl(FPIMM(ctx->opcode) << (4 * sh)); |
|
2435 |
t1 = tcg_const_i32(1 << sh); |
|
2436 |
gen_helper_store_fpscr(t0, t1); |
|
2437 |
tcg_temp_free(t0); |
|
2438 |
tcg_temp_free(t1); |
|
2436 | 2439 |
if (unlikely(Rc(ctx->opcode) != 0)) { |
2437 | 2440 |
tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
2438 | 2441 |
} |
2439 | 2442 |
/* We can raise a differed exception */ |
2440 |
gen_op_float_check_status();
|
|
2443 |
gen_helper_float_check_status();
|
|
2441 | 2444 |
} |
2442 | 2445 |
|
2443 | 2446 |
/*** Addressing modes ***/ |
Also available in: Unified diff