Revision af7bf89b target-sparc/cpu.h

b/target-sparc/cpu.h
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#ifndef CPU_SPARC_H
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#define CPU_SPARC_H
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#include "config.h"
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#if !defined(TARGET_SPARC64)
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#define TARGET_LONG_BITS 32
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#define TARGET_FPREGS 32
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#define TARGET_FPREG_T float
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#else
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#define TARGET_LONG_BITS 64
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#define TARGET_FPREGS 64
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#define TARGET_FPREG_T double
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#endif
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#include "cpu-defs.h"
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......
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#define NWINDOWS  32
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typedef struct CPUSPARCState {
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    uint32_t gregs[8]; /* general registers */
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    uint32_t *regwptr; /* pointer to current register window */
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    float    fpr[32];  /* floating point registers */
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    uint32_t pc;       /* program counter */
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    uint32_t npc;      /* next program counter */
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    uint32_t y;        /* multiply/divide register */
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    target_ulong gregs[8]; /* general registers */
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    target_ulong *regwptr; /* pointer to current register window */
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    TARGET_FPREG_T    fpr[TARGET_FPREGS];  /* floating point registers */
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    target_ulong pc;       /* program counter */
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    target_ulong npc;      /* next program counter */
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    target_ulong y;        /* multiply/divide register */
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    uint32_t psr;      /* processor state register */
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    uint32_t fsr;      /* FPU state register */
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    uint32_t T2;
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    uint32_t cwp;      /* index of current register window (extracted
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                          from PSR) */
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    uint32_t wim;      /* window invalid mask */
......
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    int exception_index;
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    int interrupt_index;
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    int interrupt_request;
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    uint32_t exception_next_pc;
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    target_ulong exception_next_pc;
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    struct TranslationBlock *current_tb;
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    void *opaque;
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    /* NOTE: we allow 8 more registers to handle wrapping */
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    uint32_t regbase[NWINDOWS * 16 + 8];
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    target_ulong regbase[NWINDOWS * 16 + 8];
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    /* in order to avoid passing too many arguments to the memory
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       write helpers, we store some rarely used information in the CPU
......
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    /* temporary float registers */
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    float ft0, ft1, ft2;
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    double dt0, dt1, dt2;
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#if defined(TARGET_SPARC64)
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    target_ulong t0, t1, t2;
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#endif
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    /* ice debug support */
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    uint32_t breakpoints[MAX_BREAKPOINTS];
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    target_ulong breakpoints[MAX_BREAKPOINTS];
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    int nb_breakpoints;
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    int singlestep_enabled; /* XXX: should use CPU single step mode instead */
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......
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double cpu_put_fp64(uint64_t mant, uint16_t exp);
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/* Fake impl 0, version 4 */
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#define GET_PSR(env) ((0 << 28) | (4 << 24) | env->psr |		\
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#define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) |	\
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		      (env->psref? PSR_EF : 0) |			\
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		      (env->psrpil << 8) |				\
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		      (env->psrs? PSR_S : 0) |				\
......
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#endif
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#define PUT_PSR(env, val) do { int _tmp = val;				\
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	env->psr = _tmp & ~PSR_ICC;					\
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	env->psr = _tmp & PSR_ICC;					\
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	env->psref = (_tmp & PSR_EF)? 1 : 0;				\
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	env->psrpil = (_tmp & PSR_PIL) >> 8;				\
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	env->psrs = (_tmp & PSR_S)? 1 : 0;				\

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