Revision af92284b

b/hw/vga.c
522 522
    VGACommonState *s = opaque;
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    uint32_t val;
524 524

  
525
    if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
525
    if (s->vbe_index < VBE_DISPI_INDEX_NB) {
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        if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
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            switch(s->vbe_index) {
528 528
                /* XXX: do not hardcode ? */
......
542 542
        } else {
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            val = s->vbe_regs[s->vbe_index];
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        }
545
    } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
546
        val = s->vram_size / (64 * 1024);
545 547
    } else {
546 548
        val = 0;
547 549
    }
......
1955 1957
#ifdef CONFIG_BOCHS_VBE
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    s->vbe_index = 0;
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    memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1958
    s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
1960
    s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
1959 1961
    s->vbe_start_addr = 0;
1960 1962
    s->vbe_line_offset = 0;
1961 1963
    s->vbe_bank_mask = (s->vram_size >> 16) - 1;
b/hw/vga_int.h
47 47
#define VBE_DISPI_INDEX_VIRT_HEIGHT     0x7
48 48
#define VBE_DISPI_INDEX_X_OFFSET        0x8
49 49
#define VBE_DISPI_INDEX_Y_OFFSET        0x9
50
#define VBE_DISPI_INDEX_NB              0xa
50
#define VBE_DISPI_INDEX_NB              0xa /* size of vbe_regs[] */
51
#define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa /* read-only, not in vbe_regs */
51 52

  
52 53
#define VBE_DISPI_ID0                   0xB0C0
53 54
#define VBE_DISPI_ID1                   0xB0C1
54 55
#define VBE_DISPI_ID2                   0xB0C2
55 56
#define VBE_DISPI_ID3                   0xB0C3
56 57
#define VBE_DISPI_ID4                   0xB0C4
58
#define VBE_DISPI_ID5                   0xB0C5
57 59

  
58 60
#define VBE_DISPI_DISABLED              0x00
59 61
#define VBE_DISPI_ENABLED               0x01

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