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/*
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* Copyright (C) 2010 Red Hat, Inc.
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*
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* written by Gerd Hoffmann <kraxel@redhat.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "qemu-timer.h" |
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#include "audiodev.h" |
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#include "intel-hda.h" |
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#include "intel-hda-defs.h" |
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|
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/* --------------------------------------------------------------------- */
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/* hda bus */
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|
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static struct BusInfo hda_codec_bus_info = { |
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.name = "HDA",
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.size = sizeof(HDACodecBus),
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.props = (Property[]) {
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DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), |
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DEFINE_PROP_END_OF_LIST() |
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} |
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}; |
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|
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void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
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hda_codec_response_func response, |
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hda_codec_xfer_func xfer) |
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{
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qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL);
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bus->response = response; |
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bus->xfer = xfer; |
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} |
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|
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static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo *base) |
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{
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HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus); |
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HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
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HDACodecDeviceInfo *info = DO_UPCAST(HDACodecDeviceInfo, qdev, base); |
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|
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dev->info = info; |
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if (dev->cad == -1) { |
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dev->cad = bus->next_cad; |
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} |
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if (dev->cad > 15) |
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return -1; |
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bus->next_cad = dev->cad + 1;
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return info->init(dev);
|
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} |
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|
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static int hda_codec_dev_exit(DeviceState *qdev) |
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{
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HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
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|
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if (dev->info->exit) {
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dev->info->exit(dev); |
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} |
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return 0; |
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} |
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|
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void hda_codec_register(HDACodecDeviceInfo *info)
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{
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info->qdev.init = hda_codec_dev_init; |
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info->qdev.exit = hda_codec_dev_exit; |
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info->qdev.bus_info = &hda_codec_bus_info; |
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qdev_register(&info->qdev); |
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} |
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|
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HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) |
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{
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DeviceState *qdev; |
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HDACodecDevice *cdev; |
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|
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QLIST_FOREACH(qdev, &bus->qbus.children, sibling) {
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cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
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if (cdev->cad == cad) {
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return cdev;
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} |
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} |
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return NULL; |
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} |
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|
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void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) |
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{
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HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
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bus->response(dev, solicited, response); |
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} |
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|
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bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, |
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uint8_t *buf, uint32_t len) |
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{
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HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
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return bus->xfer(dev, stnr, output, buf, len);
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} |
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|
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/* --------------------------------------------------------------------- */
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/* intel hda emulation */
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|
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typedef struct IntelHDAStream IntelHDAStream; |
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typedef struct IntelHDAState IntelHDAState; |
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typedef struct IntelHDAReg IntelHDAReg; |
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|
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typedef struct bpl { |
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uint64_t addr; |
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uint32_t len; |
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uint32_t flags; |
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} bpl; |
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|
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struct IntelHDAStream {
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/* registers */
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uint32_t ctl; |
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uint32_t lpib; |
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uint32_t cbl; |
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uint32_t lvi; |
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uint32_t fmt; |
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uint32_t bdlp_lbase; |
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uint32_t bdlp_ubase; |
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|
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/* state */
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bpl *bpl; |
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uint32_t bentries; |
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uint32_t bsize, be, bp; |
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}; |
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|
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struct IntelHDAState {
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PCIDevice pci; |
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const char *name; |
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HDACodecBus codecs; |
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|
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/* registers */
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uint32_t g_ctl; |
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uint32_t wake_en; |
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uint32_t state_sts; |
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uint32_t int_ctl; |
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uint32_t int_sts; |
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uint32_t wall_clk; |
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|
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uint32_t corb_lbase; |
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uint32_t corb_ubase; |
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uint32_t corb_rp; |
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uint32_t corb_wp; |
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uint32_t corb_ctl; |
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uint32_t corb_sts; |
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uint32_t corb_size; |
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|
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uint32_t rirb_lbase; |
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uint32_t rirb_ubase; |
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uint32_t rirb_wp; |
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uint32_t rirb_cnt; |
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uint32_t rirb_ctl; |
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uint32_t rirb_sts; |
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uint32_t rirb_size; |
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|
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uint32_t dp_lbase; |
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uint32_t dp_ubase; |
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|
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uint32_t icw; |
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uint32_t irr; |
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uint32_t ics; |
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|
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/* streams */
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IntelHDAStream st[8];
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|
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/* state */
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int mmio_addr;
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uint32_t rirb_count; |
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int64_t wall_base_ns; |
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|
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/* debug logging */
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const IntelHDAReg *last_reg;
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uint32_t last_val; |
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uint32_t last_write; |
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uint32_t last_sec; |
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uint32_t repeat_count; |
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|
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/* properties */
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uint32_t debug; |
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}; |
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|
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struct IntelHDAReg {
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const char *name; /* register name */ |
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uint32_t size; /* size in bytes */
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uint32_t reset; /* reset value */
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uint32_t wmask; /* write mask */
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uint32_t wclear; /* write 1 to clear bits */
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uint32_t offset; /* location in IntelHDAState */
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uint32_t shift; /* byte access entries for dwords */
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uint32_t stream; |
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void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); |
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void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); |
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}; |
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|
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static void intel_hda_reset(DeviceState *dev); |
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|
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/* --------------------------------------------------------------------- */
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static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
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{
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target_phys_addr_t addr; |
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#if TARGET_PHYS_ADDR_BITS == 32 |
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addr = lbase; |
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#else
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addr = ubase; |
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addr <<= 32;
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addr |= lbase; |
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#endif
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return addr;
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} |
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static void stl_phys_le(target_phys_addr_t addr, uint32_t value) |
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{
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uint32_t value_le = cpu_to_le32(value); |
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cpu_physical_memory_write(addr, (uint8_t*)(&value_le), sizeof(value_le));
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} |
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static uint32_t ldl_phys_le(target_phys_addr_t addr)
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{
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uint32_t value_le; |
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cpu_physical_memory_read(addr, (uint8_t*)(&value_le), sizeof(value_le));
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return le32_to_cpu(value_le);
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} |
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|
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static void intel_hda_update_int_sts(IntelHDAState *d) |
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{
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uint32_t sts = 0;
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uint32_t i; |
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/* update controller status */
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if (d->rirb_sts & ICH6_RBSTS_IRQ) {
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sts |= (1 << 30); |
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} |
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if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
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sts |= (1 << 30); |
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} |
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if (d->state_sts & d->wake_en) {
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sts |= (1 << 30); |
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} |
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|
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/* update stream status */
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for (i = 0; i < 8; i++) { |
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/* buffer completion interrupt */
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if (d->st[i].ctl & (1 << 26)) { |
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sts |= (1 << i);
|
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} |
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} |
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|
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/* update global status */
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if (sts & d->int_ctl) {
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sts |= (1 << 31); |
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} |
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|
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d->int_sts = sts; |
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} |
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|
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static void intel_hda_update_irq(IntelHDAState *d) |
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{
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int level;
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|
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intel_hda_update_int_sts(d); |
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if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) { |
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level = 1;
|
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} else {
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level = 0;
|
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} |
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dprint(d, 2, "%s: level %d\n", __FUNCTION__, level); |
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qemu_set_irq(d->pci.irq[0], level);
|
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} |
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|
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static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) |
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{
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uint32_t cad, nid, data; |
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HDACodecDevice *codec; |
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|
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cad = (verb >> 28) & 0x0f; |
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if (verb & (1 << 27)) { |
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/* indirect node addressing, not specified in HDA 1.0 */
|
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dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__); |
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return -1; |
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} |
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nid = (verb >> 20) & 0x7f; |
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data = verb & 0xfffff;
|
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|
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codec = hda_codec_find(&d->codecs, cad); |
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if (codec == NULL) { |
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dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__); |
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return -1; |
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} |
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codec->info->command(codec, nid, data); |
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return 0; |
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} |
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|
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static void intel_hda_corb_run(IntelHDAState *d) |
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{
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target_phys_addr_t addr; |
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uint32_t rp, verb; |
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|
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if (d->ics & ICH6_IRS_BUSY) {
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dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw); |
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intel_hda_send_command(d, d->icw); |
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return;
|
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} |
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|
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for (;;) {
|
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if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
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dprint(d, 2, "%s: !run\n", __FUNCTION__); |
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return;
|
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} |
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if ((d->corb_rp & 0xff) == d->corb_wp) { |
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dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__); |
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return;
|
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} |
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if (d->rirb_count == d->rirb_cnt) {
|
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dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__); |
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return;
|
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} |
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|
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rp = (d->corb_rp + 1) & 0xff; |
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addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); |
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verb = ldl_phys_le(addr + 4*rp);
|
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d->corb_rp = rp; |
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|
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dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb); |
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intel_hda_send_command(d, verb); |
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} |
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} |
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|
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static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) |
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{
|
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HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
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IntelHDAState *d = container_of(bus, IntelHDAState, codecs); |
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target_phys_addr_t addr; |
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uint32_t wp, ex; |
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|
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if (d->ics & ICH6_IRS_BUSY) {
|
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dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", |
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__FUNCTION__, response, dev->cad); |
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d->irr = response; |
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d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
|
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d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
|
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return;
|
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} |
| 356 |
|
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if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
|
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dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__); |
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return;
|
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} |
| 361 |
|
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ex = (solicited ? 0 : (1 << 4)) | dev->cad; |
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wp = (d->rirb_wp + 1) & 0xff; |
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addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); |
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stl_phys_le(addr + 8*wp, response);
|
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stl_phys_le(addr + 8*wp + 4, ex); |
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d->rirb_wp = wp; |
| 368 |
|
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dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", |
| 370 |
__FUNCTION__, wp, response, ex); |
| 371 |
|
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d->rirb_count++; |
| 373 |
if (d->rirb_count == d->rirb_cnt) {
|
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dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count); |
| 375 |
if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
|
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d->rirb_sts |= ICH6_RBSTS_IRQ; |
| 377 |
intel_hda_update_irq(d); |
| 378 |
} |
| 379 |
} else if ((d->corb_rp & 0xff) == d->corb_wp) { |
| 380 |
dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__, |
| 381 |
d->rirb_count, d->rirb_cnt); |
| 382 |
if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
|
| 383 |
d->rirb_sts |= ICH6_RBSTS_IRQ; |
| 384 |
intel_hda_update_irq(d); |
| 385 |
} |
| 386 |
} |
| 387 |
} |
| 388 |
|
| 389 |
static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, |
| 390 |
uint8_t *buf, uint32_t len) |
| 391 |
{
|
| 392 |
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
| 393 |
IntelHDAState *d = container_of(bus, IntelHDAState, codecs); |
| 394 |
IntelHDAStream *st = NULL;
|
| 395 |
target_phys_addr_t addr; |
| 396 |
uint32_t s, copy, left; |
| 397 |
bool irq = false; |
| 398 |
|
| 399 |
for (s = 0; s < ARRAY_SIZE(d->st); s++) { |
| 400 |
if (stnr == ((d->st[s].ctl >> 20) & 0x0f)) { |
| 401 |
st = d->st + s; |
| 402 |
break;
|
| 403 |
} |
| 404 |
} |
| 405 |
if (st == NULL) { |
| 406 |
return false; |
| 407 |
} |
| 408 |
if (st->bpl == NULL) { |
| 409 |
return false; |
| 410 |
} |
| 411 |
if (st->ctl & (1 << 26)) { |
| 412 |
/*
|
| 413 |
* Wait with the next DMA xfer until the guest
|
| 414 |
* has acked the buffer completion interrupt
|
| 415 |
*/
|
| 416 |
return false; |
| 417 |
} |
| 418 |
|
| 419 |
left = len; |
| 420 |
while (left > 0) { |
| 421 |
copy = left; |
| 422 |
if (copy > st->bsize - st->lpib)
|
| 423 |
copy = st->bsize - st->lpib; |
| 424 |
if (copy > st->bpl[st->be].len - st->bp)
|
| 425 |
copy = st->bpl[st->be].len - st->bp; |
| 426 |
|
| 427 |
dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", |
| 428 |
st->be, st->bp, st->bpl[st->be].len, copy); |
| 429 |
|
| 430 |
cpu_physical_memory_rw(st->bpl[st->be].addr + st->bp, |
| 431 |
buf, copy, !output); |
| 432 |
st->lpib += copy; |
| 433 |
st->bp += copy; |
| 434 |
buf += copy; |
| 435 |
left -= copy; |
| 436 |
|
| 437 |
if (st->bpl[st->be].len == st->bp) {
|
| 438 |
/* bpl entry filled */
|
| 439 |
if (st->bpl[st->be].flags & 0x01) { |
| 440 |
irq = true;
|
| 441 |
} |
| 442 |
st->bp = 0;
|
| 443 |
st->be++; |
| 444 |
if (st->be == st->bentries) {
|
| 445 |
/* bpl wrap around */
|
| 446 |
st->be = 0;
|
| 447 |
st->lpib = 0;
|
| 448 |
} |
| 449 |
} |
| 450 |
} |
| 451 |
if (d->dp_lbase & 0x01) { |
| 452 |
addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
|
| 453 |
stl_phys_le(addr + 8*s, st->lpib);
|
| 454 |
} |
| 455 |
dprint(d, 3, "dma: --\n"); |
| 456 |
|
| 457 |
if (irq) {
|
| 458 |
st->ctl |= (1 << 26); /* buffer completion interrupt */ |
| 459 |
intel_hda_update_irq(d); |
| 460 |
} |
| 461 |
return true; |
| 462 |
} |
| 463 |
|
| 464 |
static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) |
| 465 |
{
|
| 466 |
target_phys_addr_t addr; |
| 467 |
uint8_t buf[16];
|
| 468 |
uint32_t i; |
| 469 |
|
| 470 |
addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); |
| 471 |
st->bentries = st->lvi +1;
|
| 472 |
qemu_free(st->bpl); |
| 473 |
st->bpl = qemu_malloc(sizeof(bpl) * st->bentries);
|
| 474 |
for (i = 0; i < st->bentries; i++, addr += 16) { |
| 475 |
cpu_physical_memory_read(addr, buf, 16);
|
| 476 |
st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); |
| 477 |
st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
|
| 478 |
st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
|
| 479 |
dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", |
| 480 |
i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); |
| 481 |
} |
| 482 |
|
| 483 |
st->bsize = st->cbl; |
| 484 |
st->lpib = 0;
|
| 485 |
st->be = 0;
|
| 486 |
st->bp = 0;
|
| 487 |
} |
| 488 |
|
| 489 |
static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running) |
| 490 |
{
|
| 491 |
DeviceState *qdev; |
| 492 |
HDACodecDevice *cdev; |
| 493 |
|
| 494 |
QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
|
| 495 |
cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
| 496 |
if (cdev->info->stream) {
|
| 497 |
cdev->info->stream(cdev, stream, running); |
| 498 |
} |
| 499 |
} |
| 500 |
} |
| 501 |
|
| 502 |
/* --------------------------------------------------------------------- */
|
| 503 |
|
| 504 |
static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 505 |
{
|
| 506 |
if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { |
| 507 |
intel_hda_reset(&d->pci.qdev); |
| 508 |
} |
| 509 |
} |
| 510 |
|
| 511 |
static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 512 |
{
|
| 513 |
intel_hda_update_irq(d); |
| 514 |
} |
| 515 |
|
| 516 |
static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 517 |
{
|
| 518 |
intel_hda_update_irq(d); |
| 519 |
} |
| 520 |
|
| 521 |
static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) |
| 522 |
{
|
| 523 |
int64_t ns; |
| 524 |
|
| 525 |
ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns; |
| 526 |
d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ |
| 527 |
} |
| 528 |
|
| 529 |
static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 530 |
{
|
| 531 |
intel_hda_corb_run(d); |
| 532 |
} |
| 533 |
|
| 534 |
static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 535 |
{
|
| 536 |
intel_hda_corb_run(d); |
| 537 |
} |
| 538 |
|
| 539 |
static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 540 |
{
|
| 541 |
if (d->rirb_wp & ICH6_RIRBWP_RST) {
|
| 542 |
d->rirb_wp = 0;
|
| 543 |
} |
| 544 |
} |
| 545 |
|
| 546 |
static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 547 |
{
|
| 548 |
intel_hda_update_irq(d); |
| 549 |
|
| 550 |
if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
|
| 551 |
/* cleared ICH6_RBSTS_IRQ */
|
| 552 |
d->rirb_count = 0;
|
| 553 |
intel_hda_corb_run(d); |
| 554 |
} |
| 555 |
} |
| 556 |
|
| 557 |
static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 558 |
{
|
| 559 |
if (d->ics & ICH6_IRS_BUSY) {
|
| 560 |
intel_hda_corb_run(d); |
| 561 |
} |
| 562 |
} |
| 563 |
|
| 564 |
static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 565 |
{
|
| 566 |
IntelHDAStream *st = d->st + reg->stream; |
| 567 |
|
| 568 |
if (st->ctl & 0x01) { |
| 569 |
/* reset */
|
| 570 |
dprint(d, 1, "st #%d: reset\n", reg->stream); |
| 571 |
st->ctl = 0;
|
| 572 |
} |
| 573 |
if ((st->ctl & 0x02) != (old & 0x02)) { |
| 574 |
uint32_t stnr = (st->ctl >> 20) & 0x0f; |
| 575 |
/* run bit flipped */
|
| 576 |
if (st->ctl & 0x02) { |
| 577 |
/* start */
|
| 578 |
dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", |
| 579 |
reg->stream, stnr, st->cbl); |
| 580 |
intel_hda_parse_bdl(d, st); |
| 581 |
intel_hda_notify_codecs(d, stnr, true);
|
| 582 |
} else {
|
| 583 |
/* stop */
|
| 584 |
dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); |
| 585 |
intel_hda_notify_codecs(d, stnr, false);
|
| 586 |
} |
| 587 |
} |
| 588 |
intel_hda_update_irq(d); |
| 589 |
} |
| 590 |
|
| 591 |
/* --------------------------------------------------------------------- */
|
| 592 |
|
| 593 |
#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) |
| 594 |
|
| 595 |
static const struct IntelHDAReg regtab[] = { |
| 596 |
/* global */
|
| 597 |
[ ICH6_REG_GCAP ] = {
|
| 598 |
.name = "GCAP",
|
| 599 |
.size = 2,
|
| 600 |
.reset = 0x4401,
|
| 601 |
}, |
| 602 |
[ ICH6_REG_VMIN ] = {
|
| 603 |
.name = "VMIN",
|
| 604 |
.size = 1,
|
| 605 |
}, |
| 606 |
[ ICH6_REG_VMAJ ] = {
|
| 607 |
.name = "VMAJ",
|
| 608 |
.size = 1,
|
| 609 |
.reset = 1,
|
| 610 |
}, |
| 611 |
[ ICH6_REG_OUTPAY ] = {
|
| 612 |
.name = "OUTPAY",
|
| 613 |
.size = 2,
|
| 614 |
.reset = 0x3c,
|
| 615 |
}, |
| 616 |
[ ICH6_REG_INPAY ] = {
|
| 617 |
.name = "INPAY",
|
| 618 |
.size = 2,
|
| 619 |
.reset = 0x1d,
|
| 620 |
}, |
| 621 |
[ ICH6_REG_GCTL ] = {
|
| 622 |
.name = "GCTL",
|
| 623 |
.size = 4,
|
| 624 |
.wmask = 0x0103,
|
| 625 |
.offset = offsetof(IntelHDAState, g_ctl), |
| 626 |
.whandler = intel_hda_set_g_ctl, |
| 627 |
}, |
| 628 |
[ ICH6_REG_WAKEEN ] = {
|
| 629 |
.name = "WAKEEN",
|
| 630 |
.size = 2,
|
| 631 |
.wmask = 0x3fff,
|
| 632 |
.offset = offsetof(IntelHDAState, wake_en), |
| 633 |
}, |
| 634 |
[ ICH6_REG_STATESTS ] = {
|
| 635 |
.name = "STATESTS",
|
| 636 |
.size = 2,
|
| 637 |
.wmask = 0x3fff,
|
| 638 |
.wclear = 0x3fff,
|
| 639 |
.offset = offsetof(IntelHDAState, state_sts), |
| 640 |
.whandler = intel_hda_set_state_sts, |
| 641 |
}, |
| 642 |
|
| 643 |
/* interrupts */
|
| 644 |
[ ICH6_REG_INTCTL ] = {
|
| 645 |
.name = "INTCTL",
|
| 646 |
.size = 4,
|
| 647 |
.wmask = 0xc00000ff,
|
| 648 |
.offset = offsetof(IntelHDAState, int_ctl), |
| 649 |
.whandler = intel_hda_set_int_ctl, |
| 650 |
}, |
| 651 |
[ ICH6_REG_INTSTS ] = {
|
| 652 |
.name = "INTSTS",
|
| 653 |
.size = 4,
|
| 654 |
.wmask = 0xc00000ff,
|
| 655 |
.wclear = 0xc00000ff,
|
| 656 |
.offset = offsetof(IntelHDAState, int_sts), |
| 657 |
}, |
| 658 |
|
| 659 |
/* misc */
|
| 660 |
[ ICH6_REG_WALLCLK ] = {
|
| 661 |
.name = "WALLCLK",
|
| 662 |
.size = 4,
|
| 663 |
.offset = offsetof(IntelHDAState, wall_clk), |
| 664 |
.rhandler = intel_hda_get_wall_clk, |
| 665 |
}, |
| 666 |
[ ICH6_REG_WALLCLK + 0x2000 ] = {
|
| 667 |
.name = "WALLCLK(alias)",
|
| 668 |
.size = 4,
|
| 669 |
.offset = offsetof(IntelHDAState, wall_clk), |
| 670 |
.rhandler = intel_hda_get_wall_clk, |
| 671 |
}, |
| 672 |
|
| 673 |
/* dma engine */
|
| 674 |
[ ICH6_REG_CORBLBASE ] = {
|
| 675 |
.name = "CORBLBASE",
|
| 676 |
.size = 4,
|
| 677 |
.wmask = 0xffffff80,
|
| 678 |
.offset = offsetof(IntelHDAState, corb_lbase), |
| 679 |
}, |
| 680 |
[ ICH6_REG_CORBUBASE ] = {
|
| 681 |
.name = "CORBUBASE",
|
| 682 |
.size = 4,
|
| 683 |
.wmask = 0xffffffff,
|
| 684 |
.offset = offsetof(IntelHDAState, corb_ubase), |
| 685 |
}, |
| 686 |
[ ICH6_REG_CORBWP ] = {
|
| 687 |
.name = "CORBWP",
|
| 688 |
.size = 2,
|
| 689 |
.wmask = 0xff,
|
| 690 |
.offset = offsetof(IntelHDAState, corb_wp), |
| 691 |
.whandler = intel_hda_set_corb_wp, |
| 692 |
}, |
| 693 |
[ ICH6_REG_CORBRP ] = {
|
| 694 |
.name = "CORBRP",
|
| 695 |
.size = 2,
|
| 696 |
.wmask = 0x80ff,
|
| 697 |
.offset = offsetof(IntelHDAState, corb_rp), |
| 698 |
}, |
| 699 |
[ ICH6_REG_CORBCTL ] = {
|
| 700 |
.name = "CORBCTL",
|
| 701 |
.size = 1,
|
| 702 |
.wmask = 0x03,
|
| 703 |
.offset = offsetof(IntelHDAState, corb_ctl), |
| 704 |
.whandler = intel_hda_set_corb_ctl, |
| 705 |
}, |
| 706 |
[ ICH6_REG_CORBSTS ] = {
|
| 707 |
.name = "CORBSTS",
|
| 708 |
.size = 1,
|
| 709 |
.wmask = 0x01,
|
| 710 |
.wclear = 0x01,
|
| 711 |
.offset = offsetof(IntelHDAState, corb_sts), |
| 712 |
}, |
| 713 |
[ ICH6_REG_CORBSIZE ] = {
|
| 714 |
.name = "CORBSIZE",
|
| 715 |
.size = 1,
|
| 716 |
.reset = 0x42,
|
| 717 |
.offset = offsetof(IntelHDAState, corb_size), |
| 718 |
}, |
| 719 |
[ ICH6_REG_RIRBLBASE ] = {
|
| 720 |
.name = "RIRBLBASE",
|
| 721 |
.size = 4,
|
| 722 |
.wmask = 0xffffff80,
|
| 723 |
.offset = offsetof(IntelHDAState, rirb_lbase), |
| 724 |
}, |
| 725 |
[ ICH6_REG_RIRBUBASE ] = {
|
| 726 |
.name = "RIRBUBASE",
|
| 727 |
.size = 4,
|
| 728 |
.wmask = 0xffffffff,
|
| 729 |
.offset = offsetof(IntelHDAState, rirb_ubase), |
| 730 |
}, |
| 731 |
[ ICH6_REG_RIRBWP ] = {
|
| 732 |
.name = "RIRBWP",
|
| 733 |
.size = 2,
|
| 734 |
.wmask = 0x8000,
|
| 735 |
.offset = offsetof(IntelHDAState, rirb_wp), |
| 736 |
.whandler = intel_hda_set_rirb_wp, |
| 737 |
}, |
| 738 |
[ ICH6_REG_RINTCNT ] = {
|
| 739 |
.name = "RINTCNT",
|
| 740 |
.size = 2,
|
| 741 |
.wmask = 0xff,
|
| 742 |
.offset = offsetof(IntelHDAState, rirb_cnt), |
| 743 |
}, |
| 744 |
[ ICH6_REG_RIRBCTL ] = {
|
| 745 |
.name = "RIRBCTL",
|
| 746 |
.size = 1,
|
| 747 |
.wmask = 0x07,
|
| 748 |
.offset = offsetof(IntelHDAState, rirb_ctl), |
| 749 |
}, |
| 750 |
[ ICH6_REG_RIRBSTS ] = {
|
| 751 |
.name = "RIRBSTS",
|
| 752 |
.size = 1,
|
| 753 |
.wmask = 0x05,
|
| 754 |
.wclear = 0x05,
|
| 755 |
.offset = offsetof(IntelHDAState, rirb_sts), |
| 756 |
.whandler = intel_hda_set_rirb_sts, |
| 757 |
}, |
| 758 |
[ ICH6_REG_RIRBSIZE ] = {
|
| 759 |
.name = "RIRBSIZE",
|
| 760 |
.size = 1,
|
| 761 |
.reset = 0x42,
|
| 762 |
.offset = offsetof(IntelHDAState, rirb_size), |
| 763 |
}, |
| 764 |
|
| 765 |
[ ICH6_REG_DPLBASE ] = {
|
| 766 |
.name = "DPLBASE",
|
| 767 |
.size = 4,
|
| 768 |
.wmask = 0xffffff81,
|
| 769 |
.offset = offsetof(IntelHDAState, dp_lbase), |
| 770 |
}, |
| 771 |
[ ICH6_REG_DPUBASE ] = {
|
| 772 |
.name = "DPUBASE",
|
| 773 |
.size = 4,
|
| 774 |
.wmask = 0xffffffff,
|
| 775 |
.offset = offsetof(IntelHDAState, dp_ubase), |
| 776 |
}, |
| 777 |
|
| 778 |
[ ICH6_REG_IC ] = {
|
| 779 |
.name = "ICW",
|
| 780 |
.size = 4,
|
| 781 |
.wmask = 0xffffffff,
|
| 782 |
.offset = offsetof(IntelHDAState, icw), |
| 783 |
}, |
| 784 |
[ ICH6_REG_IR ] = {
|
| 785 |
.name = "IRR",
|
| 786 |
.size = 4,
|
| 787 |
.offset = offsetof(IntelHDAState, irr), |
| 788 |
}, |
| 789 |
[ ICH6_REG_IRS ] = {
|
| 790 |
.name = "ICS",
|
| 791 |
.size = 2,
|
| 792 |
.wmask = 0x0003,
|
| 793 |
.wclear = 0x0002,
|
| 794 |
.offset = offsetof(IntelHDAState, ics), |
| 795 |
.whandler = intel_hda_set_ics, |
| 796 |
}, |
| 797 |
|
| 798 |
#define HDA_STREAM(_t, _i) \
|
| 799 |
[ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
|
| 800 |
.stream = _i, \ |
| 801 |
.name = _t stringify(_i) " CTL", \
|
| 802 |
.size = 4, \
|
| 803 |
.wmask = 0x1cff001f, \
|
| 804 |
.offset = offsetof(IntelHDAState, st[_i].ctl), \ |
| 805 |
.whandler = intel_hda_set_st_ctl, \ |
| 806 |
}, \ |
| 807 |
[ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
|
| 808 |
.stream = _i, \ |
| 809 |
.name = _t stringify(_i) " CTL(stnr)", \
|
| 810 |
.size = 1, \
|
| 811 |
.shift = 16, \
|
| 812 |
.wmask = 0x00ff0000, \
|
| 813 |
.offset = offsetof(IntelHDAState, st[_i].ctl), \ |
| 814 |
.whandler = intel_hda_set_st_ctl, \ |
| 815 |
}, \ |
| 816 |
[ ST_REG(_i, ICH6_REG_SD_STS)] = { \
|
| 817 |
.stream = _i, \ |
| 818 |
.name = _t stringify(_i) " CTL(sts)", \
|
| 819 |
.size = 1, \
|
| 820 |
.shift = 24, \
|
| 821 |
.wmask = 0x1c000000, \
|
| 822 |
.wclear = 0x1c000000, \
|
| 823 |
.offset = offsetof(IntelHDAState, st[_i].ctl), \ |
| 824 |
.whandler = intel_hda_set_st_ctl, \ |
| 825 |
}, \ |
| 826 |
[ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
|
| 827 |
.stream = _i, \ |
| 828 |
.name = _t stringify(_i) " LPIB", \
|
| 829 |
.size = 4, \
|
| 830 |
.offset = offsetof(IntelHDAState, st[_i].lpib), \ |
| 831 |
}, \ |
| 832 |
[ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
|
| 833 |
.stream = _i, \ |
| 834 |
.name = _t stringify(_i) " LPIB(alias)", \
|
| 835 |
.size = 4, \
|
| 836 |
.offset = offsetof(IntelHDAState, st[_i].lpib), \ |
| 837 |
}, \ |
| 838 |
[ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
|
| 839 |
.stream = _i, \ |
| 840 |
.name = _t stringify(_i) " CBL", \
|
| 841 |
.size = 4, \
|
| 842 |
.wmask = 0xffffffff, \
|
| 843 |
.offset = offsetof(IntelHDAState, st[_i].cbl), \ |
| 844 |
}, \ |
| 845 |
[ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
|
| 846 |
.stream = _i, \ |
| 847 |
.name = _t stringify(_i) " LVI", \
|
| 848 |
.size = 2, \
|
| 849 |
.wmask = 0x00ff, \
|
| 850 |
.offset = offsetof(IntelHDAState, st[_i].lvi), \ |
| 851 |
}, \ |
| 852 |
[ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
|
| 853 |
.stream = _i, \ |
| 854 |
.name = _t stringify(_i) " FIFOS", \
|
| 855 |
.size = 2, \
|
| 856 |
.reset = HDA_BUFFER_SIZE, \ |
| 857 |
}, \ |
| 858 |
[ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
|
| 859 |
.stream = _i, \ |
| 860 |
.name = _t stringify(_i) " FMT", \
|
| 861 |
.size = 2, \
|
| 862 |
.wmask = 0x7f7f, \
|
| 863 |
.offset = offsetof(IntelHDAState, st[_i].fmt), \ |
| 864 |
}, \ |
| 865 |
[ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
|
| 866 |
.stream = _i, \ |
| 867 |
.name = _t stringify(_i) " BDLPL", \
|
| 868 |
.size = 4, \
|
| 869 |
.wmask = 0xffffff80, \
|
| 870 |
.offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ |
| 871 |
}, \ |
| 872 |
[ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
|
| 873 |
.stream = _i, \ |
| 874 |
.name = _t stringify(_i) " BDLPU", \
|
| 875 |
.size = 4, \
|
| 876 |
.wmask = 0xffffffff, \
|
| 877 |
.offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ |
| 878 |
}, \ |
| 879 |
|
| 880 |
HDA_STREAM("IN", 0) |
| 881 |
HDA_STREAM("IN", 1) |
| 882 |
HDA_STREAM("IN", 2) |
| 883 |
HDA_STREAM("IN", 3) |
| 884 |
|
| 885 |
HDA_STREAM("OUT", 4) |
| 886 |
HDA_STREAM("OUT", 5) |
| 887 |
HDA_STREAM("OUT", 6) |
| 888 |
HDA_STREAM("OUT", 7) |
| 889 |
|
| 890 |
}; |
| 891 |
|
| 892 |
static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr) |
| 893 |
{
|
| 894 |
const IntelHDAReg *reg;
|
| 895 |
|
| 896 |
if (addr >= sizeof(regtab)/sizeof(regtab[0])) { |
| 897 |
goto noreg;
|
| 898 |
} |
| 899 |
reg = regtab+addr; |
| 900 |
if (reg->name == NULL) { |
| 901 |
goto noreg;
|
| 902 |
} |
| 903 |
return reg;
|
| 904 |
|
| 905 |
noreg:
|
| 906 |
dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); |
| 907 |
return NULL; |
| 908 |
} |
| 909 |
|
| 910 |
static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) |
| 911 |
{
|
| 912 |
uint8_t *addr = (void*)d;
|
| 913 |
|
| 914 |
addr += reg->offset; |
| 915 |
return (uint32_t*)addr;
|
| 916 |
} |
| 917 |
|
| 918 |
static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, |
| 919 |
uint32_t wmask) |
| 920 |
{
|
| 921 |
uint32_t *addr; |
| 922 |
uint32_t old; |
| 923 |
|
| 924 |
if (!reg) {
|
| 925 |
return;
|
| 926 |
} |
| 927 |
|
| 928 |
if (d->debug) {
|
| 929 |
time_t now = time(NULL);
|
| 930 |
if (d->last_write && d->last_reg == reg && d->last_val == val) {
|
| 931 |
d->repeat_count++; |
| 932 |
if (d->last_sec != now) {
|
| 933 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
| 934 |
d->last_sec = now; |
| 935 |
d->repeat_count = 0;
|
| 936 |
} |
| 937 |
} else {
|
| 938 |
if (d->repeat_count) {
|
| 939 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
| 940 |
} |
| 941 |
dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); |
| 942 |
d->last_write = 1;
|
| 943 |
d->last_reg = reg; |
| 944 |
d->last_val = val; |
| 945 |
d->last_sec = now; |
| 946 |
d->repeat_count = 0;
|
| 947 |
} |
| 948 |
} |
| 949 |
assert(reg->offset != 0);
|
| 950 |
|
| 951 |
addr = intel_hda_reg_addr(d, reg); |
| 952 |
old = *addr; |
| 953 |
|
| 954 |
if (reg->shift) {
|
| 955 |
val <<= reg->shift; |
| 956 |
wmask <<= reg->shift; |
| 957 |
} |
| 958 |
wmask &= reg->wmask; |
| 959 |
*addr &= ~wmask; |
| 960 |
*addr |= wmask & val; |
| 961 |
*addr &= ~(val & reg->wclear); |
| 962 |
|
| 963 |
if (reg->whandler) {
|
| 964 |
reg->whandler(d, reg, old); |
| 965 |
} |
| 966 |
} |
| 967 |
|
| 968 |
static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, |
| 969 |
uint32_t rmask) |
| 970 |
{
|
| 971 |
uint32_t *addr, ret; |
| 972 |
|
| 973 |
if (!reg) {
|
| 974 |
return 0; |
| 975 |
} |
| 976 |
|
| 977 |
if (reg->rhandler) {
|
| 978 |
reg->rhandler(d, reg); |
| 979 |
} |
| 980 |
|
| 981 |
if (reg->offset == 0) { |
| 982 |
/* constant read-only register */
|
| 983 |
ret = reg->reset; |
| 984 |
} else {
|
| 985 |
addr = intel_hda_reg_addr(d, reg); |
| 986 |
ret = *addr; |
| 987 |
if (reg->shift) {
|
| 988 |
ret >>= reg->shift; |
| 989 |
} |
| 990 |
ret &= rmask; |
| 991 |
} |
| 992 |
if (d->debug) {
|
| 993 |
time_t now = time(NULL);
|
| 994 |
if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
|
| 995 |
d->repeat_count++; |
| 996 |
if (d->last_sec != now) {
|
| 997 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
| 998 |
d->last_sec = now; |
| 999 |
d->repeat_count = 0;
|
| 1000 |
} |
| 1001 |
} else {
|
| 1002 |
if (d->repeat_count) {
|
| 1003 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
| 1004 |
} |
| 1005 |
dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); |
| 1006 |
d->last_write = 0;
|
| 1007 |
d->last_reg = reg; |
| 1008 |
d->last_val = ret; |
| 1009 |
d->last_sec = now; |
| 1010 |
d->repeat_count = 0;
|
| 1011 |
} |
| 1012 |
} |
| 1013 |
return ret;
|
| 1014 |
} |
| 1015 |
|
| 1016 |
static void intel_hda_regs_reset(IntelHDAState *d) |
| 1017 |
{
|
| 1018 |
uint32_t *addr; |
| 1019 |
int i;
|
| 1020 |
|
| 1021 |
for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) { |
| 1022 |
if (regtab[i].name == NULL) { |
| 1023 |
continue;
|
| 1024 |
} |
| 1025 |
if (regtab[i].offset == 0) { |
| 1026 |
continue;
|
| 1027 |
} |
| 1028 |
addr = intel_hda_reg_addr(d, regtab + i); |
| 1029 |
*addr = regtab[i].reset; |
| 1030 |
} |
| 1031 |
} |
| 1032 |
|
| 1033 |
/* --------------------------------------------------------------------- */
|
| 1034 |
|
| 1035 |
static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1036 |
{
|
| 1037 |
IntelHDAState *d = opaque; |
| 1038 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
| 1039 |
|
| 1040 |
intel_hda_reg_write(d, reg, val, 0xff);
|
| 1041 |
} |
| 1042 |
|
| 1043 |
static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1044 |
{
|
| 1045 |
IntelHDAState *d = opaque; |
| 1046 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
| 1047 |
|
| 1048 |
intel_hda_reg_write(d, reg, val, 0xffff);
|
| 1049 |
} |
| 1050 |
|
| 1051 |
static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1052 |
{
|
| 1053 |
IntelHDAState *d = opaque; |
| 1054 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
| 1055 |
|
| 1056 |
intel_hda_reg_write(d, reg, val, 0xffffffff);
|
| 1057 |
} |
| 1058 |
|
| 1059 |
static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr) |
| 1060 |
{
|
| 1061 |
IntelHDAState *d = opaque; |
| 1062 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
| 1063 |
|
| 1064 |
return intel_hda_reg_read(d, reg, 0xff); |
| 1065 |
} |
| 1066 |
|
| 1067 |
static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr) |
| 1068 |
{
|
| 1069 |
IntelHDAState *d = opaque; |
| 1070 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
| 1071 |
|
| 1072 |
return intel_hda_reg_read(d, reg, 0xffff); |
| 1073 |
} |
| 1074 |
|
| 1075 |
static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr) |
| 1076 |
{
|
| 1077 |
IntelHDAState *d = opaque; |
| 1078 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
| 1079 |
|
| 1080 |
return intel_hda_reg_read(d, reg, 0xffffffff); |
| 1081 |
} |
| 1082 |
|
| 1083 |
static CPUReadMemoryFunc * const intel_hda_mmio_read[3] = { |
| 1084 |
intel_hda_mmio_readb, |
| 1085 |
intel_hda_mmio_readw, |
| 1086 |
intel_hda_mmio_readl, |
| 1087 |
}; |
| 1088 |
|
| 1089 |
static CPUWriteMemoryFunc * const intel_hda_mmio_write[3] = { |
| 1090 |
intel_hda_mmio_writeb, |
| 1091 |
intel_hda_mmio_writew, |
| 1092 |
intel_hda_mmio_writel, |
| 1093 |
}; |
| 1094 |
|
| 1095 |
static void intel_hda_map(PCIDevice *pci, int region_num, |
| 1096 |
pcibus_t addr, pcibus_t size, int type)
|
| 1097 |
{
|
| 1098 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
| 1099 |
|
| 1100 |
cpu_register_physical_memory(addr, 0x4000, d->mmio_addr);
|
| 1101 |
} |
| 1102 |
|
| 1103 |
/* --------------------------------------------------------------------- */
|
| 1104 |
|
| 1105 |
static void intel_hda_reset(DeviceState *dev) |
| 1106 |
{
|
| 1107 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev); |
| 1108 |
DeviceState *qdev; |
| 1109 |
HDACodecDevice *cdev; |
| 1110 |
|
| 1111 |
intel_hda_regs_reset(d); |
| 1112 |
d->wall_base_ns = qemu_get_clock(vm_clock); |
| 1113 |
|
| 1114 |
/* reset codecs */
|
| 1115 |
QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
|
| 1116 |
cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
| 1117 |
if (qdev->info->reset) {
|
| 1118 |
qdev->info->reset(qdev); |
| 1119 |
} |
| 1120 |
d->state_sts |= (1 << cdev->cad);
|
| 1121 |
} |
| 1122 |
intel_hda_update_irq(d); |
| 1123 |
} |
| 1124 |
|
| 1125 |
static int intel_hda_init(PCIDevice *pci) |
| 1126 |
{
|
| 1127 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
| 1128 |
uint8_t *conf = d->pci.config; |
| 1129 |
|
| 1130 |
d->name = d->pci.qdev.info->name; |
| 1131 |
|
| 1132 |
pci_config_set_vendor_id(conf, PCI_VENDOR_ID_INTEL); |
| 1133 |
pci_config_set_device_id(conf, 0x2668);
|
| 1134 |
pci_config_set_revision(conf, 1);
|
| 1135 |
pci_config_set_class(conf, PCI_CLASS_MULTIMEDIA_HD_AUDIO); |
| 1136 |
pci_config_set_interrupt_pin(conf, 1);
|
| 1137 |
|
| 1138 |
/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
|
| 1139 |
conf[0x40] = 0x01; |
| 1140 |
|
| 1141 |
d->mmio_addr = cpu_register_io_memory(intel_hda_mmio_read, |
| 1142 |
intel_hda_mmio_write, d); |
| 1143 |
pci_register_bar(&d->pci, 0, 0x4000, PCI_BASE_ADDRESS_SPACE_MEMORY, |
| 1144 |
intel_hda_map); |
| 1145 |
|
| 1146 |
hda_codec_bus_init(&d->pci.qdev, &d->codecs, |
| 1147 |
intel_hda_response, intel_hda_xfer); |
| 1148 |
|
| 1149 |
return 0; |
| 1150 |
} |
| 1151 |
|
| 1152 |
static int intel_hda_exit(PCIDevice *pci) |
| 1153 |
{
|
| 1154 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
| 1155 |
|
| 1156 |
cpu_unregister_io_memory(d->mmio_addr); |
| 1157 |
return 0; |
| 1158 |
} |
| 1159 |
|
| 1160 |
static int intel_hda_post_load(void *opaque, int version) |
| 1161 |
{
|
| 1162 |
IntelHDAState* d = opaque; |
| 1163 |
int i;
|
| 1164 |
|
| 1165 |
dprint(d, 1, "%s\n", __FUNCTION__); |
| 1166 |
for (i = 0; i < ARRAY_SIZE(d->st); i++) { |
| 1167 |
if (d->st[i].ctl & 0x02) { |
| 1168 |
intel_hda_parse_bdl(d, &d->st[i]); |
| 1169 |
} |
| 1170 |
} |
| 1171 |
intel_hda_update_irq(d); |
| 1172 |
return 0; |
| 1173 |
} |
| 1174 |
|
| 1175 |
static const VMStateDescription vmstate_intel_hda_stream = { |
| 1176 |
.name = "intel-hda-stream",
|
| 1177 |
.version_id = 1,
|
| 1178 |
.fields = (VMStateField []) {
|
| 1179 |
VMSTATE_UINT32(ctl, IntelHDAStream), |
| 1180 |
VMSTATE_UINT32(lpib, IntelHDAStream), |
| 1181 |
VMSTATE_UINT32(cbl, IntelHDAStream), |
| 1182 |
VMSTATE_UINT32(lvi, IntelHDAStream), |
| 1183 |
VMSTATE_UINT32(fmt, IntelHDAStream), |
| 1184 |
VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), |
| 1185 |
VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), |
| 1186 |
VMSTATE_END_OF_LIST() |
| 1187 |
} |
| 1188 |
}; |
| 1189 |
|
| 1190 |
static const VMStateDescription vmstate_intel_hda = { |
| 1191 |
.name = "intel-hda",
|
| 1192 |
.version_id = 1,
|
| 1193 |
.post_load = intel_hda_post_load, |
| 1194 |
.fields = (VMStateField []) {
|
| 1195 |
VMSTATE_PCI_DEVICE(pci, IntelHDAState), |
| 1196 |
|
| 1197 |
/* registers */
|
| 1198 |
VMSTATE_UINT32(g_ctl, IntelHDAState), |
| 1199 |
VMSTATE_UINT32(wake_en, IntelHDAState), |
| 1200 |
VMSTATE_UINT32(state_sts, IntelHDAState), |
| 1201 |
VMSTATE_UINT32(int_ctl, IntelHDAState), |
| 1202 |
VMSTATE_UINT32(int_sts, IntelHDAState), |
| 1203 |
VMSTATE_UINT32(wall_clk, IntelHDAState), |
| 1204 |
VMSTATE_UINT32(corb_lbase, IntelHDAState), |
| 1205 |
VMSTATE_UINT32(corb_ubase, IntelHDAState), |
| 1206 |
VMSTATE_UINT32(corb_rp, IntelHDAState), |
| 1207 |
VMSTATE_UINT32(corb_wp, IntelHDAState), |
| 1208 |
VMSTATE_UINT32(corb_ctl, IntelHDAState), |
| 1209 |
VMSTATE_UINT32(corb_sts, IntelHDAState), |
| 1210 |
VMSTATE_UINT32(corb_size, IntelHDAState), |
| 1211 |
VMSTATE_UINT32(rirb_lbase, IntelHDAState), |
| 1212 |
VMSTATE_UINT32(rirb_ubase, IntelHDAState), |
| 1213 |
VMSTATE_UINT32(rirb_wp, IntelHDAState), |
| 1214 |
VMSTATE_UINT32(rirb_cnt, IntelHDAState), |
| 1215 |
VMSTATE_UINT32(rirb_ctl, IntelHDAState), |
| 1216 |
VMSTATE_UINT32(rirb_sts, IntelHDAState), |
| 1217 |
VMSTATE_UINT32(rirb_size, IntelHDAState), |
| 1218 |
VMSTATE_UINT32(dp_lbase, IntelHDAState), |
| 1219 |
VMSTATE_UINT32(dp_ubase, IntelHDAState), |
| 1220 |
VMSTATE_UINT32(icw, IntelHDAState), |
| 1221 |
VMSTATE_UINT32(irr, IntelHDAState), |
| 1222 |
VMSTATE_UINT32(ics, IntelHDAState), |
| 1223 |
VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, |
| 1224 |
vmstate_intel_hda_stream, |
| 1225 |
IntelHDAStream), |
| 1226 |
|
| 1227 |
/* additional state info */
|
| 1228 |
VMSTATE_UINT32(rirb_count, IntelHDAState), |
| 1229 |
VMSTATE_INT64(wall_base_ns, IntelHDAState), |
| 1230 |
|
| 1231 |
VMSTATE_END_OF_LIST() |
| 1232 |
} |
| 1233 |
}; |
| 1234 |
|
| 1235 |
static PCIDeviceInfo intel_hda_info = {
|
| 1236 |
.qdev.name = "intel-hda",
|
| 1237 |
.qdev.desc = "Intel HD Audio Controller",
|
| 1238 |
.qdev.size = sizeof(IntelHDAState),
|
| 1239 |
.qdev.vmsd = &vmstate_intel_hda, |
| 1240 |
.qdev.reset = intel_hda_reset, |
| 1241 |
.init = intel_hda_init, |
| 1242 |
.exit = intel_hda_exit, |
| 1243 |
.qdev.props = (Property[]) {
|
| 1244 |
DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), |
| 1245 |
DEFINE_PROP_END_OF_LIST(), |
| 1246 |
} |
| 1247 |
}; |
| 1248 |
|
| 1249 |
static void intel_hda_register(void) |
| 1250 |
{
|
| 1251 |
pci_qdev_register(&intel_hda_info); |
| 1252 |
} |
| 1253 |
device_init(intel_hda_register); |
| 1254 |
|
| 1255 |
/*
|
| 1256 |
* create intel hda controller with codec attached to it,
|
| 1257 |
* so '-soundhw hda' works.
|
| 1258 |
*/
|
| 1259 |
int intel_hda_and_codec_init(PCIBus *bus)
|
| 1260 |
{
|
| 1261 |
PCIDevice *controller; |
| 1262 |
BusState *hdabus; |
| 1263 |
DeviceState *codec; |
| 1264 |
|
| 1265 |
controller = pci_create_simple(bus, -1, "intel-hda"); |
| 1266 |
hdabus = QLIST_FIRST(&controller->qdev.child_bus); |
| 1267 |
codec = qdev_create(hdabus, "hda-duplex");
|
| 1268 |
qdev_init_nofail(codec); |
| 1269 |
return 0; |
| 1270 |
} |
| 1271 |
|