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Revision afa88c3a

IDafa88c3ae5fb6b2dce4e6221b4cf2664b05adcc5

Added by Aurelien Jarno over 10 years ago

target-mips: add Loongson support prefetch

Loongson CPU uses a load to zero register for prefetch.
Emulate it as a NOP.

Signed-off-by: Aurelien Jarno <>

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